2 * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
9 #include <dt-bindings/clock/berlin2q.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "skeleton.dtsi"
15 model = "Marvell Armada 1500 pro (BG2-Q) SoC";
16 compatible = "marvell,berlin2q", "marvell,berlin";
21 enable-method = "marvell,berlin-smp";
24 compatible = "arm,cortex-a9";
26 next-level-cache = <&l2>;
31 compatible = "arm,cortex-a9";
33 next-level-cache = <&l2>;
38 compatible = "arm,cortex-a9";
40 next-level-cache = <&l2>;
45 compatible = "arm,cortex-a9";
47 next-level-cache = <&l2>;
53 compatible = "fixed-clock";
55 clock-frequency = <25000000>;
59 compatible = "simple-bus";
63 ranges = <0 0xf7000000 0x1000000>;
64 interrupt-parent = <&gic>;
67 compatible = "arm,cortex-a9-pmu";
68 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
69 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
70 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
71 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
74 sdhci0: sdhci@ab0000 {
75 compatible = "mrvl,pxav3-mmc";
76 reg = <0xab0000 0x200>;
77 clocks = <&chip CLKID_SDIO1XIN>;
78 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
82 sdhci1: sdhci@ab0800 {
83 compatible = "mrvl,pxav3-mmc";
84 reg = <0xab0800 0x200>;
85 clocks = <&chip CLKID_SDIO1XIN>;
86 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
90 sdhci2: sdhci@ab1000 {
91 compatible = "mrvl,pxav3-mmc";
92 reg = <0xab1000 0x200>;
93 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
94 clocks = <&chip CLKID_NFC_ECC>, <&chip CLKID_NFC>;
95 clock-names = "io", "core";
99 l2: l2-cache-controller@ac0000 {
100 compatible = "arm,pl310-cache";
101 reg = <0xac0000 0x1000>;
103 arm,data-latency = <2 2 2>;
104 arm,tag-latency = <2 2 2>;
107 scu: snoop-control-unit@ad0000 {
108 compatible = "arm,cortex-a9-scu";
109 reg = <0xad0000 0x58>;
113 compatible = "arm,cortex-a9-twd-timer";
114 reg = <0xad0600 0x20>;
115 clocks = <&chip CLKID_TWD>;
116 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
119 gic: interrupt-controller@ad1000 {
120 compatible = "arm,cortex-a9-gic";
121 reg = <0xad1000 0x1000>, <0xad0100 0x100>;
122 interrupt-controller;
123 #interrupt-cells = <3>;
126 usb_phy2: phy@a2f400 {
127 compatible = "marvell,berlin2-usb-phy";
128 reg = <0xa2f400 0x128>;
130 resets = <&chip 0x104 14>;
135 compatible = "chipidea,usb2";
136 reg = <0xa30000 0x10000>;
137 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
138 clocks = <&chip CLKID_USB2>;
140 phy-names = "usb-phy";
144 usb_phy0: phy@b74000 {
145 compatible = "marvell,berlin2-usb-phy";
146 reg = <0xb74000 0x128>;
148 resets = <&chip 0x104 12>;
152 usb_phy1: phy@b78000 {
153 compatible = "marvell,berlin2-usb-phy";
154 reg = <0xb78000 0x128>;
156 resets = <&chip 0x104 13>;
160 eth0: ethernet@b90000 {
161 compatible = "marvell,pxa168-eth";
162 reg = <0xb90000 0x10000>;
163 clocks = <&chip CLKID_GETH0>;
164 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
165 /* set by bootloader */
166 local-mac-address = [00 00 00 00 00 00];
167 #address-cells = <1>;
169 phy-connection-type = "mii";
170 phy-handle = <ðphy0>;
173 ethphy0: ethernet-phy@0 {
179 compatible = "marvell,berlin-cpu-ctrl";
180 reg = <0xdd0000 0x10000>;
184 compatible = "simple-bus";
185 #address-cells = <1>;
188 ranges = <0 0xe80000 0x10000>;
189 interrupt-parent = <&aic>;
192 compatible = "snps,dw-apb-gpio";
193 reg = <0x0400 0x400>;
194 #address-cells = <1>;
198 compatible = "snps,dw-apb-gpio-port";
201 snps,nr-gpios = <32>;
203 interrupt-controller;
204 #interrupt-cells = <2>;
210 compatible = "snps,dw-apb-gpio";
211 reg = <0x0800 0x400>;
212 #address-cells = <1>;
216 compatible = "snps,dw-apb-gpio-port";
219 snps,nr-gpios = <32>;
221 interrupt-controller;
222 #interrupt-cells = <2>;
228 compatible = "snps,dw-apb-gpio";
229 reg = <0x0c00 0x400>;
230 #address-cells = <1>;
234 compatible = "snps,dw-apb-gpio-port";
237 snps,nr-gpios = <32>;
239 interrupt-controller;
240 #interrupt-cells = <2>;
246 compatible = "snps,dw-apb-gpio";
247 reg = <0x1000 0x400>;
248 #address-cells = <1>;
252 compatible = "snps,dw-apb-gpio-port";
255 snps,nr-gpios = <32>;
257 interrupt-controller;
258 #interrupt-cells = <2>;
264 compatible = "snps,designware-i2c";
265 #address-cells = <1>;
267 reg = <0x1400 0x100>;
268 interrupt-parent = <&aic>;
270 clocks = <&chip CLKID_CFG>;
271 pinctrl-0 = <&twsi0_pmux>;
272 pinctrl-names = "default";
277 compatible = "snps,designware-i2c";
278 #address-cells = <1>;
280 reg = <0x1800 0x100>;
281 interrupt-parent = <&aic>;
283 clocks = <&chip CLKID_CFG>;
284 pinctrl-0 = <&twsi1_pmux>;
285 pinctrl-names = "default";
290 compatible = "snps,dw-apb-timer";
292 clocks = <&chip CLKID_CFG>;
293 clock-names = "timer";
298 compatible = "snps,dw-apb-timer";
300 clocks = <&chip CLKID_CFG>;
301 clock-names = "timer";
305 compatible = "snps,dw-apb-timer";
307 clocks = <&chip CLKID_CFG>;
308 clock-names = "timer";
313 compatible = "snps,dw-apb-timer";
315 clocks = <&chip CLKID_CFG>;
316 clock-names = "timer";
321 compatible = "snps,dw-apb-timer";
323 clocks = <&chip CLKID_CFG>;
324 clock-names = "timer";
329 compatible = "snps,dw-apb-timer";
331 clocks = <&chip CLKID_CFG>;
332 clock-names = "timer";
337 compatible = "snps,dw-apb-timer";
339 clocks = <&chip CLKID_CFG>;
340 clock-names = "timer";
345 compatible = "snps,dw-apb-timer";
347 clocks = <&chip CLKID_CFG>;
348 clock-names = "timer";
352 aic: interrupt-controller@3800 {
353 compatible = "snps,dw-apb-ictl";
355 interrupt-controller;
356 #interrupt-cells = <1>;
357 interrupt-parent = <&gic>;
358 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
362 chip: chip-control@ea0000 {
363 compatible = "marvell,berlin2q-chip-ctrl";
366 reg = <0xea0000 0x400>, <0xdd0170 0x10>;
368 clock-names = "refclk";
370 twsi0_pmux: twsi0-pmux {
375 twsi1_pmux: twsi1-pmux {
382 compatible = "marvell,berlin2q-ahci", "generic-ahci";
383 reg = <0xe90000 0x1000>;
384 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
385 clocks = <&chip CLKID_SATA>;
386 #address-cells = <1>;
391 phys = <&sata_phy 0>;
397 phys = <&sata_phy 1>;
402 sata_phy: phy@e900a0 {
403 compatible = "marvell,berlin2q-sata-phy";
404 reg = <0xe900a0 0x200>;
405 clocks = <&chip CLKID_SATA>;
406 #address-cells = <1>;
421 compatible = "chipidea,usb2";
422 reg = <0xed0000 0x10000>;
423 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
424 clocks = <&chip CLKID_USB0>;
426 phy-names = "usb-phy";
431 compatible = "chipidea,usb2";
432 reg = <0xee0000 0x10000>;
433 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
434 clocks = <&chip CLKID_USB1>;
436 phy-names = "usb-phy";
441 compatible = "simple-bus";
442 #address-cells = <1>;
445 ranges = <0 0xfc0000 0x10000>;
446 interrupt-parent = <&sic>;
448 sm_gpio1: gpio@5000 {
449 compatible = "snps,dw-apb-gpio";
450 reg = <0x5000 0x400>;
451 #address-cells = <1>;
455 compatible = "snps,dw-apb-gpio-port";
458 snps,nr-gpios = <32>;
464 compatible = "snps,designware-i2c";
465 #address-cells = <1>;
467 reg = <0x7000 0x100>;
468 interrupt-parent = <&sic>;
471 pinctrl-0 = <&twsi2_pmux>;
472 pinctrl-names = "default";
477 compatible = "snps,designware-i2c";
478 #address-cells = <1>;
480 reg = <0x8000 0x100>;
481 interrupt-parent = <&sic>;
484 pinctrl-0 = <&twsi3_pmux>;
485 pinctrl-names = "default";
490 compatible = "snps,dw-apb-uart";
491 reg = <0x9000 0x100>;
492 interrupt-parent = <&sic>;
496 pinctrl-0 = <&uart0_pmux>;
497 pinctrl-names = "default";
502 compatible = "snps,dw-apb-uart";
503 reg = <0xa000 0x100>;
504 interrupt-parent = <&sic>;
508 pinctrl-0 = <&uart1_pmux>;
509 pinctrl-names = "default";
513 sm_gpio0: gpio@c000 {
514 compatible = "snps,dw-apb-gpio";
515 reg = <0xc000 0x400>;
516 #address-cells = <1>;
520 compatible = "snps,dw-apb-gpio-port";
523 snps,nr-gpios = <32>;
528 sysctrl: pin-controller@d000 {
529 compatible = "marvell,berlin2q-system-ctrl";
530 reg = <0xd000 0x100>;
532 uart0_pmux: uart0-pmux {
537 uart1_pmux: uart1-pmux {
542 twsi2_pmux: twsi2-pmux {
547 twsi3_pmux: twsi3-pmux {
553 sic: interrupt-controller@e000 {
554 compatible = "snps,dw-apb-ictl";
556 interrupt-controller;
557 #interrupt-cells = <1>;
558 interrupt-parent = <&gic>;
559 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;