1 /include/ "skeleton.dtsi"
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
6 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
9 compatible = "marvell,dove";
10 model = "Marvell Armada 88AP510 SoC";
11 interrupt-parent = <&intc>;
24 compatible = "marvell,pj4a", "marvell,sheeva-v7";
26 next-level-cache = <&l2>;
32 compatible = "marvell,tauros2-cache";
33 marvell,tauros2-cache-features = <0>;
37 compatible = "marvell,dove-mbus", "marvell,mbus", "simple-bus";
40 controller = <&mbusc>;
41 pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256M MEM space */
42 pcie-io-aperture = <0xf2000000 0x00200000>; /* 2M I/O space */
44 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x0100000 /* MBUS regs 1M */
45 MBUS_ID(0xf0, 0x02) 0 0xf1800000 0x1000000 /* AXI regs 16M */
46 MBUS_ID(0x01, 0xfd) 0 0xf8000000 0x8000000 /* BootROM 128M */
47 MBUS_ID(0x03, 0x01) 0 0xc8000000 0x0100000 /* CESA SRAM 1M */
48 MBUS_ID(0x0d, 0x00) 0 0xf0000000 0x0100000>; /* PMU SRAM 1M */
50 pcie: pcie-controller {
51 compatible = "marvell,dove-pcie";
58 bus-range = <0x00 0xff>;
60 ranges = <0x82000000 0x0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x2000
61 0x82000000 0x0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x2000
62 0x82000000 0x1 0x0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 Mem */
63 0x81000000 0x1 0x0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 I/O */
64 0x82000000 0x2 0x0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 Mem */
65 0x81000000 0x2 0x0 MBUS_ID(0x08, 0xe0) 0 1 0>; /* Port 1.0 I/O */
70 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
71 reg = <0x0800 0 0 0 0>;
72 clocks = <&gate_clk 4>;
73 marvell,pcie-port = <0>;
77 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
78 0x81000000 0 0 0x81000000 0x1 0 1 0>;
80 #interrupt-cells = <1>;
81 interrupt-map-mask = <0 0 0 0>;
82 interrupt-map = <0 0 0 0 &intc 16>;
88 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
89 reg = <0x1000 0 0 0 0>;
90 clocks = <&gate_clk 5>;
91 marvell,pcie-port = <1>;
95 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
96 0x81000000 0 0 0x81000000 0x2 0 1 0>;
98 #interrupt-cells = <1>;
99 interrupt-map-mask = <0 0 0 0>;
100 interrupt-map = <0 0 0 0 &intc 18>;
105 compatible = "simple-bus";
106 #address-cells = <1>;
108 ranges = <0x00000000 MBUS_ID(0xf0, 0x01) 0 0x0100000 /* MBUS regs 1M */
109 0x00800000 MBUS_ID(0xf0, 0x02) 0 0x1000000 /* AXI regs 16M */
110 0xffffe000 MBUS_ID(0x03, 0x01) 0 0x0000800 /* CESA SRAM 2k */
111 0xfffff000 MBUS_ID(0x0d, 0x00) 0 0x0000800>; /* PMU SRAM 2k */
113 spi0: spi-ctrl@10600 {
114 compatible = "marvell,orion-spi";
115 #address-cells = <1>;
119 reg = <0x10600 0x28>;
120 clocks = <&core_clk 0>;
121 pinctrl-0 = <&pmx_spi0>;
122 pinctrl-names = "default";
126 i2c0: i2c-ctrl@11000 {
127 compatible = "marvell,mv64xxx-i2c";
128 reg = <0x11000 0x20>;
129 #address-cells = <1>;
132 clock-frequency = <400000>;
134 clocks = <&core_clk 0>;
138 uart0: serial@12000 {
139 compatible = "ns16550a";
140 reg = <0x12000 0x100>;
143 clocks = <&core_clk 0>;
147 uart1: serial@12100 {
148 compatible = "ns16550a";
149 reg = <0x12100 0x100>;
152 clocks = <&core_clk 0>;
153 pinctrl-0 = <&pmx_uart1>;
154 pinctrl-names = "default";
158 uart2: serial@12200 {
159 compatible = "ns16550a";
160 reg = <0x12200 0x100>;
163 clocks = <&core_clk 0>;
167 uart3: serial@12300 {
168 compatible = "ns16550a";
169 reg = <0x12300 0x100>;
172 clocks = <&core_clk 0>;
176 spi1: spi-ctrl@14600 {
177 compatible = "marvell,orion-spi";
178 #address-cells = <1>;
182 reg = <0x14600 0x28>;
183 clocks = <&core_clk 0>;
187 mbusc: mbus-ctrl@20000 {
188 compatible = "marvell,mbus-controller";
189 reg = <0x20000 0x80>, <0x800100 0x8>;
192 sysc: system-ctrl@20000 {
193 compatible = "marvell,orion-system-controller";
194 reg = <0x20000 0x110>;
197 bridge_intc: bridge-interrupt-ctrl@20110 {
198 compatible = "marvell,orion-bridge-intc";
199 interrupt-controller;
200 #interrupt-cells = <1>;
203 marvell,#interrupts = <5>;
206 intc: main-interrupt-ctrl@20200 {
207 compatible = "marvell,orion-intc";
208 interrupt-controller;
209 #interrupt-cells = <1>;
210 reg = <0x20200 0x10>, <0x20210 0x10>;
214 compatible = "marvell,orion-timer";
215 reg = <0x20300 0x20>;
216 interrupt-parent = <&bridge_intc>;
217 interrupts = <1>, <2>;
218 clocks = <&core_clk 0>;
222 compatible = "marvell,orion-wdt";
223 reg = <0x20300 0x28>, <0x20108 0x4>;
224 interrupt-parent = <&bridge_intc>;
226 clocks = <&core_clk 0>;
229 crypto: crypto-engine@30000 {
230 compatible = "marvell,orion-crypto";
231 reg = <0x30000 0x10000>,
233 reg-names = "regs", "sram";
235 clocks = <&gate_clk 15>;
239 ehci0: usb-host@50000 {
240 compatible = "marvell,orion-ehci";
241 reg = <0x50000 0x1000>;
243 clocks = <&gate_clk 0>;
247 ehci1: usb-host@51000 {
248 compatible = "marvell,orion-ehci";
249 reg = <0x51000 0x1000>;
251 clocks = <&gate_clk 1>;
255 xor0: dma-engine@60800 {
256 compatible = "marvell,orion-xor";
259 clocks = <&gate_clk 23>;
275 xor1: dma-engine@60900 {
276 compatible = "marvell,orion-xor";
279 clocks = <&gate_clk 24>;
295 sdio1: sdio-host@90000 {
296 compatible = "marvell,dove-sdhci";
297 reg = <0x90000 0x100>;
298 interrupts = <36>, <38>;
299 clocks = <&gate_clk 9>;
300 pinctrl-0 = <&pmx_sdio1>;
301 pinctrl-names = "default";
305 eth: ethernet-ctrl@72000 {
306 compatible = "marvell,orion-eth";
307 #address-cells = <1>;
309 reg = <0x72000 0x4000>;
310 clocks = <&gate_clk 2>;
311 marvell,tx-checksum-limit = <1600>;
315 compatible = "marvell,orion-eth-port";
318 /* overwrite MAC address in bootloader */
319 local-mac-address = [00 00 00 00 00 00];
320 phy-handle = <ðphy>;
324 mdio: mdio-bus@72004 {
325 compatible = "marvell,orion-mdio";
326 #address-cells = <1>;
328 reg = <0x72004 0x84>;
330 clocks = <&gate_clk 2>;
333 ethphy: ethernet-phy {
334 /* set phy address in board file */
338 sdio0: sdio-host@92000 {
339 compatible = "marvell,dove-sdhci";
340 reg = <0x92000 0x100>;
341 interrupts = <35>, <37>;
342 clocks = <&gate_clk 8>;
343 pinctrl-0 = <&pmx_sdio0>;
344 pinctrl-names = "default";
348 sata0: sata-host@a0000 {
349 compatible = "marvell,orion-sata";
350 reg = <0xa0000 0x2400>;
352 clocks = <&gate_clk 3>;
359 sata_phy0: sata-phy@a2000 {
360 compatible = "marvell,mvebu-sata-phy";
361 reg = <0xa2000 0x0334>;
362 clocks = <&gate_clk 3>;
363 clock-names = "sata";
368 audio0: audio-controller@b0000 {
369 compatible = "marvell,dove-audio";
370 reg = <0xb0000 0x2210>;
371 interrupts = <19>, <20>;
372 clocks = <&gate_clk 12>;
373 clock-names = "internal";
377 audio1: audio-controller@b4000 {
378 compatible = "marvell,dove-audio";
379 reg = <0xb4000 0x2210>;
380 interrupts = <21>, <22>;
381 clocks = <&gate_clk 13>;
382 clock-names = "internal";
386 thermal: thermal-diode@d001c {
387 compatible = "marvell,dove-thermal";
388 reg = <0xd001c 0x0c>, <0xd005c 0x08>;
391 gate_clk: clock-gating-ctrl@d0038 {
392 compatible = "marvell,dove-gating-clock";
394 clocks = <&core_clk 0>;
398 pinctrl: pin-ctrl@d0200 {
399 compatible = "marvell,dove-pinctrl";
400 reg = <0xd0200 0x14>,
402 clocks = <&gate_clk 22>;
404 pmx_gpio_0: pmx-gpio-0 {
405 marvell,pins = "mpp0";
406 marvell,function = "gpio";
409 pmx_gpio_1: pmx-gpio-1 {
410 marvell,pins = "mpp1";
411 marvell,function = "gpio";
414 pmx_gpio_2: pmx-gpio-2 {
415 marvell,pins = "mpp2";
416 marvell,function = "gpio";
419 pmx_gpio_3: pmx-gpio-3 {
420 marvell,pins = "mpp3";
421 marvell,function = "gpio";
424 pmx_gpio_4: pmx-gpio-4 {
425 marvell,pins = "mpp4";
426 marvell,function = "gpio";
429 pmx_gpio_5: pmx-gpio-5 {
430 marvell,pins = "mpp5";
431 marvell,function = "gpio";
434 pmx_gpio_6: pmx-gpio-6 {
435 marvell,pins = "mpp6";
436 marvell,function = "gpio";
439 pmx_gpio_7: pmx-gpio-7 {
440 marvell,pins = "mpp7";
441 marvell,function = "gpio";
444 pmx_gpio_8: pmx-gpio-8 {
445 marvell,pins = "mpp8";
446 marvell,function = "gpio";
449 pmx_gpio_9: pmx-gpio-9 {
450 marvell,pins = "mpp9";
451 marvell,function = "gpio";
454 pmx_pcie1_clkreq: pmx-pcie1-clkreq {
455 marvell,pins = "mpp9";
456 marvell,function = "pex1";
459 pmx_gpio_10: pmx-gpio-10 {
460 marvell,pins = "mpp10";
461 marvell,function = "gpio";
464 pmx_gpio_11: pmx-gpio-11 {
465 marvell,pins = "mpp11";
466 marvell,function = "gpio";
469 pmx_pcie0_clkreq: pmx-pcie0-clkreq {
470 marvell,pins = "mpp11";
471 marvell,function = "pex0";
474 pmx_gpio_12: pmx-gpio-12 {
475 marvell,pins = "mpp12";
476 marvell,function = "gpio";
479 pmx_gpio_13: pmx-gpio-13 {
480 marvell,pins = "mpp13";
481 marvell,function = "gpio";
484 pmx_audio1_extclk: pmx-audio1-extclk {
485 marvell,pins = "mpp13";
486 marvell,function = "audio1";
489 pmx_gpio_14: pmx-gpio-14 {
490 marvell,pins = "mpp14";
491 marvell,function = "gpio";
494 pmx_gpio_15: pmx-gpio-15 {
495 marvell,pins = "mpp15";
496 marvell,function = "gpio";
499 pmx_gpio_16: pmx-gpio-16 {
500 marvell,pins = "mpp16";
501 marvell,function = "gpio";
504 pmx_gpio_17: pmx-gpio-17 {
505 marvell,pins = "mpp17";
506 marvell,function = "gpio";
509 pmx_gpio_18: pmx-gpio-18 {
510 marvell,pins = "mpp18";
511 marvell,function = "gpio";
514 pmx_gpio_19: pmx-gpio-19 {
515 marvell,pins = "mpp19";
516 marvell,function = "gpio";
519 pmx_gpio_20: pmx-gpio-20 {
520 marvell,pins = "mpp20";
521 marvell,function = "gpio";
524 pmx_gpio_21: pmx-gpio-21 {
525 marvell,pins = "mpp21";
526 marvell,function = "gpio";
529 pmx_camera: pmx-camera {
530 marvell,pins = "mpp_camera";
531 marvell,function = "camera";
534 pmx_camera_gpio: pmx-camera-gpio {
535 marvell,pins = "mpp_camera";
536 marvell,function = "gpio";
539 pmx_sdio0: pmx-sdio0 {
540 marvell,pins = "mpp_sdio0";
541 marvell,function = "sdio0";
544 pmx_sdio0_gpio: pmx-sdio0-gpio {
545 marvell,pins = "mpp_sdio0";
546 marvell,function = "gpio";
549 pmx_sdio1: pmx-sdio1 {
550 marvell,pins = "mpp_sdio1";
551 marvell,function = "sdio1";
554 pmx_sdio1_gpio: pmx-sdio1-gpio {
555 marvell,pins = "mpp_sdio1";
556 marvell,function = "gpio";
559 pmx_audio1_gpio: pmx-audio1-gpio {
560 marvell,pins = "mpp_audio1";
561 marvell,function = "gpio";
564 pmx_audio1_i2s1_spdifo: pmx-audio1-i2s1-spdifo {
565 marvell,pins = "mpp_audio1";
566 marvell,function = "i2s1/spdifo";
570 marvell,pins = "mpp_spi0";
571 marvell,function = "spi0";
574 pmx_spi0_gpio: pmx-spi0-gpio {
575 marvell,pins = "mpp_spi0";
576 marvell,function = "gpio";
579 pmx_spi1_4_7: pmx-spi1-4-7 {
580 marvell,pins = "mpp4", "mpp5",
582 marvell,function = "spi1";
585 pmx_spi1_20_23: pmx-spi1-20-23 {
586 marvell,pins = "mpp20", "mpp21",
588 marvell,function = "spi1";
591 pmx_uart1: pmx-uart1 {
592 marvell,pins = "mpp_uart1";
593 marvell,function = "uart1";
596 pmx_uart1_gpio: pmx-uart1-gpio {
597 marvell,pins = "mpp_uart1";
598 marvell,function = "gpio";
602 marvell,pins = "mpp_nand";
603 marvell,function = "nand";
606 pmx_nand_gpo: pmx-nand-gpo {
607 marvell,pins = "mpp_nand";
608 marvell,function = "gpo";
612 marvell,pins = "mpp17", "mpp19";
613 marvell,function = "twsi";
617 marvell,pins = "mpp_audio1";
618 marvell,function = "twsi";
621 pmx_ssp_i2c2: pmx-ssp-i2c2 {
622 marvell,pins = "mpp_audio1";
623 marvell,function = "ssp/twsi";
626 pmx_i2cmux_0: pmx-i2cmux-0 {
627 marvell,pins = "twsi";
628 marvell,function = "twsi-opt1";
631 pmx_i2cmux_1: pmx-i2cmux-1 {
632 marvell,pins = "twsi";
633 marvell,function = "twsi-opt2";
636 pmx_i2cmux_2: pmx-i2cmux-2 {
637 marvell,pins = "twsi";
638 marvell,function = "twsi-opt3";
642 core_clk: core-clocks@d0214 {
643 compatible = "marvell,dove-core-clock";
648 gpio0: gpio-ctrl@d0400 {
649 compatible = "marvell,orion-gpio";
652 reg = <0xd0400 0x20>;
654 interrupt-controller;
655 #interrupt-cells = <2>;
656 interrupts = <12>, <13>, <14>, <60>;
659 gpio1: gpio-ctrl@d0420 {
660 compatible = "marvell,orion-gpio";
663 reg = <0xd0420 0x20>;
665 interrupt-controller;
666 #interrupt-cells = <2>;
670 rtc: real-time-clock@d8500 {
671 compatible = "marvell,orion-rtc";
672 reg = <0xd8500 0x20>;
675 gconf: global-config@e802c {
676 compatible = "marvell,dove-global-config",
678 reg = <0xe802c 0x14>;
681 gpio2: gpio-ctrl@e8400 {
682 compatible = "marvell,orion-gpio";
685 reg = <0xe8400 0x0c>;
689 lcd1: lcd-controller@810000 {
690 compatible = "marvell,dove-lcd";
691 reg = <0x810000 0x1000>;
696 lcd0: lcd-controller@820000 {
697 compatible = "marvell,dove-lcd";
698 reg = <0x820000 0x1000>;