2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 #include "dra74x.dtsi"
14 compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
17 device_type = "memory";
18 reg = <0x80000000 0x60000000>; /* 1536 MB */
21 mmc2_3v3: fixedregulator-mmc2 {
22 compatible = "regulator-fixed";
23 regulator-name = "mmc2_3v3";
24 regulator-min-microvolt = <3300000>;
25 regulator-max-microvolt = <3300000>;
30 i2c1_pins: pinmux_i2c1_pins {
31 pinctrl-single,pins = <
32 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda */
33 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl */
37 i2c2_pins: pinmux_i2c2_pins {
38 pinctrl-single,pins = <
39 0x408 (PIN_INPUT | MUX_MODE0) /* i2c2_sda */
40 0x40c (PIN_INPUT | MUX_MODE0) /* i2c2_scl */
44 i2c3_pins: pinmux_i2c3_pins {
45 pinctrl-single,pins = <
46 0x410 (PIN_INPUT | MUX_MODE0) /* i2c3_sda */
47 0x414 (PIN_INPUT | MUX_MODE0) /* i2c3_scl */
51 mcspi1_pins: pinmux_mcspi1_pins {
52 pinctrl-single,pins = <
53 0x3a4 (PIN_INPUT | MUX_MODE0) /* spi2_clk */
54 0x3a8 (PIN_INPUT | MUX_MODE0) /* spi2_d1 */
55 0x3ac (PIN_INPUT | MUX_MODE0) /* spi2_d0 */
56 0x3b0 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */
57 0x3b4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs1 */
58 0x3b8 (PIN_INPUT_SLEW | MUX_MODE6) /* spi2_cs2 */
59 0x3bc (PIN_INPUT_SLEW | MUX_MODE6) /* spi2_cs3 */
63 mcspi2_pins: pinmux_mcspi2_pins {
64 pinctrl-single,pins = <
65 0x3c0 (PIN_INPUT | MUX_MODE0) /* spi2_sclk */
66 0x3c4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
67 0x3c8 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
68 0x3cc (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */
72 uart1_pins: pinmux_uart1_pins {
73 pinctrl-single,pins = <
74 0x3e0 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */
75 0x3e4 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */
76 0x3e8 (PIN_INPUT | MUX_MODE3) /* uart1_ctsn */
77 0x3ec (PIN_INPUT | MUX_MODE3) /* uart1_rtsn */
81 uart2_pins: pinmux_uart2_pins {
82 pinctrl-single,pins = <
83 0x3f0 (PIN_INPUT | MUX_MODE0) /* uart2_rxd */
84 0x3f4 (PIN_INPUT | MUX_MODE0) /* uart2_txd */
85 0x3f8 (PIN_INPUT | MUX_MODE0) /* uart2_ctsn */
86 0x3fc (PIN_INPUT | MUX_MODE0) /* uart2_rtsn */
90 uart3_pins: pinmux_uart3_pins {
91 pinctrl-single,pins = <
92 0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */
93 0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
97 qspi1_pins: pinmux_qspi1_pins {
98 pinctrl-single,pins = <
99 0x4c (PIN_INPUT | MUX_MODE1) /* gpmc_a3.qspi1_cs2 */
100 0x50 (PIN_INPUT | MUX_MODE1) /* gpmc_a4.qspi1_cs3 */
101 0x74 (PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
102 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */
103 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */
104 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
105 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */
106 0x88 (PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
107 0xb8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */
108 0xbc (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs3.qspi1_cs1 */
112 usb1_pins: pinmux_usb1_pins {
113 pinctrl-single,pins = <
114 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
118 usb2_pins: pinmux_usb2_pins {
119 pinctrl-single,pins = <
120 0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
124 nand_flash_x16: nand_flash_x16 {
125 /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
126 * So NAND flash requires following switch settings:
127 * SW5.9 (GPMC_WPN) = LOW
128 * SW5.1 (NAND_BOOTn) = HIGH */
129 pinctrl-single,pins = <
130 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
131 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
132 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
133 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
134 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
135 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
136 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
137 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
138 0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
139 0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
140 0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
141 0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
142 0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
143 0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
144 0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
145 0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
146 0xd8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0 */
147 0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
148 0xb4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0 */
149 0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
150 0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
151 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */
158 pinctrl-names = "default";
159 pinctrl-0 = <&i2c1_pins>;
160 clock-frequency = <400000>;
162 tps659038: tps659038@58 {
163 compatible = "ti,tps659038";
167 compatible = "ti,tps659038-pmic";
170 smps123_reg: smps123 {
172 regulator-name = "smps123";
173 regulator-min-microvolt = < 850000>;
174 regulator-max-microvolt = <1250000>;
181 regulator-name = "smps45";
182 regulator-min-microvolt = < 850000>;
183 regulator-max-microvolt = <1150000>;
188 /* VDD_GPU - over VDD_SMPS6 */
189 regulator-name = "smps6";
190 regulator-min-microvolt = <850000>;
191 regulator-max-microvolt = <12500000>;
197 regulator-name = "smps7";
198 regulator-min-microvolt = <850000>;
199 regulator-max-microvolt = <1030000>;
206 regulator-name = "smps8";
207 regulator-min-microvolt = < 850000>;
208 regulator-max-microvolt = <1250000>;
214 regulator-name = "smps9";
215 regulator-min-microvolt = <1800000>;
216 regulator-max-microvolt = <1800000>;
222 /* LDO1_OUT --> SDIO */
223 regulator-name = "ldo1";
224 regulator-min-microvolt = <1800000>;
225 regulator-max-microvolt = <3300000>;
231 /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
232 regulator-name = "ldo2";
233 regulator-min-microvolt = <3300000>;
234 regulator-max-microvolt = <3300000>;
240 regulator-name = "ldo3";
241 regulator-min-microvolt = <1800000>;
242 regulator-max-microvolt = <1800000>;
248 regulator-name = "ldo9";
249 regulator-min-microvolt = <1050000>;
250 regulator-max-microvolt = <1050000>;
256 regulator-name = "ldoln";
257 regulator-min-microvolt = <1800000>;
258 regulator-max-microvolt = <1800000>;
264 /* VDDA_3V_USB: VDDA_USBHS33 */
265 regulator-name = "ldousb";
266 regulator-min-microvolt = <3300000>;
267 regulator-max-microvolt = <3300000>;
277 pinctrl-names = "default";
278 pinctrl-0 = <&i2c2_pins>;
279 clock-frequency = <400000>;
284 pinctrl-names = "default";
285 pinctrl-0 = <&i2c3_pins>;
286 clock-frequency = <3400000>;
291 pinctrl-names = "default";
292 pinctrl-0 = <&mcspi1_pins>;
297 pinctrl-names = "default";
298 pinctrl-0 = <&mcspi2_pins>;
303 pinctrl-names = "default";
304 pinctrl-0 = <&uart1_pins>;
309 pinctrl-names = "default";
310 pinctrl-0 = <&uart2_pins>;
315 pinctrl-names = "default";
316 pinctrl-0 = <&uart3_pins>;
321 vmmc-supply = <&ldo1_reg>;
327 vmmc-supply = <&mmc2_3v3>;
332 cpu0-supply = <&smps123_reg>;
337 pinctrl-names = "default";
338 pinctrl-0 = <&qspi1_pins>;
340 spi-max-frequency = <48000000>;
342 compatible = "s25fl256s1";
343 spi-max-frequency = <48000000>;
345 spi-tx-bus-width = <1>;
346 spi-rx-bus-width = <4>;
349 #address-cells = <1>;
352 /* MTD partition table.
353 * The ROM checks the first four physical blocks
354 * for a valid file to boot and the flash here is
359 reg = <0x00000000 0x000010000>;
362 label = "QSPI.SPL.backup1";
363 reg = <0x00010000 0x00010000>;
366 label = "QSPI.SPL.backup2";
367 reg = <0x00020000 0x00010000>;
370 label = "QSPI.SPL.backup3";
371 reg = <0x00030000 0x00010000>;
374 label = "QSPI.u-boot";
375 reg = <0x00040000 0x00100000>;
378 label = "QSPI.u-boot-spl-os";
379 reg = <0x00140000 0x00010000>;
382 label = "QSPI.u-boot-env";
383 reg = <0x00150000 0x00010000>;
386 label = "QSPI.u-boot-env.backup1";
387 reg = <0x00160000 0x0010000>;
390 label = "QSPI.kernel";
391 reg = <0x00170000 0x0800000>;
394 label = "QSPI.file-system";
395 reg = <0x00970000 0x01690000>;
401 dr_mode = "peripheral";
402 pinctrl-names = "default";
403 pinctrl-0 = <&usb1_pins>;
408 pinctrl-names = "default";
409 pinctrl-0 = <&usb2_pins>;
418 pinctrl-names = "default";
419 pinctrl-0 = <&nand_flash_x16>;
420 ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
422 reg = <0 0 4>; /* device IO registers */
423 ti,nand-ecc-opt = "bch8";
425 nand-bus-width = <16>;
426 gpmc,device-width = <2>;
427 gpmc,sync-clk-ps = <0>;
429 gpmc,cs-rd-off-ns = <40>;
430 gpmc,cs-wr-off-ns = <40>;
431 gpmc,adv-on-ns = <0>;
432 gpmc,adv-rd-off-ns = <30>;
433 gpmc,adv-wr-off-ns = <30>;
435 gpmc,we-off-ns = <25>;
437 gpmc,oe-off-ns = <20>;
438 gpmc,access-ns = <20>;
439 gpmc,wr-access-ns = <40>;
440 gpmc,rd-cycle-ns = <40>;
441 gpmc,wr-cycle-ns = <40>;
445 gpmc,bus-turnaround-ns = <0>;
446 gpmc,cycle2cycle-delay-ns = <0>;
447 gpmc,clk-activation-ns = <0>;
448 gpmc,wait-monitoring-ns = <0>;
449 gpmc,wr-data-mux-bus-ns = <0>;
450 /* MTD partition table */
451 /* All SPL-* partitions are sized to minimal length
452 * which can be independently programmable. For
453 * NAND flash this is equal to size of erase-block */
454 #address-cells = <1>;
458 reg = <0x00000000 0x000020000>;
461 label = "NAND.SPL.backup1";
462 reg = <0x00020000 0x00020000>;
465 label = "NAND.SPL.backup2";
466 reg = <0x00040000 0x00020000>;
469 label = "NAND.SPL.backup3";
470 reg = <0x00060000 0x00020000>;
473 label = "NAND.u-boot-spl-os";
474 reg = <0x00080000 0x00040000>;
477 label = "NAND.u-boot";
478 reg = <0x000c0000 0x00100000>;
481 label = "NAND.u-boot-env";
482 reg = <0x001c0000 0x00020000>;
485 label = "NAND.u-boot-env";
486 reg = <0x001e0000 0x00020000>;
489 label = "NAND.kernel";
490 reg = <0x00200000 0x00800000>;
493 label = "NAND.file-system";
494 reg = <0x00a00000 0x0f600000>;