2 * Device Tree Source for the EMEV2 SoC
4 * Copyright (C) 2012 Renesas Solutions Corp.
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 #include "skeleton.dtsi"
12 #include <dt-bindings/interrupt-controller/irq.h>
15 compatible = "renesas,emev2";
16 interrupt-parent = <&gic>;
32 compatible = "arm,cortex-a9";
34 clock-frequency = <533000000>;
38 compatible = "arm,cortex-a9";
40 clock-frequency = <533000000>;
44 gic: interrupt-controller@e0020000 {
45 compatible = "arm,cortex-a9-gic";
47 #interrupt-cells = <3>;
48 reg = <0xe0028000 0x1000>,
53 compatible = "arm,cortex-a9-pmu";
54 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
55 <0 121 IRQ_TYPE_LEVEL_HIGH>;
59 compatible = "renesas,emev2-smu";
60 reg = <0xe0110000 0x10000>;
65 compatible = "fixed-clock";
66 clock-frequency = <32768>;
70 compatible = "fixed-factor-clock";
76 usia_u0_sclkdiv: usia_u0_sclkdiv {
77 compatible = "renesas,emev2-smu-clkdiv";
82 usib_u1_sclkdiv: usib_u1_sclkdiv {
83 compatible = "renesas,emev2-smu-clkdiv";
88 usib_u2_sclkdiv: usib_u2_sclkdiv {
89 compatible = "renesas,emev2-smu-clkdiv";
94 usib_u3_sclkdiv: usib_u3_sclkdiv {
95 compatible = "renesas,emev2-smu-clkdiv";
100 usia_u0_sclk: usia_u0_sclk {
101 compatible = "renesas,emev2-smu-gclk";
103 clocks = <&usia_u0_sclkdiv>;
106 usib_u1_sclk: usib_u1_sclk {
107 compatible = "renesas,emev2-smu-gclk";
109 clocks = <&usib_u1_sclkdiv>;
112 usib_u2_sclk: usib_u2_sclk {
113 compatible = "renesas,emev2-smu-gclk";
115 clocks = <&usib_u2_sclkdiv>;
118 usib_u3_sclk: usib_u3_sclk {
119 compatible = "renesas,emev2-smu-gclk";
121 clocks = <&usib_u3_sclkdiv>;
125 compatible = "renesas,emev2-smu-gclk";
133 compatible = "renesas,em-sti";
134 reg = <0xe0180000 0x54>;
135 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
136 clocks = <&sti_sclk>;
137 clock-names = "sclk";
141 compatible = "renesas,em-uart";
142 reg = <0xe1020000 0x38>;
143 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
144 clocks = <&usia_u0_sclk>;
145 clock-names = "sclk";
149 compatible = "renesas,em-uart";
150 reg = <0xe1030000 0x38>;
151 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
152 clocks = <&usib_u1_sclk>;
153 clock-names = "sclk";
157 compatible = "renesas,em-uart";
158 reg = <0xe1040000 0x38>;
159 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
160 clocks = <&usib_u2_sclk>;
161 clock-names = "sclk";
165 compatible = "renesas,em-uart";
166 reg = <0xe1050000 0x38>;
167 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
168 clocks = <&usib_u3_sclk>;
169 clock-names = "sclk";
172 gpio0: gpio@e0050000 {
173 compatible = "renesas,em-gio";
174 reg = <0xe0050000 0x2c>, <0xe0050040 0x20>;
175 interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>,
176 <0 68 IRQ_TYPE_LEVEL_HIGH>;
180 interrupt-controller;
181 #interrupt-cells = <2>;
183 gpio1: gpio@e0050080 {
184 compatible = "renesas,em-gio";
185 reg = <0xe0050080 0x2c>, <0xe00500c0 0x20>;
186 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>,
187 <0 70 IRQ_TYPE_LEVEL_HIGH>;
191 interrupt-controller;
192 #interrupt-cells = <2>;
194 gpio2: gpio@e0050100 {
195 compatible = "renesas,em-gio";
196 reg = <0xe0050100 0x2c>, <0xe0050140 0x20>;
197 interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>,
198 <0 72 IRQ_TYPE_LEVEL_HIGH>;
202 interrupt-controller;
203 #interrupt-cells = <2>;
205 gpio3: gpio@e0050180 {
206 compatible = "renesas,em-gio";
207 reg = <0xe0050180 0x2c>, <0xe00501c0 0x20>;
208 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>,
209 <0 74 IRQ_TYPE_LEVEL_HIGH>;
213 interrupt-controller;
214 #interrupt-cells = <2>;
216 gpio4: gpio@e0050200 {
217 compatible = "renesas,em-gio";
218 reg = <0xe0050200 0x2c>, <0xe0050240 0x20>;
219 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>,
220 <0 76 IRQ_TYPE_LEVEL_HIGH>;
224 interrupt-controller;
225 #interrupt-cells = <2>;