arch/arm/boot/dts/emev2.dtsi

   1 /*
   2  * Device Tree Source for the EMEV2 SoC
   3  *
   4  * Copyright (C) 2012 Renesas Solutions Corp.
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2.  This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 /include/ "skeleton.dtsi"
  12
  13 / {
  14         compatible = "renesas,emev2";
  15         interrupt-parent = <&gic>;
  16
  17         aliases {
  18                 gpio0 = &gpio0;
  19                 gpio1 = &gpio1;
  20                 gpio2 = &gpio2;
  21                 gpio3 = &gpio3;
  22                 gpio4 = &gpio4;
  23         };
  24
  25         cpus {
  26                 #address-cells = <1>;
  27                 #size-cells = <0>;
  28
  29                 cpu@0 {
  30                         device_type = "cpu";
  31                         compatible = "arm,cortex-a9";
  32                         reg = <0>;
  33                 };
  34                 cpu@1 {
  35                         device_type = "cpu";
  36                         compatible = "arm,cortex-a9";
  37                         reg = <1>;
  38                 };
  39         };
  40
  41         gic: interrupt-controller@e0020000 {
  42                 compatible = "arm,cortex-a9-gic";
  43                 interrupt-controller;
  44                 #interrupt-cells = <3>;
  45                 reg = <0xe0028000 0x1000>,
  46                       <0xe0020000 0x0100>;
  47         };
  48
  49         sti@e0180000 {
  50                 compatible = "renesas,em-sti";
  51                 reg = <0xe0180000 0x54>;
  52                 interrupts = <0 125 0>;
  53         };
  54
  55         uart@e1020000 {
  56                 compatible = "renesas,em-uart";
  57                 reg = <0xe1020000 0x38>;
  58                 interrupts = <0 8 0>;
  59         };
  60
  61         uart@e1030000 {
  62                 compatible = "renesas,em-uart";
  63                 reg = <0xe1030000 0x38>;
  64                 interrupts = <0 9 0>;
  65         };
  66
  67         uart@e1040000 {
  68                 compatible = "renesas,em-uart";
  69                 reg = <0xe1040000 0x38>;
  70                 interrupts = <0 10 0>;
  71         };
  72
  73         uart@e1050000 {
  74                 compatible = "renesas,em-uart";
  75                 reg = <0xe1050000 0x38>;
  76                 interrupts = <0 11 0>;
  77         };
  78
  79         gpio0: gpio@e0050000 {
  80                 compatible = "renesas,em-gio";
  81                 reg = <0xe0050000 0x2c>, <0xe0050040 0x20>;
  82                 interrupts = <0 67 0>, <0 68 0>;
  83                 gpio-controller;
  84                 #gpio-cells = <2>;
  85                 ngpios = <32>;
  86                 interrupt-controller;
  87                 #interrupt-cells = <2>;
  88         };
  89         gpio1: gpio@e0050080 {
  90                 compatible = "renesas,em-gio";
  91                 reg = <0xe0050080 0x2c>, <0xe00500c0 0x20>;
  92                 interrupts = <0 69 0>, <0 70 0>;
  93                 gpio-controller;
  94                 #gpio-cells = <2>;
  95                 ngpios = <32>;
  96                 interrupt-controller;
  97                 #interrupt-cells = <2>;
  98         };
  99         gpio2: gpio@e0050100 {
 100                 compatible = "renesas,em-gio";
 101                 reg = <0xe0050100 0x2c>, <0xe0050140 0x20>;
 102                 interrupts = <0 71 0>, <0 72 0>;
 103                 gpio-controller;
 104                 #gpio-cells = <2>;
 105                 ngpios = <32>;
 106                 interrupt-controller;
 107                 #interrupt-cells = <2>;
 108         };
 109         gpio3: gpio@e0050180 {
 110                 compatible = "renesas,em-gio";
 111                 reg = <0xe0050180 0x2c>, <0xe00501c0 0x20>;
 112                 interrupts = <0 73 0>, <0 74 0>;
 113                 gpio-controller;
 114                 #gpio-cells = <2>;
 115                 ngpios = <32>;
 116                 interrupt-controller;
 117                 #interrupt-cells = <2>;
 118         };
 119         gpio4: gpio@e0050200 {
 120                 compatible = "renesas,em-gio";
 121                 reg = <0xe0050200 0x2c>, <0xe0050240 0x20>;
 122                 interrupts = <0 75 0>, <0 76 0>;
 123                 gpio-controller;
 124                 #gpio-cells = <2>;
 125                 ngpios = <31>;
 126                 interrupt-controller;
 127                 #interrupt-cells = <2>;
 128         };
 129 };