2 * Device Tree Source for the EMEV2 SoC
4 * Copyright (C) 2012 Renesas Solutions Corp.
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 /include/ "skeleton.dtsi"
14 compatible = "renesas,emev2";
15 interrupt-parent = <&gic>;
31 compatible = "arm,cortex-a9";
36 compatible = "arm,cortex-a9";
41 gic: interrupt-controller@e0020000 {
42 compatible = "arm,cortex-a9-gic";
44 #interrupt-cells = <3>;
45 reg = <0xe0028000 0x1000>,
50 compatible = "renesas,em-sti";
51 reg = <0xe0180000 0x54>;
52 interrupts = <0 125 0>;
56 compatible = "renesas,em-uart";
57 reg = <0xe1020000 0x38>;
62 compatible = "renesas,em-uart";
63 reg = <0xe1030000 0x38>;
68 compatible = "renesas,em-uart";
69 reg = <0xe1040000 0x38>;
70 interrupts = <0 10 0>;
74 compatible = "renesas,em-uart";
75 reg = <0xe1050000 0x38>;
76 interrupts = <0 11 0>;
79 gpio0: gpio@e0050000 {
80 compatible = "renesas,em-gio";
81 reg = <0xe0050000 0x2c>, <0xe0050040 0x20>;
82 interrupts = <0 67 0>, <0 68 0>;
87 #interrupt-cells = <2>;
89 gpio1: gpio@e0050080 {
90 compatible = "renesas,em-gio";
91 reg = <0xe0050080 0x2c>, <0xe00500c0 0x20>;
92 interrupts = <0 69 0>, <0 70 0>;
97 #interrupt-cells = <2>;
99 gpio2: gpio@e0050100 {
100 compatible = "renesas,em-gio";
101 reg = <0xe0050100 0x2c>, <0xe0050140 0x20>;
102 interrupts = <0 71 0>, <0 72 0>;
106 interrupt-controller;
107 #interrupt-cells = <2>;
109 gpio3: gpio@e0050180 {
110 compatible = "renesas,em-gio";
111 reg = <0xe0050180 0x2c>, <0xe00501c0 0x20>;
112 interrupts = <0 73 0>, <0 74 0>;
116 interrupt-controller;
117 #interrupt-cells = <2>;
119 gpio4: gpio@e0050200 {
120 compatible = "renesas,em-gio";
121 reg = <0xe0050200 0x2c>, <0xe0050240 0x20>;
122 interrupts = <0 75 0>, <0 76 0>;
126 interrupt-controller;
127 #interrupt-cells = <2>;