2 * Samsung's Exynos3250 SoC device tree source
4 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
8 * based board files can include this file and provide values for board specfic
11 * Note: This file does not include device nodes for all the controllers in
12 * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
13 * nodes can be added to this file.
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
20 #include "skeleton.dtsi"
21 #include <dt-bindings/clock/exynos3250.h>
24 compatible = "samsung,exynos3250";
25 interrupt-parent = <&gic>;
28 pinctrl0 = &pinctrl_0;
29 pinctrl1 = &pinctrl_1;
52 compatible = "arm,cortex-a7";
54 clock-frequency = <1000000000>;
59 compatible = "arm,cortex-a7";
61 clock-frequency = <1000000000>;
66 compatible = "simple-bus";
76 compatible = "fixed-clock";
80 clock-frequency = <0>;
82 clock-output-names = "xusbxti";
86 compatible = "fixed-clock";
88 clock-frequency = <0>;
90 clock-output-names = "xxti";
94 compatible = "fixed-clock";
96 clock-frequency = <0>;
98 clock-output-names = "xtcxo";
103 compatible = "mmio-sram";
104 reg = <0x02020000 0x40000>;
105 #address-cells = <1>;
107 ranges = <0 0x02020000 0x40000>;
110 compatible = "samsung,exynos4210-sysram";
115 compatible = "samsung,exynos4210-sysram-ns";
116 reg = <0x3f000 0x1000>;
121 compatible = "samsung,exynos4210-chipid";
122 reg = <0x10000000 0x100>;
125 sys_reg: syscon@10010000 {
126 compatible = "samsung,exynos3-sysreg", "syscon";
127 reg = <0x10010000 0x400>;
130 pmu_system_controller: system-controller@10020000 {
131 compatible = "samsung,exynos3250-pmu", "syscon";
132 reg = <0x10020000 0x4000>;
135 pd_cam: cam-power-domain@10023C00 {
136 compatible = "samsung,exynos4210-pd";
137 reg = <0x10023C00 0x20>;
140 pd_mfc: mfc-power-domain@10023C40 {
141 compatible = "samsung,exynos4210-pd";
142 reg = <0x10023C40 0x20>;
145 pd_g3d: g3d-power-domain@10023C60 {
146 compatible = "samsung,exynos4210-pd";
147 reg = <0x10023C60 0x20>;
150 pd_lcd0: lcd0-power-domain@10023C80 {
151 compatible = "samsung,exynos4210-pd";
152 reg = <0x10023C80 0x20>;
155 pd_isp: isp-power-domain@10023CA0 {
156 compatible = "samsung,exynos4210-pd";
157 reg = <0x10023CA0 0x20>;
160 cmu: clock-controller@10030000 {
161 compatible = "samsung,exynos3250-cmu";
162 reg = <0x10030000 0x20000>;
167 compatible = "samsung,s3c6410-rtc";
168 reg = <0x10070000 0x100>;
169 interrupts = <0 73 0>, <0 74 0>;
174 compatible = "samsung,exynos3250-tmu";
175 reg = <0x100C0000 0x100>;
176 interrupts = <0 216 0>;
177 clocks = <&cmu CLK_TMU_APBIF>;
178 clock-names = "tmu_apbif";
182 gic: interrupt-controller@10481000 {
183 compatible = "arm,cortex-a15-gic";
184 #interrupt-cells = <3>;
185 interrupt-controller;
186 reg = <0x10481000 0x1000>,
190 interrupts = <1 9 0xf04>;
194 compatible = "samsung,exynos4210-mct";
195 reg = <0x10050000 0x800>;
196 interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>,
197 <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>;
198 clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
199 clock-names = "fin_pll", "mct";
202 pinctrl_1: pinctrl@11000000 {
203 compatible = "samsung,exynos3250-pinctrl";
204 reg = <0x11000000 0x1000>;
205 interrupts = <0 225 0>;
207 wakeup-interrupt-controller {
208 compatible = "samsung,exynos4210-wakeup-eint";
209 interrupts = <0 48 0>;
213 pinctrl_0: pinctrl@11400000 {
214 compatible = "samsung,exynos3250-pinctrl";
215 reg = <0x11400000 0x1000>;
216 interrupts = <0 240 0>;
219 mshc_0: mshc@12510000 {
220 compatible = "samsung,exynos5250-dw-mshc";
221 reg = <0x12510000 0x1000>;
222 interrupts = <0 142 0>;
223 clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
224 clock-names = "biu", "ciu";
226 #address-cells = <1>;
231 mshc_1: mshc@12520000 {
232 compatible = "samsung,exynos5250-dw-mshc";
233 reg = <0x12520000 0x1000>;
234 interrupts = <0 143 0>;
235 clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
236 clock-names = "biu", "ciu";
238 #address-cells = <1>;
244 compatible = "arm,amba-bus";
245 #address-cells = <1>;
249 pdma0: pdma@12680000 {
250 compatible = "arm,pl330", "arm,primecell";
251 reg = <0x12680000 0x1000>;
252 interrupts = <0 138 0>;
253 clocks = <&cmu CLK_PDMA0>;
254 clock-names = "apb_pclk";
257 #dma-requests = <32>;
260 pdma1: pdma@12690000 {
261 compatible = "arm,pl330", "arm,primecell";
262 reg = <0x12690000 0x1000>;
263 interrupts = <0 139 0>;
264 clocks = <&cmu CLK_PDMA1>;
265 clock-names = "apb_pclk";
268 #dma-requests = <32>;
273 compatible = "samsung,exynos3250-adc",
274 "samsung,exynos-adc-v2";
275 reg = <0x126C0000 0x100>;
276 interrupts = <0 137 0>;
277 clock-names = "adc", "sclk";
278 clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
279 #io-channel-cells = <1>;
281 samsung,syscon-phandle = <&pmu_system_controller>;
285 serial_0: serial@13800000 {
286 compatible = "samsung,exynos4210-uart";
287 reg = <0x13800000 0x100>;
288 interrupts = <0 109 0>;
289 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
290 clock-names = "uart", "clk_uart_baud0";
291 pinctrl-names = "default";
292 pinctrl-0 = <&uart0_data &uart0_fctl>;
296 serial_1: serial@13810000 {
297 compatible = "samsung,exynos4210-uart";
298 reg = <0x13810000 0x100>;
299 interrupts = <0 110 0>;
300 clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
301 clock-names = "uart", "clk_uart_baud0";
302 pinctrl-names = "default";
303 pinctrl-0 = <&uart1_data>;
307 i2c_0: i2c@13860000 {
308 #address-cells = <1>;
310 compatible = "samsung,s3c2440-i2c";
311 reg = <0x13860000 0x100>;
312 interrupts = <0 113 0>;
313 clocks = <&cmu CLK_I2C0>;
315 pinctrl-names = "default";
316 pinctrl-0 = <&i2c0_bus>;
320 i2c_1: i2c@13870000 {
321 #address-cells = <1>;
323 compatible = "samsung,s3c2440-i2c";
324 reg = <0x13870000 0x100>;
325 interrupts = <0 114 0>;
326 clocks = <&cmu CLK_I2C1>;
328 pinctrl-names = "default";
329 pinctrl-0 = <&i2c1_bus>;
333 i2c_2: i2c@13880000 {
334 #address-cells = <1>;
336 compatible = "samsung,s3c2440-i2c";
337 reg = <0x13880000 0x100>;
338 interrupts = <0 115 0>;
339 clocks = <&cmu CLK_I2C2>;
341 pinctrl-names = "default";
342 pinctrl-0 = <&i2c2_bus>;
346 i2c_3: i2c@13890000 {
347 #address-cells = <1>;
349 compatible = "samsung,s3c2440-i2c";
350 reg = <0x13890000 0x100>;
351 interrupts = <0 116 0>;
352 clocks = <&cmu CLK_I2C3>;
354 pinctrl-names = "default";
355 pinctrl-0 = <&i2c3_bus>;
359 i2c_4: i2c@138A0000 {
360 #address-cells = <1>;
362 compatible = "samsung,s3c2440-i2c";
363 reg = <0x138A0000 0x100>;
364 interrupts = <0 117 0>;
365 clocks = <&cmu CLK_I2C4>;
367 pinctrl-names = "default";
368 pinctrl-0 = <&i2c4_bus>;
372 i2c_5: i2c@138B0000 {
373 #address-cells = <1>;
375 compatible = "samsung,s3c2440-i2c";
376 reg = <0x138B0000 0x100>;
377 interrupts = <0 118 0>;
378 clocks = <&cmu CLK_I2C5>;
380 pinctrl-names = "default";
381 pinctrl-0 = <&i2c5_bus>;
385 i2c_6: i2c@138C0000 {
386 #address-cells = <1>;
388 compatible = "samsung,s3c2440-i2c";
389 reg = <0x138C0000 0x100>;
390 interrupts = <0 119 0>;
391 clocks = <&cmu CLK_I2C6>;
393 pinctrl-names = "default";
394 pinctrl-0 = <&i2c6_bus>;
398 i2c_7: i2c@138D0000 {
399 #address-cells = <1>;
401 compatible = "samsung,s3c2440-i2c";
402 reg = <0x138D0000 0x100>;
403 interrupts = <0 120 0>;
404 clocks = <&cmu CLK_I2C7>;
406 pinctrl-names = "default";
407 pinctrl-0 = <&i2c7_bus>;
411 spi_0: spi@13920000 {
412 compatible = "samsung,exynos4210-spi";
413 reg = <0x13920000 0x100>;
414 interrupts = <0 121 0>;
415 dmas = <&pdma0 7>, <&pdma0 6>;
416 dma-names = "tx", "rx";
417 #address-cells = <1>;
419 clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
420 clock-names = "spi", "spi_busclk0";
421 samsung,spi-src-clk = <0>;
422 pinctrl-names = "default";
423 pinctrl-0 = <&spi0_bus>;
427 spi_1: spi@13930000 {
428 compatible = "samsung,exynos4210-spi";
429 reg = <0x13930000 0x100>;
430 interrupts = <0 122 0>;
431 dmas = <&pdma1 7>, <&pdma1 6>;
432 dma-names = "tx", "rx";
433 #address-cells = <1>;
435 clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
436 clock-names = "spi", "spi_busclk0";
437 samsung,spi-src-clk = <0>;
438 pinctrl-names = "default";
439 pinctrl-0 = <&spi1_bus>;
444 compatible = "samsung,s3c6410-i2s";
445 reg = <0x13970000 0x100>;
446 interrupts = <0 126 0>;
447 clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>;
448 clock-names = "iis", "i2s_opclk0";
449 dmas = <&pdma0 14>, <&pdma0 13>;
450 dma-names = "tx", "rx";
451 pinctrl-0 = <&i2s2_bus>;
452 pinctrl-names = "default";
457 compatible = "samsung,exynos4210-pwm";
458 reg = <0x139D0000 0x1000>;
459 interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
460 <0 107 0>, <0 108 0>;
466 compatible = "arm,cortex-a7-pmu";
467 interrupts = <0 18 0>, <0 19 0>;
472 #include "exynos3250-pinctrl.dtsi"