2 * Samsung's Exynos3250 SoC device tree source
4 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
8 * based board files can include this file and provide values for board specfic
11 * Note: This file does not include device nodes for all the controllers in
12 * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
13 * nodes can be added to this file.
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
20 #include "skeleton.dtsi"
21 #include <dt-bindings/clock/exynos3250.h>
24 compatible = "samsung,exynos3250";
25 interrupt-parent = <&gic>;
28 pinctrl0 = &pinctrl_0;
29 pinctrl1 = &pinctrl_1;
52 compatible = "arm,cortex-a7";
54 clock-frequency = <1000000000>;
59 compatible = "arm,cortex-a7";
61 clock-frequency = <1000000000>;
66 compatible = "simple-bus";
76 compatible = "fixed-clock";
80 clock-frequency = <0>;
82 clock-output-names = "xusbxti";
86 compatible = "fixed-clock";
88 clock-frequency = <0>;
90 clock-output-names = "xxti";
94 compatible = "fixed-clock";
96 clock-frequency = <0>;
98 clock-output-names = "xtcxo";
103 compatible = "mmio-sram";
104 reg = <0x02020000 0x40000>;
105 #address-cells = <1>;
107 ranges = <0 0x02020000 0x40000>;
110 compatible = "samsung,exynos4210-sysram";
115 compatible = "samsung,exynos4210-sysram-ns";
116 reg = <0x3f000 0x1000>;
121 compatible = "samsung,exynos4210-chipid";
122 reg = <0x10000000 0x100>;
125 sys_reg: syscon@10010000 {
126 compatible = "samsung,exynos3-sysreg", "syscon";
127 reg = <0x10010000 0x400>;
130 pmu_system_controller: system-controller@10020000 {
131 compatible = "samsung,exynos3250-pmu", "syscon";
132 reg = <0x10020000 0x4000>;
135 mipi_phy: video-phy@10020710 {
136 compatible = "samsung,s5pv210-mipi-video-phy";
137 reg = <0x10020710 8>;
141 pd_cam: cam-power-domain@10023C00 {
142 compatible = "samsung,exynos4210-pd";
143 reg = <0x10023C00 0x20>;
146 pd_mfc: mfc-power-domain@10023C40 {
147 compatible = "samsung,exynos4210-pd";
148 reg = <0x10023C40 0x20>;
151 pd_g3d: g3d-power-domain@10023C60 {
152 compatible = "samsung,exynos4210-pd";
153 reg = <0x10023C60 0x20>;
156 pd_lcd0: lcd0-power-domain@10023C80 {
157 compatible = "samsung,exynos4210-pd";
158 reg = <0x10023C80 0x20>;
161 pd_isp: isp-power-domain@10023CA0 {
162 compatible = "samsung,exynos4210-pd";
163 reg = <0x10023CA0 0x20>;
166 cmu: clock-controller@10030000 {
167 compatible = "samsung,exynos3250-cmu";
168 reg = <0x10030000 0x20000>;
172 cmu_dmc: clock-controller@105C0000 {
173 compatible = "samsung,exynos3250-cmu-dmc";
174 reg = <0x105C0000 0x2000>;
179 compatible = "samsung,exynos3250-rtc";
180 reg = <0x10070000 0x100>;
181 interrupts = <0 73 0>, <0 74 0>;
186 compatible = "samsung,exynos3250-tmu";
187 reg = <0x100C0000 0x100>;
188 interrupts = <0 216 0>;
189 clocks = <&cmu CLK_TMU_APBIF>;
190 clock-names = "tmu_apbif";
194 gic: interrupt-controller@10481000 {
195 compatible = "arm,cortex-a15-gic";
196 #interrupt-cells = <3>;
197 interrupt-controller;
198 reg = <0x10481000 0x1000>,
202 interrupts = <1 9 0xf04>;
206 compatible = "samsung,exynos4210-mct";
207 reg = <0x10050000 0x800>;
208 interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>,
209 <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>;
210 clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
211 clock-names = "fin_pll", "mct";
214 pinctrl_1: pinctrl@11000000 {
215 compatible = "samsung,exynos3250-pinctrl";
216 reg = <0x11000000 0x1000>;
217 interrupts = <0 225 0>;
219 wakeup-interrupt-controller {
220 compatible = "samsung,exynos4210-wakeup-eint";
221 interrupts = <0 48 0>;
225 pinctrl_0: pinctrl@11400000 {
226 compatible = "samsung,exynos3250-pinctrl";
227 reg = <0x11400000 0x1000>;
228 interrupts = <0 240 0>;
231 fimd: fimd@11c00000 {
232 compatible = "samsung,exynos3250-fimd";
233 reg = <0x11c00000 0x30000>;
234 interrupt-names = "fifo", "vsync", "lcd_sys";
235 interrupts = <0 84 0>, <0 85 0>, <0 86 0>;
236 clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
237 clock-names = "sclk_fimd", "fimd";
238 samsung,power-domain = <&pd_lcd0>;
239 samsung,sysreg = <&sys_reg>;
243 dsi_0: dsi@11C80000 {
244 compatible = "samsung,exynos3250-mipi-dsi";
245 reg = <0x11C80000 0x10000>;
246 interrupts = <0 83 0>;
247 samsung,phy-type = <0>;
248 samsung,power-domain = <&pd_lcd0>;
249 phys = <&mipi_phy 1>;
251 clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
252 clock-names = "bus_clk", "pll_clk";
253 #address-cells = <1>;
258 mshc_0: mshc@12510000 {
259 compatible = "samsung,exynos5250-dw-mshc";
260 reg = <0x12510000 0x1000>;
261 interrupts = <0 142 0>;
262 clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
263 clock-names = "biu", "ciu";
265 #address-cells = <1>;
270 mshc_1: mshc@12520000 {
271 compatible = "samsung,exynos5250-dw-mshc";
272 reg = <0x12520000 0x1000>;
273 interrupts = <0 143 0>;
274 clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
275 clock-names = "biu", "ciu";
277 #address-cells = <1>;
283 compatible = "arm,amba-bus";
284 #address-cells = <1>;
288 pdma0: pdma@12680000 {
289 compatible = "arm,pl330", "arm,primecell";
290 reg = <0x12680000 0x1000>;
291 interrupts = <0 138 0>;
292 clocks = <&cmu CLK_PDMA0>;
293 clock-names = "apb_pclk";
296 #dma-requests = <32>;
299 pdma1: pdma@12690000 {
300 compatible = "arm,pl330", "arm,primecell";
301 reg = <0x12690000 0x1000>;
302 interrupts = <0 139 0>;
303 clocks = <&cmu CLK_PDMA1>;
304 clock-names = "apb_pclk";
307 #dma-requests = <32>;
312 compatible = "samsung,exynos3250-adc",
313 "samsung,exynos-adc-v2";
314 reg = <0x126C0000 0x100>, <0x10020718 0x4>;
315 interrupts = <0 137 0>;
316 clock-names = "adc", "sclk";
317 clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
318 #io-channel-cells = <1>;
323 mfc: codec@13400000 {
324 compatible = "samsung,mfc-v7";
325 reg = <0x13400000 0x10000>;
326 interrupts = <0 102 0>;
327 clock-names = "mfc", "sclk_mfc";
328 clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>;
329 samsung,power-domain = <&pd_mfc>;
333 serial_0: serial@13800000 {
334 compatible = "samsung,exynos4210-uart";
335 reg = <0x13800000 0x100>;
336 interrupts = <0 109 0>;
337 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
338 clock-names = "uart", "clk_uart_baud0";
339 pinctrl-names = "default";
340 pinctrl-0 = <&uart0_data &uart0_fctl>;
344 serial_1: serial@13810000 {
345 compatible = "samsung,exynos4210-uart";
346 reg = <0x13810000 0x100>;
347 interrupts = <0 110 0>;
348 clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
349 clock-names = "uart", "clk_uart_baud0";
350 pinctrl-names = "default";
351 pinctrl-0 = <&uart1_data>;
355 i2c_0: i2c@13860000 {
356 #address-cells = <1>;
358 compatible = "samsung,s3c2440-i2c";
359 reg = <0x13860000 0x100>;
360 interrupts = <0 113 0>;
361 clocks = <&cmu CLK_I2C0>;
363 pinctrl-names = "default";
364 pinctrl-0 = <&i2c0_bus>;
368 i2c_1: i2c@13870000 {
369 #address-cells = <1>;
371 compatible = "samsung,s3c2440-i2c";
372 reg = <0x13870000 0x100>;
373 interrupts = <0 114 0>;
374 clocks = <&cmu CLK_I2C1>;
376 pinctrl-names = "default";
377 pinctrl-0 = <&i2c1_bus>;
381 i2c_2: i2c@13880000 {
382 #address-cells = <1>;
384 compatible = "samsung,s3c2440-i2c";
385 reg = <0x13880000 0x100>;
386 interrupts = <0 115 0>;
387 clocks = <&cmu CLK_I2C2>;
389 pinctrl-names = "default";
390 pinctrl-0 = <&i2c2_bus>;
394 i2c_3: i2c@13890000 {
395 #address-cells = <1>;
397 compatible = "samsung,s3c2440-i2c";
398 reg = <0x13890000 0x100>;
399 interrupts = <0 116 0>;
400 clocks = <&cmu CLK_I2C3>;
402 pinctrl-names = "default";
403 pinctrl-0 = <&i2c3_bus>;
407 i2c_4: i2c@138A0000 {
408 #address-cells = <1>;
410 compatible = "samsung,s3c2440-i2c";
411 reg = <0x138A0000 0x100>;
412 interrupts = <0 117 0>;
413 clocks = <&cmu CLK_I2C4>;
415 pinctrl-names = "default";
416 pinctrl-0 = <&i2c4_bus>;
420 i2c_5: i2c@138B0000 {
421 #address-cells = <1>;
423 compatible = "samsung,s3c2440-i2c";
424 reg = <0x138B0000 0x100>;
425 interrupts = <0 118 0>;
426 clocks = <&cmu CLK_I2C5>;
428 pinctrl-names = "default";
429 pinctrl-0 = <&i2c5_bus>;
433 i2c_6: i2c@138C0000 {
434 #address-cells = <1>;
436 compatible = "samsung,s3c2440-i2c";
437 reg = <0x138C0000 0x100>;
438 interrupts = <0 119 0>;
439 clocks = <&cmu CLK_I2C6>;
441 pinctrl-names = "default";
442 pinctrl-0 = <&i2c6_bus>;
446 i2c_7: i2c@138D0000 {
447 #address-cells = <1>;
449 compatible = "samsung,s3c2440-i2c";
450 reg = <0x138D0000 0x100>;
451 interrupts = <0 120 0>;
452 clocks = <&cmu CLK_I2C7>;
454 pinctrl-names = "default";
455 pinctrl-0 = <&i2c7_bus>;
459 spi_0: spi@13920000 {
460 compatible = "samsung,exynos4210-spi";
461 reg = <0x13920000 0x100>;
462 interrupts = <0 121 0>;
463 dmas = <&pdma0 7>, <&pdma0 6>;
464 dma-names = "tx", "rx";
465 #address-cells = <1>;
467 clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
468 clock-names = "spi", "spi_busclk0";
469 samsung,spi-src-clk = <0>;
470 pinctrl-names = "default";
471 pinctrl-0 = <&spi0_bus>;
475 spi_1: spi@13930000 {
476 compatible = "samsung,exynos4210-spi";
477 reg = <0x13930000 0x100>;
478 interrupts = <0 122 0>;
479 dmas = <&pdma1 7>, <&pdma1 6>;
480 dma-names = "tx", "rx";
481 #address-cells = <1>;
483 clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
484 clock-names = "spi", "spi_busclk0";
485 samsung,spi-src-clk = <0>;
486 pinctrl-names = "default";
487 pinctrl-0 = <&spi1_bus>;
492 compatible = "samsung,s3c6410-i2s";
493 reg = <0x13970000 0x100>;
494 interrupts = <0 126 0>;
495 clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>;
496 clock-names = "iis", "i2s_opclk0";
497 dmas = <&pdma0 14>, <&pdma0 13>;
498 dma-names = "tx", "rx";
499 pinctrl-0 = <&i2s2_bus>;
500 pinctrl-names = "default";
505 compatible = "samsung,exynos4210-pwm";
506 reg = <0x139D0000 0x1000>;
507 interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
508 <0 107 0>, <0 108 0>;
514 compatible = "arm,cortex-a7-pmu";
515 interrupts = <0 18 0>, <0 19 0>;
520 #include "exynos3250-pinctrl.dtsi"