2 * Samsung's Exynos4210 SoC device tree source
4 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 * Copyright (c) 2010-2011 Linaro Ltd.
9 * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
10 * based board files can include this file and provide values for board specfic
13 * Note: This file does not include device nodes for all the controllers in
14 * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional
15 * nodes can be added to this file.
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
22 #include "exynos4.dtsi"
23 #include "exynos4210-pinctrl.dtsi"
26 compatible = "samsung,exynos4210", "samsung,exynos4";
29 pinctrl0 = &pinctrl_0;
30 pinctrl1 = &pinctrl_1;
31 pinctrl2 = &pinctrl_2;
35 compatible = "mmio-sram";
36 reg = <0x02020000 0x20000>;
39 ranges = <0 0x02020000 0x20000>;
42 compatible = "samsung,exynos4210-sysram";
47 compatible = "samsung,exynos4210-sysram-ns";
48 reg = <0x1f000 0x1000>;
52 pd_lcd1: lcd1-power-domain@10023CA0 {
53 compatible = "samsung,exynos4210-pd";
54 reg = <0x10023CA0 0x20>;
57 gic: interrupt-controller@10490000 {
58 cpu-offset = <0x8000>;
61 combiner: interrupt-controller@10440000 {
62 samsung,combiner-nr = <16>;
63 interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
64 <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
65 <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
66 <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
70 compatible = "samsung,exynos4210-mct";
71 reg = <0x10050000 0x800>;
72 interrupt-parent = <&mct_map>;
73 interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
74 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
75 clock-names = "fin_pll", "mct";
78 #interrupt-cells = <1>;
81 interrupt-map = <0 &gic 0 57 0>,
90 clock: clock-controller@10030000 {
91 compatible = "samsung,exynos4210-clock";
92 reg = <0x10030000 0x20000>;
97 compatible = "arm,cortex-a9-pmu";
98 interrupt-parent = <&combiner>;
99 interrupts = <2 2>, <3 2>;
102 pinctrl_0: pinctrl@11400000 {
103 compatible = "samsung,exynos4210-pinctrl";
104 reg = <0x11400000 0x1000>;
105 interrupts = <0 47 0>;
108 pinctrl_1: pinctrl@11000000 {
109 compatible = "samsung,exynos4210-pinctrl";
110 reg = <0x11000000 0x1000>;
111 interrupts = <0 46 0>;
113 wakup_eint: wakeup-interrupt-controller {
114 compatible = "samsung,exynos4210-wakeup-eint";
115 interrupt-parent = <&gic>;
116 interrupts = <0 32 0>;
120 pinctrl_2: pinctrl@03860000 {
121 compatible = "samsung,exynos4210-pinctrl";
122 reg = <0x03860000 0x1000>;
126 compatible = "samsung,exynos4210-tmu";
127 interrupt-parent = <&combiner>;
128 reg = <0x100C0000 0x100>;
130 clocks = <&clock CLK_TMU_APBIF>;
131 clock-names = "tmu_apbif";
136 compatible = "samsung,s5pv210-g2d";
137 reg = <0x12800000 0x1000>;
138 interrupts = <0 89 0>;
139 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
140 clock-names = "sclk_fimg2d", "fimg2d";
145 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
146 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
147 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
149 fimc_0: fimc@11800000 {
150 samsung,pix-limits = <4224 8192 1920 4224>;
151 samsung,mainscaler-ext;
155 fimc_1: fimc@11810000 {
156 samsung,pix-limits = <4224 8192 1920 4224>;
157 samsung,mainscaler-ext;
161 fimc_2: fimc@11820000 {
162 samsung,pix-limits = <4224 8192 1920 4224>;
163 samsung,mainscaler-ext;
167 fimc_3: fimc@11830000 {
168 samsung,pix-limits = <1920 8192 1366 1920>;
169 samsung,rotators = <0>;
170 samsung,mainscaler-ext;