2 * Samsung's Exynos4210 SoC device tree source
4 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 * Copyright (c) 2010-2011 Linaro Ltd.
9 * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
10 * based board files can include this file and provide values for board specfic
13 * Note: This file does not include device nodes for all the controllers in
14 * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional
15 * nodes can be added to this file.
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
22 #include "exynos4.dtsi"
23 #include "exynos4210-pinctrl.dtsi"
24 #include "exynos4-cpu-thermal.dtsi"
27 compatible = "samsung,exynos4210", "samsung,exynos4";
30 pinctrl0 = &pinctrl_0;
31 pinctrl1 = &pinctrl_1;
32 pinctrl2 = &pinctrl_2;
41 compatible = "arm,cortex-a9";
43 cooling-min-level = <4>;
44 cooling-max-level = <2>;
45 #cooling-cells = <2>; /* min followed by max */
50 compatible = "arm,cortex-a9";
55 pmu_system_controller: system-controller@10020000 {
56 clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
57 "clkout4", "clkout8", "clkout9";
58 clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
59 <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
60 <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>,
66 compatible = "mmio-sram";
67 reg = <0x02020000 0x20000>;
70 ranges = <0 0x02020000 0x20000>;
73 compatible = "samsung,exynos4210-sysram";
78 compatible = "samsung,exynos4210-sysram-ns";
79 reg = <0x1f000 0x1000>;
83 pd_lcd1: lcd1-power-domain@10023CA0 {
84 compatible = "samsung,exynos4210-pd";
85 reg = <0x10023CA0 0x20>;
86 #power-domain-cells = <0>;
89 l2c: l2-cache-controller@10502000 {
90 compatible = "arm,pl310-cache";
91 reg = <0x10502000 0x1000>;
94 arm,tag-latency = <2 2 1>;
95 arm,data-latency = <2 2 1>;
98 gic: interrupt-controller@10490000 {
99 cpu-offset = <0x8000>;
102 combiner: interrupt-controller@10440000 {
103 samsung,combiner-nr = <16>;
104 interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
105 <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
106 <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
107 <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
111 compatible = "samsung,exynos4210-mct";
112 reg = <0x10050000 0x800>;
113 interrupt-parent = <&mct_map>;
114 interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
115 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
116 clock-names = "fin_pll", "mct";
119 #interrupt-cells = <1>;
120 #address-cells = <0>;
122 interrupt-map = <0 &gic 0 57 0>,
131 clock: clock-controller@10030000 {
132 compatible = "samsung,exynos4210-clock";
133 reg = <0x10030000 0x20000>;
137 pinctrl_0: pinctrl@11400000 {
138 compatible = "samsung,exynos4210-pinctrl";
139 reg = <0x11400000 0x1000>;
140 interrupts = <0 47 0>;
143 pinctrl_1: pinctrl@11000000 {
144 compatible = "samsung,exynos4210-pinctrl";
145 reg = <0x11000000 0x1000>;
146 interrupts = <0 46 0>;
148 wakup_eint: wakeup-interrupt-controller {
149 compatible = "samsung,exynos4210-wakeup-eint";
150 interrupt-parent = <&gic>;
151 interrupts = <0 32 0>;
155 pinctrl_2: pinctrl@03860000 {
156 compatible = "samsung,exynos4210-pinctrl";
157 reg = <0x03860000 0x1000>;
161 compatible = "samsung,exynos4210-tmu";
162 interrupt-parent = <&combiner>;
163 reg = <0x100C0000 0x100>;
165 clocks = <&clock CLK_TMU_APBIF>;
166 clock-names = "tmu_apbif";
167 samsung,tmu_gain = <15>;
168 samsung,tmu_reference_voltage = <7>;
173 cpu_thermal: cpu-thermal {
174 polling-delay-passive = <0>;
176 thermal-sensors = <&tmu 0>;
179 cpu_alert0: cpu-alert-0 {
180 temperature = <85000>; /* millicelsius */
182 cpu_alert1: cpu-alert-1 {
183 temperature = <100000>; /* millicelsius */
185 cpu_alert2: cpu-alert-2 {
186 temperature = <110000>; /* millicelsius */
193 compatible = "samsung,s5pv210-g2d";
194 reg = <0x12800000 0x1000>;
195 interrupts = <0 89 0>;
196 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
197 clock-names = "sclk_fimg2d", "fimg2d";
202 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
203 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
204 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
206 fimc_0: fimc@11800000 {
207 samsung,pix-limits = <4224 8192 1920 4224>;
208 samsung,mainscaler-ext;
212 fimc_1: fimc@11810000 {
213 samsung,pix-limits = <4224 8192 1920 4224>;
214 samsung,mainscaler-ext;
218 fimc_2: fimc@11820000 {
219 samsung,pix-limits = <4224 8192 1920 4224>;
220 samsung,mainscaler-ext;
224 fimc_3: fimc@11830000 {
225 samsung,pix-limits = <1920 8192 1366 1920>;
226 samsung,rotators = <0>;
227 samsung,mainscaler-ext;
232 mixer: mixer@12C10000 {
233 clock-names = "mixer", "hdmi", "sclk_hdmi", "vp", "mout_mixer",
235 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
236 <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>,
237 <&clock CLK_MOUT_MIXER>, <&clock CLK_SCLK_MIXER>;
240 ppmu_lcd1: ppmu_lcd1@12240000 {
241 compatible = "samsung,exynos-ppmu";
242 reg = <0x12240000 0x2000>;
243 clocks = <&clock CLK_PPMULCD1>;
244 clock-names = "ppmu";