2 * Samsung's Exynos4x12 SoCs device tree source
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * Samsung's Exynos4x12 SoCs device nodes are listed in this file. Exynos4x12
8 * based board files can include this file and provide values for board specfic
11 * Note: This file does not include device nodes for all the controllers in
12 * Exynos4x12 SoC. As device tree coverage for Exynos4x12 increases, additional
13 * nodes can be added to this file.
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
20 #include "exynos4.dtsi"
21 #include "exynos4x12-pinctrl.dtsi"
25 pinctrl0 = &pinctrl_0;
26 pinctrl1 = &pinctrl_1;
27 pinctrl2 = &pinctrl_2;
28 pinctrl3 = &pinctrl_3;
29 fimc-lite0 = &fimc_lite_0;
30 fimc-lite1 = &fimc_lite_1;
35 compatible = "mmio-sram";
36 reg = <0x02020000 0x40000>;
39 ranges = <0 0x02020000 0x40000>;
42 compatible = "samsung,exynos4210-sysram";
47 compatible = "samsung,exynos4210-sysram-ns";
48 reg = <0x2f000 0x1000>;
52 pd_isp: isp-power-domain@10023CA0 {
53 compatible = "samsung,exynos4210-pd";
54 reg = <0x10023CA0 0x20>;
57 clock: clock-controller@10030000 {
58 compatible = "samsung,exynos4412-clock";
59 reg = <0x10030000 0x20000>;
64 compatible = "samsung,exynos4412-mct";
65 reg = <0x10050000 0x800>;
66 interrupt-parent = <&mct_map>;
67 interrupts = <0>, <1>, <2>, <3>, <4>;
68 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
69 clock-names = "fin_pll", "mct";
72 #interrupt-cells = <1>;
75 interrupt-map = <0 &gic 0 57 0>,
83 combiner: interrupt-controller@10440000 {
84 interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
85 <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
86 <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
87 <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
88 <0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>;
91 pinctrl_0: pinctrl@11400000 {
92 compatible = "samsung,exynos4x12-pinctrl";
93 reg = <0x11400000 0x1000>;
94 interrupts = <0 47 0>;
97 pinctrl_1: pinctrl@11000000 {
98 compatible = "samsung,exynos4x12-pinctrl";
99 reg = <0x11000000 0x1000>;
100 interrupts = <0 46 0>;
102 wakup_eint: wakeup-interrupt-controller {
103 compatible = "samsung,exynos4210-wakeup-eint";
104 interrupt-parent = <&gic>;
105 interrupts = <0 32 0>;
110 compatible = "samsung,exynos-adc-v1";
111 reg = <0x126C0000 0x100>, <0x10020718 0x4>;
112 interrupt-parent = <&combiner>;
114 clocks = <&clock CLK_TSADC>;
116 #io-channel-cells = <1>;
121 pinctrl_2: pinctrl@03860000 {
122 compatible = "samsung,exynos4x12-pinctrl";
123 reg = <0x03860000 0x1000>;
124 interrupt-parent = <&combiner>;
128 pinctrl_3: pinctrl@106E0000 {
129 compatible = "samsung,exynos4x12-pinctrl";
130 reg = <0x106E0000 0x1000>;
131 interrupts = <0 72 0>;
134 pmu_system_controller: system-controller@10020000 {
135 compatible = "samsung,exynos4212-pmu", "syscon";
139 compatible = "samsung,exynos4212-g2d";
140 reg = <0x10800000 0x1000>;
141 interrupts = <0 89 0>;
142 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
143 clock-names = "sclk_fimg2d", "fimg2d";
148 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
149 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
150 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
152 fimc_0: fimc@11800000 {
153 compatible = "samsung,exynos4212-fimc";
154 samsung,pix-limits = <4224 8192 1920 4224>;
155 samsung,mainscaler-ext;
160 fimc_1: fimc@11810000 {
161 compatible = "samsung,exynos4212-fimc";
162 samsung,pix-limits = <4224 8192 1920 4224>;
163 samsung,mainscaler-ext;
168 fimc_2: fimc@11820000 {
169 compatible = "samsung,exynos4212-fimc";
170 samsung,pix-limits = <4224 8192 1920 4224>;
171 samsung,mainscaler-ext;
177 fimc_3: fimc@11830000 {
178 compatible = "samsung,exynos4212-fimc";
179 samsung,pix-limits = <1920 8192 1366 1920>;
180 samsung,rotators = <0>;
181 samsung,mainscaler-ext;
186 fimc_lite_0: fimc-lite@12390000 {
187 compatible = "samsung,exynos4212-fimc-lite";
188 reg = <0x12390000 0x1000>;
189 interrupts = <0 105 0>;
190 samsung,power-domain = <&pd_isp>;
191 clocks = <&clock CLK_FIMC_LITE0>;
192 clock-names = "flite";
196 fimc_lite_1: fimc-lite@123A0000 {
197 compatible = "samsung,exynos4212-fimc-lite";
198 reg = <0x123A0000 0x1000>;
199 interrupts = <0 106 0>;
200 samsung,power-domain = <&pd_isp>;
201 clocks = <&clock CLK_FIMC_LITE1>;
202 clock-names = "flite";
206 fimc_is: fimc-is@12000000 {
207 compatible = "samsung,exynos4212-fimc-is", "simple-bus";
208 reg = <0x12000000 0x260000>;
209 interrupts = <0 90 0>, <0 95 0>;
210 samsung,power-domain = <&pd_isp>;
211 clocks = <&clock CLK_FIMC_LITE0>,
212 <&clock CLK_FIMC_LITE1>, <&clock CLK_PPMUISPX>,
213 <&clock CLK_PPMUISPMX>,
214 <&clock CLK_MOUT_MPLL_USER_T>,
215 <&clock CLK_FIMC_ISP>, <&clock CLK_FIMC_DRC>,
216 <&clock CLK_FIMC_FD>, <&clock CLK_MCUISP>,
217 <&clock CLK_DIV_ISP0>,<&clock CLK_DIV_ISP1>,
218 <&clock CLK_DIV_MCUISP0>,
219 <&clock CLK_DIV_MCUISP1>,
220 <&clock CLK_SCLK_UART_ISP>,
221 <&clock CLK_ACLK200>, <&clock CLK_DIV_ACLK200>,
222 <&clock CLK_ACLK400_MCUISP>,
223 <&clock CLK_DIV_ACLK400_MCUISP>;
224 clock-names = "lite0", "lite1", "ppmuispx",
225 "ppmuispmx", "mpll", "isp",
226 "drc", "fd", "mcuisp",
227 "ispdiv0", "ispdiv1", "mcuispdiv0",
228 "mcuispdiv1", "uart", "aclk200",
229 "div_aclk200", "aclk400mcuisp",
231 #address-cells = <1>;
237 reg = <0x10020000 0x3000>;
240 i2c1_isp: i2c-isp@12140000 {
241 compatible = "samsung,exynos4212-i2c-isp";
242 reg = <0x12140000 0x100>;
243 clocks = <&clock CLK_I2C1_ISP>;
244 clock-names = "i2c_isp";
245 #address-cells = <1>;
251 mshc_0: mmc@12550000 {
252 compatible = "samsung,exynos4412-dw-mshc";
253 reg = <0x12550000 0x1000>;
254 interrupts = <0 77 0>;
255 #address-cells = <1>;
258 clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>;
259 clock-names = "biu", "ciu";
263 exynos-usbphy@125B0000 {
264 compatible = "samsung,exynos4x12-usb2-phy";
265 samsung,sysreg-phandle = <&sys_reg>;