arch/arm/boot/dts/exynos5250-arndale.dts

   1 /*
   2  * Samsung's Exynos5250 based Arndale board device tree source
   3  *
   4  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 /dts-v1/;
  13 /include/ "exynos5250.dtsi"
  14
  15 / {
  16         model = "Insignal Arndale evaluation board based on EXYNOS5250";
  17         compatible = "insignal,arndale", "samsung,exynos5250";
  18
  19         memory {
  20                 reg = <0x40000000 0x80000000>;
  21         };
  22
  23         chosen {
  24                 bootargs = "console=ttySAC2,115200";
  25         };
  26
  27         i2c@12C60000 {
  28                 status = "disabled";
  29         };
  30
  31         i2c@12C70000 {
  32                 status = "disabled";
  33         };
  34
  35         i2c@12C80000 {
  36                 status = "disabled";
  37         };
  38
  39         i2c@12C90000 {
  40                 status = "disabled";
  41         };
  42
  43         i2c@12CA0000 {
  44                 status = "disabled";
  45         };
  46
  47         i2c@12CB0000 {
  48                 status = "disabled";
  49         };
  50
  51         i2c@12CC0000 {
  52                 status = "disabled";
  53         };
  54
  55         i2c@12CD0000 {
  56                 status = "disabled";
  57         };
  58
  59         i2c@121D0000 {
  60                 status = "disabled";
  61         };
  62
  63         dwmmc_0: dwmmc0@12200000 {
  64                 num-slots = <1>;
  65                 supports-highspeed;
  66                 broken-cd;
  67                 fifo-depth = <0x80>;
  68                 card-detect-delay = <200>;
  69                 samsung,dw-mshc-ciu-div = <3>;
  70                 samsung,dw-mshc-sdr-timing = <2 3>;
  71                 samsung,dw-mshc-ddr-timing = <1 2>;
  72
  73                 slot@0 {
  74                         reg = <0>;
  75                         bus-width = <8>;
  76                         gpios = <&gpc0 0 2 0 3>, <&gpc0 1 2 0 3>,
  77                                 <&gpc0 3 2 3 3>, <&gpc0 4 2 3 3>,
  78                                 <&gpc0 5 2 3 3>, <&gpc0 6 2 3 3>,
  79                                 <&gpc1 0 2 3 3>, <&gpc1 1 2 3 3>,
  80                                 <&gpc1 2 2 3 3>, <&gpc1 3 2 3 3>;
  81                 };
  82         };
  83
  84         dwmmc_1: dwmmc1@12210000 {
  85                 status = "disabled";
  86         };
  87
  88         dwmmc_2: dwmmc2@12220000 {
  89                 num-slots = <1>;
  90                 supports-highspeed;
  91                 fifo-depth = <0x80>;
  92                 card-detect-delay = <200>;
  93                 samsung,dw-mshc-ciu-div = <3>;
  94                 samsung,dw-mshc-sdr-timing = <2 3>;
  95                 samsung,dw-mshc-ddr-timing = <1 2>;
  96
  97                 slot@0 {
  98                         reg = <0>;
  99                         bus-width = <4>;
 100                         samsung,cd-pinmux-gpio = <&gpc3 2 2 3 3>;
 101                         gpios = <&gpc3 0 2 0 3>, <&gpc3 1 2 0 3>,
 102                                 <&gpc3 3 2 3 3>, <&gpc3 4 2 3 3>,
 103                                 <&gpc3 5 2 3 3>, <&gpc3 6 2 3 3>;
 104                 };
 105         };
 106
 107         dwmmc_3: dwmmc3@12230000 {
 108                 status = "disabled";
 109         };
 110
 111         spi_0: spi@12d20000 {
 112                 status = "disabled";
 113         };
 114
 115         spi_1: spi@12d30000 {
 116                 status = "disabled";
 117         };
 118
 119         spi_2: spi@12d40000 {
 120                 status = "disabled";
 121         };
 122
 123         fixed-rate-clocks {
 124                 xxti {
 125                         compatible = "samsung,clock-xxti";
 126                         clock-frequency = <24000000>;
 127                 };
 128         };
 129 };