arch/arm/boot/dts/exynos5250.dtsi

   1 /*
   2  * SAMSUNG EXYNOS5250 SoC device tree source
   3  *
   4  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
   8  * EXYNOS5250 based board files can include this file and provide
   9  * values for board specfic bindings.
  10  *
  11  * Note: This file does not include device nodes for all the controllers in
  12  * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
  13  * additional nodes can be added to this file.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18 */
  19
  20 #include <dt-bindings/clock/exynos5250.h>
  21 #include "exynos5.dtsi"
  22 #include "exynos5250-pinctrl.dtsi"
  23 #include "exynos4-cpu-thermal.dtsi"
  24 #include <dt-bindings/clock/exynos-audss-clk.h>
  25
  26 / {
  27         compatible = "samsung,exynos5250", "samsung,exynos5";
  28
  29         aliases {
  30                 spi0 = &spi_0;
  31                 spi1 = &spi_1;
  32                 spi2 = &spi_2;
  33                 gsc0 = &gsc_0;
  34                 gsc1 = &gsc_1;
  35                 gsc2 = &gsc_2;
  36                 gsc3 = &gsc_3;
  37                 mshc0 = &mmc_0;
  38                 mshc1 = &mmc_1;
  39                 mshc2 = &mmc_2;
  40                 mshc3 = &mmc_3;
  41                 i2c0 = &i2c_0;
  42                 i2c1 = &i2c_1;
  43                 i2c2 = &i2c_2;
  44                 i2c3 = &i2c_3;
  45                 i2c4 = &i2c_4;
  46                 i2c5 = &i2c_5;
  47                 i2c6 = &i2c_6;
  48                 i2c7 = &i2c_7;
  49                 i2c8 = &i2c_8;
  50                 i2c9 = &i2c_9;
  51                 pinctrl0 = &pinctrl_0;
  52                 pinctrl1 = &pinctrl_1;
  53                 pinctrl2 = &pinctrl_2;
  54                 pinctrl3 = &pinctrl_3;
  55         };
  56
  57         cpus {
  58                 #address-cells = <1>;
  59                 #size-cells = <0>;
  60
  61                 cpu0: cpu@0 {
  62                         device_type = "cpu";
  63                         compatible = "arm,cortex-a15";
  64                         reg = <0>;
  65                         clock-frequency = <1700000000>;
  66                         cooling-min-level = <15>;
  67                         cooling-max-level = <9>;
  68                         #cooling-cells = <2>; /* min followed by max */
  69                 };
  70                 cpu@1 {
  71                         device_type = "cpu";
  72                         compatible = "arm,cortex-a15";
  73                         reg = <1>;
  74                         clock-frequency = <1700000000>;
  75                 };
  76         };
  77
  78         sysram@02020000 {
  79                 compatible = "mmio-sram";
  80                 reg = <0x02020000 0x30000>;
  81                 #address-cells = <1>;
  82                 #size-cells = <1>;
  83                 ranges = <0 0x02020000 0x30000>;
  84
  85                 smp-sysram@0 {
  86                         compatible = "samsung,exynos4210-sysram";
  87                         reg = <0x0 0x1000>;
  88                 };
  89
  90                 smp-sysram@2f000 {
  91                         compatible = "samsung,exynos4210-sysram-ns";
  92                         reg = <0x2f000 0x1000>;
  93                 };
  94         };
  95
  96         pd_gsc: gsc-power-domain@10044000 {
  97                 compatible = "samsung,exynos4210-pd";
  98                 reg = <0x10044000 0x20>;
  99                 #power-domain-cells = <0>;
 100         };
 101
 102         pd_mfc: mfc-power-domain@10044040 {
 103                 compatible = "samsung,exynos4210-pd";
 104                 reg = <0x10044040 0x20>;
 105                 #power-domain-cells = <0>;
 106         };
 107
 108         pd_disp1: disp1-power-domain@100440A0 {
 109                 compatible = "samsung,exynos4210-pd";
 110                 reg = <0x100440A0 0x20>;
 111                 #power-domain-cells = <0>;
 112         };
 113
 114         clock: clock-controller@10010000 {
 115                 compatible = "samsung,exynos5250-clock";
 116                 reg = <0x10010000 0x30000>;
 117                 #clock-cells = <1>;
 118         };
 119
 120         clock_audss: audss-clock-controller@3810000 {
 121                 compatible = "samsung,exynos5250-audss-clock";
 122                 reg = <0x03810000 0x0C>;
 123                 #clock-cells = <1>;
 124                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
 125                          <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>;
 126                 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
 127         };
 128
 129         timer {
 130                 compatible = "arm,armv7-timer";
 131                 interrupts = <1 13 0xf08>,
 132                              <1 14 0xf08>,
 133                              <1 11 0xf08>,
 134                              <1 10 0xf08>;
 135                 /* Unfortunately we need this since some versions of U-Boot
 136                  * on Exynos don't set the CNTFRQ register, so we need the
 137                  * value from DT.
 138                  */
 139                 clock-frequency = <24000000>;
 140         };
 141
 142         mct@101C0000 {
 143                 compatible = "samsung,exynos4210-mct";
 144                 reg = <0x101C0000 0x800>;
 145                 interrupt-controller;
 146                 #interrupt-cells = <2>;
 147                 interrupt-parent = <&mct_map>;
 148                 interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
 149                              <4 0>, <5 0>;
 150                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
 151                 clock-names = "fin_pll", "mct";
 152
 153                 mct_map: mct-map {
 154                         #interrupt-cells = <2>;
 155                         #address-cells = <0>;
 156                         #size-cells = <0>;
 157                         interrupt-map = <0x0 0 &combiner 23 3>,
 158                                         <0x1 0 &combiner 23 4>,
 159                                         <0x2 0 &combiner 25 2>,
 160                                         <0x3 0 &combiner 25 3>,
 161                                         <0x4 0 &gic 0 120 0>,
 162                                         <0x5 0 &gic 0 121 0>;
 163                 };
 164         };
 165
 166         pmu {
 167                 compatible = "arm,cortex-a15-pmu";
 168                 interrupt-parent = <&combiner>;
 169                 interrupts = <1 2>, <22 4>;
 170         };
 171
 172         pinctrl_0: pinctrl@11400000 {
 173                 compatible = "samsung,exynos5250-pinctrl";
 174                 reg = <0x11400000 0x1000>;
 175                 interrupts = <0 46 0>;
 176
 177                 wakup_eint: wakeup-interrupt-controller {
 178                         compatible = "samsung,exynos4210-wakeup-eint";
 179                         interrupt-parent = <&gic>;
 180                         interrupts = <0 32 0>;
 181                 };
 182         };
 183
 184         pinctrl_1: pinctrl@13400000 {
 185                 compatible = "samsung,exynos5250-pinctrl";
 186                 reg = <0x13400000 0x1000>;
 187                 interrupts = <0 45 0>;
 188         };
 189
 190         pinctrl_2: pinctrl@10d10000 {
 191                 compatible = "samsung,exynos5250-pinctrl";
 192                 reg = <0x10d10000 0x1000>;
 193                 interrupts = <0 50 0>;
 194         };
 195
 196         pinctrl_3: pinctrl@03860000 {
 197                 compatible = "samsung,exynos5250-pinctrl";
 198                 reg = <0x03860000 0x1000>;
 199                 interrupts = <0 47 0>;
 200         };
 201
 202         pmu_system_controller: system-controller@10040000 {
 203                 compatible = "samsung,exynos5250-pmu", "syscon";
 204                 reg = <0x10040000 0x5000>;
 205                 clock-names = "clkout16";
 206                 clocks = <&clock CLK_FIN_PLL>;
 207                 #clock-cells = <1>;
 208                 interrupt-controller;
 209                 #interrupt-cells = <3>;
 210                 interrupt-parent = <&gic>;
 211         };
 212
 213         sysreg_system_controller: syscon@10050000 {
 214                 compatible = "samsung,exynos5-sysreg", "syscon";
 215                 reg = <0x10050000 0x5000>;
 216         };
 217
 218         watchdog@101D0000 {
 219                 compatible = "samsung,exynos5250-wdt";
 220                 reg = <0x101D0000 0x100>;
 221                 interrupts = <0 42 0>;
 222                 clocks = <&clock CLK_WDT>;
 223                 clock-names = "watchdog";
 224                 samsung,syscon-phandle = <&pmu_system_controller>;
 225         };
 226
 227         g2d@10850000 {
 228                 compatible = "samsung,exynos5250-g2d";
 229                 reg = <0x10850000 0x1000>;
 230                 interrupts = <0 91 0>;
 231                 clocks = <&clock CLK_G2D>;
 232                 clock-names = "fimg2d";
 233         };
 234
 235         mfc: codec@11000000 {
 236                 compatible = "samsung,mfc-v6";
 237                 reg = <0x11000000 0x10000>;
 238                 interrupts = <0 96 0>;
 239                 power-domains = <&pd_mfc>;
 240                 clocks = <&clock CLK_MFC>;
 241                 clock-names = "mfc";
 242         };
 243
 244         tmu: tmu@10060000 {
 245                 compatible = "samsung,exynos5250-tmu";
 246                 reg = <0x10060000 0x100>;
 247                 interrupts = <0 65 0>;
 248                 clocks = <&clock CLK_TMU>;
 249                 clock-names = "tmu_apbif";
 250                 #include "exynos4412-tmu-sensor-conf.dtsi"
 251         };
 252
 253         thermal-zones {
 254                 cpu_thermal: cpu-thermal {
 255                         polling-delay-passive = <0>;
 256                         polling-delay = <0>;
 257                         thermal-sensors = <&tmu 0>;
 258
 259                         cooling-maps {
 260                                 map0 {
 261                                      /* Corresponds to 800MHz at freq_table */
 262                                      cooling-device = <&cpu0 9 9>;
 263                                 };
 264                                 map1 {
 265                                      /* Corresponds to 200MHz at freq_table */
 266                                      cooling-device = <&cpu0 15 15>;
 267                                };
 268                        };
 269                 };
 270         };
 271
 272         sata: sata@122F0000 {
 273                 compatible = "snps,dwc-ahci";
 274                 samsung,sata-freq = <66>;
 275                 reg = <0x122F0000 0x1ff>;
 276                 interrupts = <0 115 0>;
 277                 clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
 278                 clock-names = "sata", "sclk_sata";
 279                 phys = <&sata_phy>;
 280                 phy-names = "sata-phy";
 281                 status = "disabled";
 282         };
 283
 284         sata_phy: sata-phy@12170000 {
 285                 compatible = "samsung,exynos5250-sata-phy";
 286                 reg = <0x12170000 0x1ff>;
 287                 clocks = <&clock CLK_SATA_PHYCTRL>;
 288                 clock-names = "sata_phyctrl";
 289                 #phy-cells = <0>;
 290                 samsung,syscon-phandle = <&pmu_system_controller>;
 291                 status = "disabled";
 292         };
 293
 294         i2c_0: i2c@12C60000 {
 295                 compatible = "samsung,s3c2440-i2c";
 296                 reg = <0x12C60000 0x100>;
 297                 interrupts = <0 56 0>;
 298                 #address-cells = <1>;
 299                 #size-cells = <0>;
 300                 clocks = <&clock CLK_I2C0>;
 301                 clock-names = "i2c";
 302                 pinctrl-names = "default";
 303                 pinctrl-0 = <&i2c0_bus>;
 304                 samsung,sysreg-phandle = <&sysreg_system_controller>;
 305                 status = "disabled";
 306         };
 307
 308         i2c_1: i2c@12C70000 {
 309                 compatible = "samsung,s3c2440-i2c";
 310                 reg = <0x12C70000 0x100>;
 311                 interrupts = <0 57 0>;
 312                 #address-cells = <1>;
 313                 #size-cells = <0>;
 314                 clocks = <&clock CLK_I2C1>;
 315                 clock-names = "i2c";
 316                 pinctrl-names = "default";
 317                 pinctrl-0 = <&i2c1_bus>;
 318                 samsung,sysreg-phandle = <&sysreg_system_controller>;
 319                 status = "disabled";
 320         };
 321
 322         i2c_2: i2c@12C80000 {
 323                 compatible = "samsung,s3c2440-i2c";
 324                 reg = <0x12C80000 0x100>;
 325                 interrupts = <0 58 0>;
 326                 #address-cells = <1>;
 327                 #size-cells = <0>;
 328                 clocks = <&clock CLK_I2C2>;
 329                 clock-names = "i2c";
 330                 pinctrl-names = "default";
 331                 pinctrl-0 = <&i2c2_bus>;
 332                 samsung,sysreg-phandle = <&sysreg_system_controller>;
 333                 status = "disabled";
 334         };
 335
 336         i2c_3: i2c@12C90000 {
 337                 compatible = "samsung,s3c2440-i2c";
 338                 reg = <0x12C90000 0x100>;
 339                 interrupts = <0 59 0>;
 340                 #address-cells = <1>;
 341                 #size-cells = <0>;
 342                 clocks = <&clock CLK_I2C3>;
 343                 clock-names = "i2c";
 344                 pinctrl-names = "default";
 345                 pinctrl-0 = <&i2c3_bus>;
 346                 samsung,sysreg-phandle = <&sysreg_system_controller>;
 347                 status = "disabled";
 348         };
 349
 350         i2c_4: i2c@12CA0000 {
 351                 compatible = "samsung,s3c2440-i2c";
 352                 reg = <0x12CA0000 0x100>;
 353                 interrupts = <0 60 0>;
 354                 #address-cells = <1>;
 355                 #size-cells = <0>;
 356                 clocks = <&clock CLK_I2C4>;
 357                 clock-names = "i2c";
 358                 pinctrl-names = "default";
 359                 pinctrl-0 = <&i2c4_bus>;
 360                 status = "disabled";
 361         };
 362
 363         i2c_5: i2c@12CB0000 {
 364                 compatible = "samsung,s3c2440-i2c";
 365                 reg = <0x12CB0000 0x100>;
 366                 interrupts = <0 61 0>;
 367                 #address-cells = <1>;
 368                 #size-cells = <0>;
 369                 clocks = <&clock CLK_I2C5>;
 370                 clock-names = "i2c";
 371                 pinctrl-names = "default";
 372                 pinctrl-0 = <&i2c5_bus>;
 373                 status = "disabled";
 374         };
 375
 376         i2c_6: i2c@12CC0000 {
 377                 compatible = "samsung,s3c2440-i2c";
 378                 reg = <0x12CC0000 0x100>;
 379                 interrupts = <0 62 0>;
 380                 #address-cells = <1>;
 381                 #size-cells = <0>;
 382                 clocks = <&clock CLK_I2C6>;
 383                 clock-names = "i2c";
 384                 pinctrl-names = "default";
 385                 pinctrl-0 = <&i2c6_bus>;
 386                 status = "disabled";
 387         };
 388
 389         i2c_7: i2c@12CD0000 {
 390                 compatible = "samsung,s3c2440-i2c";
 391                 reg = <0x12CD0000 0x100>;
 392                 interrupts = <0 63 0>;
 393                 #address-cells = <1>;
 394                 #size-cells = <0>;
 395                 clocks = <&clock CLK_I2C7>;
 396                 clock-names = "i2c";
 397                 pinctrl-names = "default";
 398                 pinctrl-0 = <&i2c7_bus>;
 399                 status = "disabled";
 400         };
 401
 402         i2c_8: i2c@12CE0000 {
 403                 compatible = "samsung,s3c2440-hdmiphy-i2c";
 404                 reg = <0x12CE0000 0x1000>;
 405                 interrupts = <0 64 0>;
 406                 #address-cells = <1>;
 407                 #size-cells = <0>;
 408                 clocks = <&clock CLK_I2C_HDMI>;
 409                 clock-names = "i2c";
 410                 status = "disabled";
 411         };
 412
 413         i2c_9: i2c@121D0000 {
 414                 compatible = "samsung,exynos5-sata-phy-i2c";
 415                 reg = <0x121D0000 0x100>;
 416                 #address-cells = <1>;
 417                 #size-cells = <0>;
 418                 clocks = <&clock CLK_SATA_PHYI2C>;
 419                 clock-names = "i2c";
 420                 status = "disabled";
 421         };
 422
 423         spi_0: spi@12d20000 {
 424                 compatible = "samsung,exynos4210-spi";
 425                 status = "disabled";
 426                 reg = <0x12d20000 0x100>;
 427                 interrupts = <0 66 0>;
 428                 dmas = <&pdma0 5
 429                         &pdma0 4>;
 430                 dma-names = "tx", "rx";
 431                 #address-cells = <1>;
 432                 #size-cells = <0>;
 433                 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
 434                 clock-names = "spi", "spi_busclk0";
 435                 pinctrl-names = "default";
 436                 pinctrl-0 = <&spi0_bus>;
 437         };
 438
 439         spi_1: spi@12d30000 {
 440                 compatible = "samsung,exynos4210-spi";
 441                 status = "disabled";
 442                 reg = <0x12d30000 0x100>;
 443                 interrupts = <0 67 0>;
 444                 dmas = <&pdma1 5
 445                         &pdma1 4>;
 446                 dma-names = "tx", "rx";
 447                 #address-cells = <1>;
 448                 #size-cells = <0>;
 449                 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
 450                 clock-names = "spi", "spi_busclk0";
 451                 pinctrl-names = "default";
 452                 pinctrl-0 = <&spi1_bus>;
 453         };
 454
 455         spi_2: spi@12d40000 {
 456                 compatible = "samsung,exynos4210-spi";
 457                 status = "disabled";
 458                 reg = <0x12d40000 0x100>;
 459                 interrupts = <0 68 0>;
 460                 dmas = <&pdma0 7
 461                         &pdma0 6>;
 462                 dma-names = "tx", "rx";
 463                 #address-cells = <1>;
 464                 #size-cells = <0>;
 465                 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
 466                 clock-names = "spi", "spi_busclk0";
 467                 pinctrl-names = "default";
 468                 pinctrl-0 = <&spi2_bus>;
 469         };
 470
 471         mmc_0: mmc@12200000 {
 472                 compatible = "samsung,exynos5250-dw-mshc";
 473                 interrupts = <0 75 0>;
 474                 #address-cells = <1>;
 475                 #size-cells = <0>;
 476                 reg = <0x12200000 0x1000>;
 477                 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
 478                 clock-names = "biu", "ciu";
 479                 fifo-depth = <0x80>;
 480                 status = "disabled";
 481         };
 482
 483         mmc_1: mmc@12210000 {
 484                 compatible = "samsung,exynos5250-dw-mshc";
 485                 interrupts = <0 76 0>;
 486                 #address-cells = <1>;
 487                 #size-cells = <0>;
 488                 reg = <0x12210000 0x1000>;
 489                 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
 490                 clock-names = "biu", "ciu";
 491                 fifo-depth = <0x80>;
 492                 status = "disabled";
 493         };
 494
 495         mmc_2: mmc@12220000 {
 496                 compatible = "samsung,exynos5250-dw-mshc";
 497                 interrupts = <0 77 0>;
 498                 #address-cells = <1>;
 499                 #size-cells = <0>;
 500                 reg = <0x12220000 0x1000>;
 501                 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
 502                 clock-names = "biu", "ciu";
 503                 fifo-depth = <0x80>;
 504                 status = "disabled";
 505         };
 506
 507         mmc_3: mmc@12230000 {
 508                 compatible = "samsung,exynos5250-dw-mshc";
 509                 reg = <0x12230000 0x1000>;
 510                 interrupts = <0 78 0>;
 511                 #address-cells = <1>;
 512                 #size-cells = <0>;
 513                 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
 514                 clock-names = "biu", "ciu";
 515                 fifo-depth = <0x80>;
 516                 status = "disabled";
 517         };
 518
 519         i2s0: i2s@03830000 {
 520                 compatible = "samsung,s5pv210-i2s";
 521                 status = "disabled";
 522                 reg = <0x03830000 0x100>;
 523                 dmas = <&pdma0 10
 524                         &pdma0 9
 525                         &pdma0 8>;
 526                 dma-names = "tx", "rx", "tx-sec";
 527                 clocks = <&clock_audss EXYNOS_I2S_BUS>,
 528                         <&clock_audss EXYNOS_I2S_BUS>,
 529                         <&clock_audss EXYNOS_SCLK_I2S>;
 530                 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
 531                 samsung,idma-addr = <0x03000000>;
 532                 pinctrl-names = "default";
 533                 pinctrl-0 = <&i2s0_bus>;
 534         };
 535
 536         i2s1: i2s@12D60000 {
 537                 compatible = "samsung,s3c6410-i2s";
 538                 status = "disabled";
 539                 reg = <0x12D60000 0x100>;
 540                 dmas = <&pdma1 12
 541                         &pdma1 11>;
 542                 dma-names = "tx", "rx";
 543                 clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
 544                 clock-names = "iis", "i2s_opclk0";
 545                 pinctrl-names = "default";
 546                 pinctrl-0 = <&i2s1_bus>;
 547         };
 548
 549         i2s2: i2s@12D70000 {
 550                 compatible = "samsung,s3c6410-i2s";
 551                 status = "disabled";
 552                 reg = <0x12D70000 0x100>;
 553                 dmas = <&pdma0 12
 554                         &pdma0 11>;
 555                 dma-names = "tx", "rx";
 556                 clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
 557                 clock-names = "iis", "i2s_opclk0";
 558                 pinctrl-names = "default";
 559                 pinctrl-0 = <&i2s2_bus>;
 560         };
 561
 562         usb@12000000 {
 563                 compatible = "samsung,exynos5250-dwusb3";
 564                 clocks = <&clock CLK_USB3>;
 565                 clock-names = "usbdrd30";
 566                 #address-cells = <1>;
 567                 #size-cells = <1>;
 568                 ranges;
 569
 570                 usbdrd_dwc3: dwc3 {
 571                         compatible = "synopsys,dwc3";
 572                         reg = <0x12000000 0x10000>;
 573                         interrupts = <0 72 0>;
 574                         phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
 575                         phy-names = "usb2-phy", "usb3-phy";
 576                 };
 577         };
 578
 579         usbdrd_phy: phy@12100000 {
 580                 compatible = "samsung,exynos5250-usbdrd-phy";
 581                 reg = <0x12100000 0x100>;
 582                 clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>;
 583                 clock-names = "phy", "ref";
 584                 samsung,pmu-syscon = <&pmu_system_controller>;
 585                 #phy-cells = <1>;
 586         };
 587
 588         ehci: usb@12110000 {
 589                 compatible = "samsung,exynos4210-ehci";
 590                 reg = <0x12110000 0x100>;
 591                 interrupts = <0 71 0>;
 592
 593                 clocks = <&clock CLK_USB2>;
 594                 clock-names = "usbhost";
 595                 #address-cells = <1>;
 596                 #size-cells = <0>;
 597                 port@0 {
 598                         reg = <0>;
 599                         phys = <&usb2_phy_gen 1>;
 600                 };
 601         };
 602
 603         ohci: usb@12120000 {
 604                 compatible = "samsung,exynos4210-ohci";
 605                 reg = <0x12120000 0x100>;
 606                 interrupts = <0 71 0>;
 607
 608                 clocks = <&clock CLK_USB2>;
 609                 clock-names = "usbhost";
 610                 #address-cells = <1>;
 611                 #size-cells = <0>;
 612                 port@0 {
 613                         reg = <0>;
 614                         phys = <&usb2_phy_gen 1>;
 615                 };
 616         };
 617
 618         usb2_phy_gen: phy@12130000 {
 619                 compatible = "samsung,exynos5250-usb2-phy";
 620                 reg = <0x12130000 0x100>;
 621                 clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>;
 622                 clock-names = "phy", "ref";
 623                 #phy-cells = <1>;
 624                 samsung,sysreg-phandle = <&sysreg_system_controller>;
 625                 samsung,pmureg-phandle = <&pmu_system_controller>;
 626         };
 627
 628         pwm: pwm@12dd0000 {
 629                 compatible = "samsung,exynos4210-pwm";
 630                 reg = <0x12dd0000 0x100>;
 631                 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
 632                 #pwm-cells = <3>;
 633                 clocks = <&clock CLK_PWM>;
 634                 clock-names = "timers";
 635         };
 636
 637         amba {
 638                 #address-cells = <1>;
 639                 #size-cells = <1>;
 640                 compatible = "arm,amba-bus";
 641                 interrupt-parent = <&gic>;
 642                 ranges;
 643
 644                 pdma0: pdma@121A0000 {
 645                         compatible = "arm,pl330", "arm,primecell";
 646                         reg = <0x121A0000 0x1000>;
 647                         interrupts = <0 34 0>;
 648                         clocks = <&clock CLK_PDMA0>;
 649                         clock-names = "apb_pclk";
 650                         #dma-cells = <1>;
 651                         #dma-channels = <8>;
 652                         #dma-requests = <32>;
 653                 };
 654
 655                 pdma1: pdma@121B0000 {
 656                         compatible = "arm,pl330", "arm,primecell";
 657                         reg = <0x121B0000 0x1000>;
 658                         interrupts = <0 35 0>;
 659                         clocks = <&clock CLK_PDMA1>;
 660                         clock-names = "apb_pclk";
 661                         #dma-cells = <1>;
 662                         #dma-channels = <8>;
 663                         #dma-requests = <32>;
 664                 };
 665
 666                 mdma0: mdma@10800000 {
 667                         compatible = "arm,pl330", "arm,primecell";
 668                         reg = <0x10800000 0x1000>;
 669                         interrupts = <0 33 0>;
 670                         clocks = <&clock CLK_MDMA0>;
 671                         clock-names = "apb_pclk";
 672                         #dma-cells = <1>;
 673                         #dma-channels = <8>;
 674                         #dma-requests = <1>;
 675                 };
 676
 677                 mdma1: mdma@11C10000 {
 678                         compatible = "arm,pl330", "arm,primecell";
 679                         reg = <0x11C10000 0x1000>;
 680                         interrupts = <0 124 0>;
 681                         clocks = <&clock CLK_MDMA1>;
 682                         clock-names = "apb_pclk";
 683                         #dma-cells = <1>;
 684                         #dma-channels = <8>;
 685                         #dma-requests = <1>;
 686                 };
 687         };
 688
 689         gsc_0:  gsc@13e00000 {
 690                 compatible = "samsung,exynos5-gsc";
 691                 reg = <0x13e00000 0x1000>;
 692                 interrupts = <0 85 0>;
 693                 power-domains = <&pd_gsc>;
 694                 clocks = <&clock CLK_GSCL0>;
 695                 clock-names = "gscl";
 696         };
 697
 698         gsc_1:  gsc@13e10000 {
 699                 compatible = "samsung,exynos5-gsc";
 700                 reg = <0x13e10000 0x1000>;
 701                 interrupts = <0 86 0>;
 702                 power-domains = <&pd_gsc>;
 703                 clocks = <&clock CLK_GSCL1>;
 704                 clock-names = "gscl";
 705         };
 706
 707         gsc_2:  gsc@13e20000 {
 708                 compatible = "samsung,exynos5-gsc";
 709                 reg = <0x13e20000 0x1000>;
 710                 interrupts = <0 87 0>;
 711                 power-domains = <&pd_gsc>;
 712                 clocks = <&clock CLK_GSCL2>;
 713                 clock-names = "gscl";
 714         };
 715
 716         gsc_3:  gsc@13e30000 {
 717                 compatible = "samsung,exynos5-gsc";
 718                 reg = <0x13e30000 0x1000>;
 719                 interrupts = <0 88 0>;
 720                 power-domains = <&pd_gsc>;
 721                 clocks = <&clock CLK_GSCL3>;
 722                 clock-names = "gscl";
 723         };
 724
 725         hdmi: hdmi {
 726                 compatible = "samsung,exynos4212-hdmi";
 727                 reg = <0x14530000 0x70000>;
 728                 power-domains = <&pd_disp1>;
 729                 interrupts = <0 95 0>;
 730                 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
 731                          <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
 732                          <&clock CLK_MOUT_HDMI>;
 733                 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
 734                                 "sclk_hdmiphy", "mout_hdmi";
 735                 samsung,syscon-phandle = <&pmu_system_controller>;
 736         };
 737
 738         mixer {
 739                 compatible = "samsung,exynos5250-mixer";
 740                 reg = <0x14450000 0x10000>;
 741                 power-domains = <&pd_disp1>;
 742                 interrupts = <0 94 0>;
 743                 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
 744                          <&clock CLK_SCLK_HDMI>;
 745                 clock-names = "mixer", "hdmi", "sclk_hdmi";
 746         };
 747
 748         dp_phy: video-phy@10040720 {
 749                 compatible = "samsung,exynos5250-dp-video-phy";
 750                 samsung,pmu-syscon = <&pmu_system_controller>;
 751                 #phy-cells = <0>;
 752         };
 753
 754         adc: adc@12D10000 {
 755                 compatible = "samsung,exynos-adc-v1";
 756                 reg = <0x12D10000 0x100>;
 757                 interrupts = <0 106 0>;
 758                 clocks = <&clock CLK_ADC>;
 759                 clock-names = "adc";
 760                 #io-channel-cells = <1>;
 761                 io-channel-ranges;
 762                 samsung,syscon-phandle = <&pmu_system_controller>;
 763                 status = "disabled";
 764         };
 765
 766         sss@10830000 {
 767                 compatible = "samsung,exynos4210-secss";
 768                 reg = <0x10830000 0x10000>;
 769                 interrupts = <0 112 0>;
 770                 clocks = <&clock CLK_SSS>;
 771                 clock-names = "secss";
 772         };
 773 };
 774
 775 &dp {
 776         power-domains = <&pd_disp1>;
 777         clocks = <&clock CLK_DP>;
 778         clock-names = "dp";
 779         phys = <&dp_phy>;
 780         phy-names = "dp";
 781 };
 782
 783 &fimd {
 784         power-domains = <&pd_disp1>;
 785         clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
 786         clock-names = "sclk_fimd", "fimd";
 787 };
 788
 789 &rtc {
 790         clocks = <&clock CLK_RTC>;
 791         clock-names = "rtc";
 792         interrupt-parent = <&pmu_system_controller>;
 793         status = "disabled";
 794 };
 795
 796 &serial_0 {
 797         clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
 798         clock-names = "uart", "clk_uart_baud0";
 799 };
 800
 801 &serial_1 {
 802         clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
 803         clock-names = "uart", "clk_uart_baud0";
 804 };
 805
 806 &serial_2 {
 807         clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
 808         clock-names = "uart", "clk_uart_baud0";
 809 };
 810
 811 &serial_3 {
 812         clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
 813         clock-names = "uart", "clk_uart_baud0";
 814 };