2 * SAMSUNG EXYNOS5250 SoC device tree source
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
8 * EXYNOS5250 based board files can include this file and provide
9 * values for board specfic bindings.
11 * Note: This file does not include device nodes for all the controllers in
12 * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
13 * additional nodes can be added to this file.
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
20 #include <dt-bindings/clock/exynos5250.h>
21 #include "exynos5.dtsi"
22 #include "exynos5250-pinctrl.dtsi"
23 #include "exynos4-cpu-thermal.dtsi"
24 #include <dt-bindings/clock/exynos-audss-clk.h>
27 compatible = "samsung,exynos5250", "samsung,exynos5";
51 pinctrl0 = &pinctrl_0;
52 pinctrl1 = &pinctrl_1;
53 pinctrl2 = &pinctrl_2;
54 pinctrl3 = &pinctrl_3;
63 compatible = "arm,cortex-a15";
65 clock-frequency = <1700000000>;
66 cooling-min-level = <15>;
67 cooling-max-level = <9>;
68 #cooling-cells = <2>; /* min followed by max */
72 compatible = "arm,cortex-a15";
74 clock-frequency = <1700000000>;
79 compatible = "mmio-sram";
80 reg = <0x02020000 0x30000>;
83 ranges = <0 0x02020000 0x30000>;
86 compatible = "samsung,exynos4210-sysram";
91 compatible = "samsung,exynos4210-sysram-ns";
92 reg = <0x2f000 0x1000>;
96 pd_gsc: gsc-power-domain@10044000 {
97 compatible = "samsung,exynos4210-pd";
98 reg = <0x10044000 0x20>;
99 #power-domain-cells = <0>;
102 pd_mfc: mfc-power-domain@10044040 {
103 compatible = "samsung,exynos4210-pd";
104 reg = <0x10044040 0x20>;
105 #power-domain-cells = <0>;
108 pd_disp1: disp1-power-domain@100440A0 {
109 compatible = "samsung,exynos4210-pd";
110 reg = <0x100440A0 0x20>;
111 #power-domain-cells = <0>;
114 clock: clock-controller@10010000 {
115 compatible = "samsung,exynos5250-clock";
116 reg = <0x10010000 0x30000>;
120 clock_audss: audss-clock-controller@3810000 {
121 compatible = "samsung,exynos5250-audss-clock";
122 reg = <0x03810000 0x0C>;
124 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
125 <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>;
126 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
130 compatible = "arm,armv7-timer";
131 interrupts = <1 13 0xf08>,
135 /* Unfortunately we need this since some versions of U-Boot
136 * on Exynos don't set the CNTFRQ register, so we need the
139 clock-frequency = <24000000>;
143 compatible = "samsung,exynos4210-mct";
144 reg = <0x101C0000 0x800>;
145 interrupt-controller;
146 #interrups-cells = <2>;
147 interrupt-parent = <&mct_map>;
148 interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
150 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
151 clock-names = "fin_pll", "mct";
154 #interrupt-cells = <2>;
155 #address-cells = <0>;
157 interrupt-map = <0x0 0 &combiner 23 3>,
158 <0x1 0 &combiner 23 4>,
159 <0x2 0 &combiner 25 2>,
160 <0x3 0 &combiner 25 3>,
161 <0x4 0 &gic 0 120 0>,
162 <0x5 0 &gic 0 121 0>;
167 compatible = "arm,cortex-a15-pmu";
168 interrupt-parent = <&combiner>;
169 interrupts = <1 2>, <22 4>;
172 pinctrl_0: pinctrl@11400000 {
173 compatible = "samsung,exynos5250-pinctrl";
174 reg = <0x11400000 0x1000>;
175 interrupts = <0 46 0>;
177 wakup_eint: wakeup-interrupt-controller {
178 compatible = "samsung,exynos4210-wakeup-eint";
179 interrupt-parent = <&gic>;
180 interrupts = <0 32 0>;
184 pinctrl_1: pinctrl@13400000 {
185 compatible = "samsung,exynos5250-pinctrl";
186 reg = <0x13400000 0x1000>;
187 interrupts = <0 45 0>;
190 pinctrl_2: pinctrl@10d10000 {
191 compatible = "samsung,exynos5250-pinctrl";
192 reg = <0x10d10000 0x1000>;
193 interrupts = <0 50 0>;
196 pinctrl_3: pinctrl@03860000 {
197 compatible = "samsung,exynos5250-pinctrl";
198 reg = <0x03860000 0x1000>;
199 interrupts = <0 47 0>;
202 pmu_system_controller: system-controller@10040000 {
203 compatible = "samsung,exynos5250-pmu", "syscon";
204 reg = <0x10040000 0x5000>;
205 clock-names = "clkout16";
206 clocks = <&clock CLK_FIN_PLL>;
210 sysreg_system_controller: syscon@10050000 {
211 compatible = "samsung,exynos5-sysreg", "syscon";
212 reg = <0x10050000 0x5000>;
216 compatible = "samsung,exynos5250-wdt";
217 reg = <0x101D0000 0x100>;
218 interrupts = <0 42 0>;
219 clocks = <&clock CLK_WDT>;
220 clock-names = "watchdog";
221 samsung,syscon-phandle = <&pmu_system_controller>;
225 compatible = "samsung,exynos5250-g2d";
226 reg = <0x10850000 0x1000>;
227 interrupts = <0 91 0>;
228 clocks = <&clock CLK_G2D>;
229 clock-names = "fimg2d";
232 mfc: codec@11000000 {
233 compatible = "samsung,mfc-v6";
234 reg = <0x11000000 0x10000>;
235 interrupts = <0 96 0>;
236 power-domains = <&pd_mfc>;
237 clocks = <&clock CLK_MFC>;
242 clocks = <&clock CLK_RTC>;
248 compatible = "samsung,exynos5250-tmu";
249 reg = <0x10060000 0x100>;
250 interrupts = <0 65 0>;
251 clocks = <&clock CLK_TMU>;
252 clock-names = "tmu_apbif";
253 #include "exynos4412-tmu-sensor-conf.dtsi"
257 cpu_thermal: cpu-thermal {
258 polling-delay-passive = <0>;
260 thermal-sensors = <&tmu 0>;
264 /* Corresponds to 800MHz at freq_table */
265 cooling-device = <&cpu0 9 9>;
268 /* Corresponds to 200MHz at freq_table */
269 cooling-device = <&cpu0 15 15>;
276 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
277 clock-names = "uart", "clk_uart_baud0";
281 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
282 clock-names = "uart", "clk_uart_baud0";
286 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
287 clock-names = "uart", "clk_uart_baud0";
291 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
292 clock-names = "uart", "clk_uart_baud0";
295 sata: sata@122F0000 {
296 compatible = "snps,dwc-ahci";
297 samsung,sata-freq = <66>;
298 reg = <0x122F0000 0x1ff>;
299 interrupts = <0 115 0>;
300 clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
301 clock-names = "sata", "sclk_sata";
303 phy-names = "sata-phy";
307 sata_phy: sata-phy@12170000 {
308 compatible = "samsung,exynos5250-sata-phy";
309 reg = <0x12170000 0x1ff>;
310 clocks = <&clock CLK_SATA_PHYCTRL>;
311 clock-names = "sata_phyctrl";
313 samsung,syscon-phandle = <&pmu_system_controller>;
317 i2c_0: i2c@12C60000 {
318 compatible = "samsung,s3c2440-i2c";
319 reg = <0x12C60000 0x100>;
320 interrupts = <0 56 0>;
321 #address-cells = <1>;
323 clocks = <&clock CLK_I2C0>;
325 pinctrl-names = "default";
326 pinctrl-0 = <&i2c0_bus>;
327 samsung,sysreg-phandle = <&sysreg_system_controller>;
331 i2c_1: i2c@12C70000 {
332 compatible = "samsung,s3c2440-i2c";
333 reg = <0x12C70000 0x100>;
334 interrupts = <0 57 0>;
335 #address-cells = <1>;
337 clocks = <&clock CLK_I2C1>;
339 pinctrl-names = "default";
340 pinctrl-0 = <&i2c1_bus>;
341 samsung,sysreg-phandle = <&sysreg_system_controller>;
345 i2c_2: i2c@12C80000 {
346 compatible = "samsung,s3c2440-i2c";
347 reg = <0x12C80000 0x100>;
348 interrupts = <0 58 0>;
349 #address-cells = <1>;
351 clocks = <&clock CLK_I2C2>;
353 pinctrl-names = "default";
354 pinctrl-0 = <&i2c2_bus>;
355 samsung,sysreg-phandle = <&sysreg_system_controller>;
359 i2c_3: i2c@12C90000 {
360 compatible = "samsung,s3c2440-i2c";
361 reg = <0x12C90000 0x100>;
362 interrupts = <0 59 0>;
363 #address-cells = <1>;
365 clocks = <&clock CLK_I2C3>;
367 pinctrl-names = "default";
368 pinctrl-0 = <&i2c3_bus>;
369 samsung,sysreg-phandle = <&sysreg_system_controller>;
373 i2c_4: i2c@12CA0000 {
374 compatible = "samsung,s3c2440-i2c";
375 reg = <0x12CA0000 0x100>;
376 interrupts = <0 60 0>;
377 #address-cells = <1>;
379 clocks = <&clock CLK_I2C4>;
381 pinctrl-names = "default";
382 pinctrl-0 = <&i2c4_bus>;
386 i2c_5: i2c@12CB0000 {
387 compatible = "samsung,s3c2440-i2c";
388 reg = <0x12CB0000 0x100>;
389 interrupts = <0 61 0>;
390 #address-cells = <1>;
392 clocks = <&clock CLK_I2C5>;
394 pinctrl-names = "default";
395 pinctrl-0 = <&i2c5_bus>;
399 i2c_6: i2c@12CC0000 {
400 compatible = "samsung,s3c2440-i2c";
401 reg = <0x12CC0000 0x100>;
402 interrupts = <0 62 0>;
403 #address-cells = <1>;
405 clocks = <&clock CLK_I2C6>;
407 pinctrl-names = "default";
408 pinctrl-0 = <&i2c6_bus>;
412 i2c_7: i2c@12CD0000 {
413 compatible = "samsung,s3c2440-i2c";
414 reg = <0x12CD0000 0x100>;
415 interrupts = <0 63 0>;
416 #address-cells = <1>;
418 clocks = <&clock CLK_I2C7>;
420 pinctrl-names = "default";
421 pinctrl-0 = <&i2c7_bus>;
425 i2c_8: i2c@12CE0000 {
426 compatible = "samsung,s3c2440-hdmiphy-i2c";
427 reg = <0x12CE0000 0x1000>;
428 interrupts = <0 64 0>;
429 #address-cells = <1>;
431 clocks = <&clock CLK_I2C_HDMI>;
436 i2c_9: i2c@121D0000 {
437 compatible = "samsung,exynos5-sata-phy-i2c";
438 reg = <0x121D0000 0x100>;
439 #address-cells = <1>;
441 clocks = <&clock CLK_SATA_PHYI2C>;
446 spi_0: spi@12d20000 {
447 compatible = "samsung,exynos4210-spi";
449 reg = <0x12d20000 0x100>;
450 interrupts = <0 66 0>;
453 dma-names = "tx", "rx";
454 #address-cells = <1>;
456 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
457 clock-names = "spi", "spi_busclk0";
458 pinctrl-names = "default";
459 pinctrl-0 = <&spi0_bus>;
462 spi_1: spi@12d30000 {
463 compatible = "samsung,exynos4210-spi";
465 reg = <0x12d30000 0x100>;
466 interrupts = <0 67 0>;
469 dma-names = "tx", "rx";
470 #address-cells = <1>;
472 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
473 clock-names = "spi", "spi_busclk0";
474 pinctrl-names = "default";
475 pinctrl-0 = <&spi1_bus>;
478 spi_2: spi@12d40000 {
479 compatible = "samsung,exynos4210-spi";
481 reg = <0x12d40000 0x100>;
482 interrupts = <0 68 0>;
485 dma-names = "tx", "rx";
486 #address-cells = <1>;
488 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
489 clock-names = "spi", "spi_busclk0";
490 pinctrl-names = "default";
491 pinctrl-0 = <&spi2_bus>;
494 mmc_0: mmc@12200000 {
495 compatible = "samsung,exynos5250-dw-mshc";
496 interrupts = <0 75 0>;
497 #address-cells = <1>;
499 reg = <0x12200000 0x1000>;
500 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
501 clock-names = "biu", "ciu";
506 mmc_1: mmc@12210000 {
507 compatible = "samsung,exynos5250-dw-mshc";
508 interrupts = <0 76 0>;
509 #address-cells = <1>;
511 reg = <0x12210000 0x1000>;
512 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
513 clock-names = "biu", "ciu";
518 mmc_2: mmc@12220000 {
519 compatible = "samsung,exynos5250-dw-mshc";
520 interrupts = <0 77 0>;
521 #address-cells = <1>;
523 reg = <0x12220000 0x1000>;
524 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
525 clock-names = "biu", "ciu";
530 mmc_3: mmc@12230000 {
531 compatible = "samsung,exynos5250-dw-mshc";
532 reg = <0x12230000 0x1000>;
533 interrupts = <0 78 0>;
534 #address-cells = <1>;
536 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
537 clock-names = "biu", "ciu";
543 compatible = "samsung,s5pv210-i2s";
545 reg = <0x03830000 0x100>;
549 dma-names = "tx", "rx", "tx-sec";
550 clocks = <&clock_audss EXYNOS_I2S_BUS>,
551 <&clock_audss EXYNOS_I2S_BUS>,
552 <&clock_audss EXYNOS_SCLK_I2S>;
553 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
554 samsung,idma-addr = <0x03000000>;
555 pinctrl-names = "default";
556 pinctrl-0 = <&i2s0_bus>;
560 compatible = "samsung,s3c6410-i2s";
562 reg = <0x12D60000 0x100>;
565 dma-names = "tx", "rx";
566 clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
567 clock-names = "iis", "i2s_opclk0";
568 pinctrl-names = "default";
569 pinctrl-0 = <&i2s1_bus>;
573 compatible = "samsung,s3c6410-i2s";
575 reg = <0x12D70000 0x100>;
578 dma-names = "tx", "rx";
579 clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
580 clock-names = "iis", "i2s_opclk0";
581 pinctrl-names = "default";
582 pinctrl-0 = <&i2s2_bus>;
586 compatible = "samsung,exynos5250-dwusb3";
587 clocks = <&clock CLK_USB3>;
588 clock-names = "usbdrd30";
589 #address-cells = <1>;
594 compatible = "synopsys,dwc3";
595 reg = <0x12000000 0x10000>;
596 interrupts = <0 72 0>;
597 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
598 phy-names = "usb2-phy", "usb3-phy";
602 usbdrd_phy: phy@12100000 {
603 compatible = "samsung,exynos5250-usbdrd-phy";
604 reg = <0x12100000 0x100>;
605 clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>;
606 clock-names = "phy", "ref";
607 samsung,pmu-syscon = <&pmu_system_controller>;
612 compatible = "samsung,exynos4210-ehci";
613 reg = <0x12110000 0x100>;
614 interrupts = <0 71 0>;
616 clocks = <&clock CLK_USB2>;
617 clock-names = "usbhost";
618 #address-cells = <1>;
622 phys = <&usb2_phy_gen 1>;
627 compatible = "samsung,exynos4210-ohci";
628 reg = <0x12120000 0x100>;
629 interrupts = <0 71 0>;
631 clocks = <&clock CLK_USB2>;
632 clock-names = "usbhost";
633 #address-cells = <1>;
637 phys = <&usb2_phy_gen 1>;
641 usb2_phy_gen: phy@12130000 {
642 compatible = "samsung,exynos5250-usb2-phy";
643 reg = <0x12130000 0x100>;
644 clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>;
645 clock-names = "phy", "ref";
647 samsung,sysreg-phandle = <&sysreg_system_controller>;
648 samsung,pmureg-phandle = <&pmu_system_controller>;
652 compatible = "samsung,exynos4210-pwm";
653 reg = <0x12dd0000 0x100>;
654 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
656 clocks = <&clock CLK_PWM>;
657 clock-names = "timers";
661 #address-cells = <1>;
663 compatible = "arm,amba-bus";
664 interrupt-parent = <&gic>;
667 pdma0: pdma@121A0000 {
668 compatible = "arm,pl330", "arm,primecell";
669 reg = <0x121A0000 0x1000>;
670 interrupts = <0 34 0>;
671 clocks = <&clock CLK_PDMA0>;
672 clock-names = "apb_pclk";
675 #dma-requests = <32>;
678 pdma1: pdma@121B0000 {
679 compatible = "arm,pl330", "arm,primecell";
680 reg = <0x121B0000 0x1000>;
681 interrupts = <0 35 0>;
682 clocks = <&clock CLK_PDMA1>;
683 clock-names = "apb_pclk";
686 #dma-requests = <32>;
689 mdma0: mdma@10800000 {
690 compatible = "arm,pl330", "arm,primecell";
691 reg = <0x10800000 0x1000>;
692 interrupts = <0 33 0>;
693 clocks = <&clock CLK_MDMA0>;
694 clock-names = "apb_pclk";
700 mdma1: mdma@11C10000 {
701 compatible = "arm,pl330", "arm,primecell";
702 reg = <0x11C10000 0x1000>;
703 interrupts = <0 124 0>;
704 clocks = <&clock CLK_MDMA1>;
705 clock-names = "apb_pclk";
712 gsc_0: gsc@13e00000 {
713 compatible = "samsung,exynos5-gsc";
714 reg = <0x13e00000 0x1000>;
715 interrupts = <0 85 0>;
716 power-domains = <&pd_gsc>;
717 clocks = <&clock CLK_GSCL0>;
718 clock-names = "gscl";
721 gsc_1: gsc@13e10000 {
722 compatible = "samsung,exynos5-gsc";
723 reg = <0x13e10000 0x1000>;
724 interrupts = <0 86 0>;
725 power-domains = <&pd_gsc>;
726 clocks = <&clock CLK_GSCL1>;
727 clock-names = "gscl";
730 gsc_2: gsc@13e20000 {
731 compatible = "samsung,exynos5-gsc";
732 reg = <0x13e20000 0x1000>;
733 interrupts = <0 87 0>;
734 power-domains = <&pd_gsc>;
735 clocks = <&clock CLK_GSCL2>;
736 clock-names = "gscl";
739 gsc_3: gsc@13e30000 {
740 compatible = "samsung,exynos5-gsc";
741 reg = <0x13e30000 0x1000>;
742 interrupts = <0 88 0>;
743 power-domains = <&pd_gsc>;
744 clocks = <&clock CLK_GSCL3>;
745 clock-names = "gscl";
749 compatible = "samsung,exynos4212-hdmi";
750 reg = <0x14530000 0x70000>;
751 power-domains = <&pd_disp1>;
752 interrupts = <0 95 0>;
753 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
754 <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
755 <&clock CLK_MOUT_HDMI>;
756 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
757 "sclk_hdmiphy", "mout_hdmi";
758 samsung,syscon-phandle = <&pmu_system_controller>;
762 compatible = "samsung,exynos5250-mixer";
763 reg = <0x14450000 0x10000>;
764 power-domains = <&pd_disp1>;
765 interrupts = <0 94 0>;
766 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
767 <&clock CLK_SCLK_HDMI>;
768 clock-names = "mixer", "hdmi", "sclk_hdmi";
771 dp_phy: video-phy@10040720 {
772 compatible = "samsung,exynos5250-dp-video-phy";
773 samsung,pmu-syscon = <&pmu_system_controller>;
777 dp: dp-controller@145B0000 {
778 power-domains = <&pd_disp1>;
779 clocks = <&clock CLK_DP>;
785 fimd: fimd@14400000 {
786 power-domains = <&pd_disp1>;
787 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
788 clock-names = "sclk_fimd", "fimd";
792 compatible = "samsung,exynos-adc-v1";
793 reg = <0x12D10000 0x100>;
794 interrupts = <0 106 0>;
795 clocks = <&clock CLK_ADC>;
797 #io-channel-cells = <1>;
799 samsung,syscon-phandle = <&pmu_system_controller>;
804 compatible = "samsung,exynos4210-secss";
805 reg = <0x10830000 0x10000>;
806 interrupts = <0 112 0>;
807 clocks = <&clock CLK_SSS>;
808 clock-names = "secss";