2 * SAMSUNG EXYNOS5260 SoC device tree source
4 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include "skeleton.dtsi"
14 #include <dt-bindings/clock/exynos5260-clk.h>
17 compatible = "samsung,exynos5260", "samsung,exynos5";
18 interrupt-parent = <&gic>;
21 pinctrl0 = &pinctrl_0;
22 pinctrl1 = &pinctrl_1;
23 pinctrl2 = &pinctrl_2;
32 compatible = "arm,cortex-a15";
34 cci-control-port = <&cci_control1>;
39 compatible = "arm,cortex-a15";
41 cci-control-port = <&cci_control1>;
46 compatible = "arm,cortex-a7";
48 cci-control-port = <&cci_control0>;
53 compatible = "arm,cortex-a7";
55 cci-control-port = <&cci_control0>;
60 compatible = "arm,cortex-a7";
62 cci-control-port = <&cci_control0>;
67 compatible = "arm,cortex-a7";
69 cci-control-port = <&cci_control0>;
74 compatible = "simple-bus";
79 clock_top: clock-controller@10010000 {
80 compatible = "samsung,exynos5260-clock-top";
81 reg = <0x10010000 0x10000>;
85 clock_peri: clock-controller@10200000 {
86 compatible = "samsung,exynos5260-clock-peri";
87 reg = <0x10200000 0x10000>;
91 clock_egl: clock-controller@10600000 {
92 compatible = "samsung,exynos5260-clock-egl";
93 reg = <0x10600000 0x10000>;
97 clock_kfc: clock-controller@10700000 {
98 compatible = "samsung,exynos5260-clock-kfc";
99 reg = <0x10700000 0x10000>;
103 clock_g2d: clock-controller@10A00000 {
104 compatible = "samsung,exynos5260-clock-g2d";
105 reg = <0x10A00000 0x10000>;
109 clock_mif: clock-controller@10CE0000 {
110 compatible = "samsung,exynos5260-clock-mif";
111 reg = <0x10CE0000 0x10000>;
115 clock_mfc: clock-controller@11090000 {
116 compatible = "samsung,exynos5260-clock-mfc";
117 reg = <0x11090000 0x10000>;
121 clock_g3d: clock-controller@11830000 {
122 compatible = "samsung,exynos5260-clock-g3d";
123 reg = <0x11830000 0x10000>;
127 clock_fsys: clock-controller@122E0000 {
128 compatible = "samsung,exynos5260-clock-fsys";
129 reg = <0x122E0000 0x10000>;
133 clock_aud: clock-controller@128C0000 {
134 compatible = "samsung,exynos5260-clock-aud";
135 reg = <0x128C0000 0x10000>;
139 clock_isp: clock-controller@133C0000 {
140 compatible = "samsung,exynos5260-clock-isp";
141 reg = <0x133C0000 0x10000>;
145 clock_gscl: clock-controller@13F00000 {
146 compatible = "samsung,exynos5260-clock-gscl";
147 reg = <0x13F00000 0x10000>;
151 clock_disp: clock-controller@14550000 {
152 compatible = "samsung,exynos5260-clock-disp";
153 reg = <0x14550000 0x10000>;
157 gic: interrupt-controller@10481000 {
158 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
159 #interrupt-cells = <3>;
160 #address-cells = <0>;
162 interrupt-controller;
163 reg = <0x10481000 0x1000>,
167 interrupts = <1 9 0xf04>;
170 chipid: chipid@10000000 {
171 compatible = "samsung,exynos4210-chipid";
172 reg = <0x10000000 0x100>;
176 compatible = "samsung,exynos4210-mct";
177 reg = <0x100B0000 0x1000>;
178 clocks = <&fin_pll>, <&clock_peri PERI_CLK_MCT>;
179 clock-names = "fin_pll", "mct";
180 interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
181 <0 107 0>, <0 122 0>, <0 123 0>,
182 <0 124 0>, <0 125 0>, <0 126 0>,
183 <0 127 0>, <0 128 0>, <0 129 0>;
187 compatible = "arm,cci-400";
188 #address-cells = <1>;
190 reg = <0x10F00000 0x1000>;
191 ranges = <0x0 0x10F00000 0x6000>;
193 cci_control0: slave-if@4000 {
194 compatible = "arm,cci-400-ctrl-if";
195 interface-type = "ace";
196 reg = <0x4000 0x1000>;
199 cci_control1: slave-if@5000 {
200 compatible = "arm,cci-400-ctrl-if";
201 interface-type = "ace";
202 reg = <0x5000 0x1000>;
206 pinctrl_0: pinctrl@11600000 {
207 compatible = "samsung,exynos5260-pinctrl";
208 reg = <0x11600000 0x1000>;
209 interrupts = <0 79 0>;
211 wakeup-interrupt-controller {
212 compatible = "samsung,exynos4210-wakeup-eint";
213 interrupt-parent = <&gic>;
214 interrupts = <0 32 0>;
218 pinctrl_1: pinctrl@12290000 {
219 compatible = "samsung,exynos5260-pinctrl";
220 reg = <0x12290000 0x1000>;
221 interrupts = <0 157 0>;
224 pinctrl_2: pinctrl@128B0000 {
225 compatible = "samsung,exynos5260-pinctrl";
226 reg = <0x128B0000 0x1000>;
227 interrupts = <0 243 0>;
230 uart0: serial@12C00000 {
231 compatible = "samsung,exynos4210-uart";
232 reg = <0x12C00000 0x100>;
233 interrupts = <0 146 0>;
234 clocks = <&clock_peri PERI_CLK_UART0>, <&clock_peri PERI_SCLK_UART0>;
235 clock-names = "uart", "clk_uart_baud0";
239 uart1: serial@12C10000 {
240 compatible = "samsung,exynos4210-uart";
241 reg = <0x12C10000 0x100>;
242 interrupts = <0 147 0>;
243 clocks = <&clock_peri PERI_CLK_UART1>, <&clock_peri PERI_SCLK_UART1>;
244 clock-names = "uart", "clk_uart_baud0";
248 uart2: serial@12C20000 {
249 compatible = "samsung,exynos4210-uart";
250 reg = <0x12C20000 0x100>;
251 interrupts = <0 148 0>;
252 clocks = <&clock_peri PERI_CLK_UART2>, <&clock_peri PERI_SCLK_UART2>;
253 clock-names = "uart", "clk_uart_baud0";
257 uart3: serial@12860000 {
258 compatible = "samsung,exynos4210-uart";
259 reg = <0x12860000 0x100>;
260 interrupts = <0 145 0>;
261 clocks = <&clock_aud AUD_CLK_AUD_UART>, <&clock_aud AUD_SCLK_AUD_UART>;
262 clock-names = "uart", "clk_uart_baud0";
266 mmc_0: mmc@12140000 {
267 compatible = "samsung,exynos5250-dw-mshc";
268 reg = <0x12140000 0x2000>;
269 interrupts = <0 156 0>;
270 #address-cells = <1>;
272 clocks = <&clock_fsys FSYS_CLK_MMC0>, <&clock_top TOP_SCLK_MMC0>;
273 clock-names = "biu", "ciu";
278 mmc_1: mmc@12150000 {
279 compatible = "samsung,exynos5250-dw-mshc";
280 reg = <0x12150000 0x2000>;
281 interrupts = <0 158 0>;
282 #address-cells = <1>;
284 clocks = <&clock_fsys FSYS_CLK_MMC1>, <&clock_top TOP_SCLK_MMC1>;
285 clock-names = "biu", "ciu";
290 mmc_2: mmc@12160000 {
291 compatible = "samsung,exynos5250-dw-mshc";
292 reg = <0x12160000 0x2000>;
293 interrupts = <0 159 0>;
294 #address-cells = <1>;
296 clocks = <&clock_fsys FSYS_CLK_MMC2>, <&clock_top TOP_SCLK_MMC2>;
297 clock-names = "biu", "ciu";
304 #include "exynos5260-pinctrl.dtsi"