2 * SAMSUNG EXYNOS5420 SoC device tree source
4 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
8 * EXYNOS5420 based board files can include this file and provide
9 * values for board specfic bindings.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <dt-bindings/clock/exynos5420.h>
17 #include "exynos5.dtsi"
18 #include "exynos5420-pinctrl.dtsi"
20 #include <dt-bindings/clock/exynos-audss-clk.h>
23 compatible = "samsung,exynos5420", "samsung,exynos5";
29 pinctrl0 = &pinctrl_0;
30 pinctrl1 = &pinctrl_1;
31 pinctrl2 = &pinctrl_2;
32 pinctrl3 = &pinctrl_3;
33 pinctrl4 = &pinctrl_4;
50 usbdrdphy0 = &usbdrd_phy0;
51 usbdrdphy1 = &usbdrd_phy1;
60 compatible = "arm,cortex-a15";
62 clock-frequency = <1800000000>;
63 cci-control-port = <&cci_control1>;
68 compatible = "arm,cortex-a15";
70 clock-frequency = <1800000000>;
71 cci-control-port = <&cci_control1>;
76 compatible = "arm,cortex-a15";
78 clock-frequency = <1800000000>;
79 cci-control-port = <&cci_control1>;
84 compatible = "arm,cortex-a15";
86 clock-frequency = <1800000000>;
87 cci-control-port = <&cci_control1>;
92 compatible = "arm,cortex-a7";
94 clock-frequency = <1000000000>;
95 cci-control-port = <&cci_control0>;
100 compatible = "arm,cortex-a7";
102 clock-frequency = <1000000000>;
103 cci-control-port = <&cci_control0>;
108 compatible = "arm,cortex-a7";
110 clock-frequency = <1000000000>;
111 cci-control-port = <&cci_control0>;
116 compatible = "arm,cortex-a7";
118 clock-frequency = <1000000000>;
119 cci-control-port = <&cci_control0>;
124 compatible = "arm,cci-400";
125 #address-cells = <1>;
127 reg = <0x10d20000 0x1000>;
128 ranges = <0x0 0x10d20000 0x6000>;
130 cci_control0: slave-if@4000 {
131 compatible = "arm,cci-400-ctrl-if";
132 interface-type = "ace";
133 reg = <0x4000 0x1000>;
135 cci_control1: slave-if@5000 {
136 compatible = "arm,cci-400-ctrl-if";
137 interface-type = "ace";
138 reg = <0x5000 0x1000>;
143 compatible = "mmio-sram";
144 reg = <0x02020000 0x54000>;
145 #address-cells = <1>;
147 ranges = <0 0x02020000 0x54000>;
150 compatible = "samsung,exynos4210-sysram";
155 compatible = "samsung,exynos4210-sysram-ns";
156 reg = <0x53000 0x1000>;
160 clock: clock-controller@10010000 {
161 compatible = "samsung,exynos5420-clock";
162 reg = <0x10010000 0x30000>;
166 clock_audss: audss-clock-controller@3810000 {
167 compatible = "samsung,exynos5420-audss-clock";
168 reg = <0x03810000 0x0C>;
170 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
171 <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
172 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
175 mfc: codec@11000000 {
176 compatible = "samsung,mfc-v7";
177 reg = <0x11000000 0x10000>;
178 interrupts = <0 96 0>;
179 clocks = <&clock CLK_MFC>;
181 samsung,power-domain = <&mfc_pd>;
184 mmc_0: mmc@12200000 {
185 compatible = "samsung,exynos5420-dw-mshc-smu";
186 interrupts = <0 75 0>;
187 #address-cells = <1>;
189 reg = <0x12200000 0x2000>;
190 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
191 clock-names = "biu", "ciu";
196 mmc_1: mmc@12210000 {
197 compatible = "samsung,exynos5420-dw-mshc-smu";
198 interrupts = <0 76 0>;
199 #address-cells = <1>;
201 reg = <0x12210000 0x2000>;
202 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
203 clock-names = "biu", "ciu";
208 mmc_2: mmc@12220000 {
209 compatible = "samsung,exynos5420-dw-mshc";
210 interrupts = <0 77 0>;
211 #address-cells = <1>;
213 reg = <0x12220000 0x1000>;
214 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
215 clock-names = "biu", "ciu";
221 compatible = "samsung,exynos4210-mct";
222 reg = <0x101C0000 0x800>;
223 interrupt-controller;
224 #interrups-cells = <1>;
225 interrupt-parent = <&mct_map>;
226 interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
227 <8>, <9>, <10>, <11>;
228 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
229 clock-names = "fin_pll", "mct";
232 #interrupt-cells = <1>;
233 #address-cells = <0>;
235 interrupt-map = <0 &combiner 23 3>,
250 gsc_pd: power-domain@10044000 {
251 compatible = "samsung,exynos4210-pd";
252 reg = <0x10044000 0x20>;
255 isp_pd: power-domain@10044020 {
256 compatible = "samsung,exynos4210-pd";
257 reg = <0x10044020 0x20>;
260 mfc_pd: power-domain@10044060 {
261 compatible = "samsung,exynos4210-pd";
262 reg = <0x10044060 0x20>;
263 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK333>,
264 <&clock CLK_MOUT_USER_ACLK333>;
265 clock-names = "oscclk", "pclk0", "clk0";
268 disp_pd: power-domain@100440C0 {
269 compatible = "samsung,exynos4210-pd";
270 reg = <0x100440C0 0x20>;
273 msc_pd: power-domain@10044120 {
274 compatible = "samsung,exynos4210-pd";
275 reg = <0x10044120 0x20>;
278 pinctrl_0: pinctrl@13400000 {
279 compatible = "samsung,exynos5420-pinctrl";
280 reg = <0x13400000 0x1000>;
281 interrupts = <0 45 0>;
283 wakeup-interrupt-controller {
284 compatible = "samsung,exynos4210-wakeup-eint";
285 interrupt-parent = <&gic>;
286 interrupts = <0 32 0>;
290 pinctrl_1: pinctrl@13410000 {
291 compatible = "samsung,exynos5420-pinctrl";
292 reg = <0x13410000 0x1000>;
293 interrupts = <0 78 0>;
296 pinctrl_2: pinctrl@14000000 {
297 compatible = "samsung,exynos5420-pinctrl";
298 reg = <0x14000000 0x1000>;
299 interrupts = <0 46 0>;
302 pinctrl_3: pinctrl@14010000 {
303 compatible = "samsung,exynos5420-pinctrl";
304 reg = <0x14010000 0x1000>;
305 interrupts = <0 50 0>;
308 pinctrl_4: pinctrl@03860000 {
309 compatible = "samsung,exynos5420-pinctrl";
310 reg = <0x03860000 0x1000>;
311 interrupts = <0 47 0>;
315 clocks = <&clock CLK_RTC>;
321 #address-cells = <1>;
323 compatible = "arm,amba-bus";
324 interrupt-parent = <&gic>;
327 adma: adma@03880000 {
328 compatible = "arm,pl330", "arm,primecell";
329 reg = <0x03880000 0x1000>;
330 interrupts = <0 110 0>;
331 clocks = <&clock_audss EXYNOS_ADMA>;
332 clock-names = "apb_pclk";
335 #dma-requests = <16>;
338 pdma0: pdma@121A0000 {
339 compatible = "arm,pl330", "arm,primecell";
340 reg = <0x121A0000 0x1000>;
341 interrupts = <0 34 0>;
342 clocks = <&clock CLK_PDMA0>;
343 clock-names = "apb_pclk";
346 #dma-requests = <32>;
349 pdma1: pdma@121B0000 {
350 compatible = "arm,pl330", "arm,primecell";
351 reg = <0x121B0000 0x1000>;
352 interrupts = <0 35 0>;
353 clocks = <&clock CLK_PDMA1>;
354 clock-names = "apb_pclk";
357 #dma-requests = <32>;
360 mdma0: mdma@10800000 {
361 compatible = "arm,pl330", "arm,primecell";
362 reg = <0x10800000 0x1000>;
363 interrupts = <0 33 0>;
364 clocks = <&clock CLK_MDMA0>;
365 clock-names = "apb_pclk";
371 mdma1: mdma@11C10000 {
372 compatible = "arm,pl330", "arm,primecell";
373 reg = <0x11C10000 0x1000>;
374 interrupts = <0 124 0>;
375 clocks = <&clock CLK_MDMA1>;
376 clock-names = "apb_pclk";
381 * MDMA1 can support both secure and non-secure
382 * AXI transactions. When this is enabled in the kernel
383 * for boards that run in secure mode, we are getting
384 * imprecise external aborts causing the kernel to oops.
391 compatible = "samsung,exynos5420-i2s";
392 reg = <0x03830000 0x100>;
396 dma-names = "tx", "rx", "tx-sec";
397 clocks = <&clock_audss EXYNOS_I2S_BUS>,
398 <&clock_audss EXYNOS_I2S_BUS>,
399 <&clock_audss EXYNOS_SCLK_I2S>;
400 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
401 samsung,idma-addr = <0x03000000>;
402 pinctrl-names = "default";
403 pinctrl-0 = <&i2s0_bus>;
408 compatible = "samsung,exynos5420-i2s";
409 reg = <0x12D60000 0x100>;
412 dma-names = "tx", "rx";
413 clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
414 clock-names = "iis", "i2s_opclk0";
415 pinctrl-names = "default";
416 pinctrl-0 = <&i2s1_bus>;
421 compatible = "samsung,exynos5420-i2s";
422 reg = <0x12D70000 0x100>;
425 dma-names = "tx", "rx";
426 clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
427 clock-names = "iis", "i2s_opclk0";
428 pinctrl-names = "default";
429 pinctrl-0 = <&i2s2_bus>;
433 spi_0: spi@12d20000 {
434 compatible = "samsung,exynos4210-spi";
435 reg = <0x12d20000 0x100>;
436 interrupts = <0 68 0>;
439 dma-names = "tx", "rx";
440 #address-cells = <1>;
442 pinctrl-names = "default";
443 pinctrl-0 = <&spi0_bus>;
444 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
445 clock-names = "spi", "spi_busclk0";
449 spi_1: spi@12d30000 {
450 compatible = "samsung,exynos4210-spi";
451 reg = <0x12d30000 0x100>;
452 interrupts = <0 69 0>;
455 dma-names = "tx", "rx";
456 #address-cells = <1>;
458 pinctrl-names = "default";
459 pinctrl-0 = <&spi1_bus>;
460 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
461 clock-names = "spi", "spi_busclk0";
465 spi_2: spi@12d40000 {
466 compatible = "samsung,exynos4210-spi";
467 reg = <0x12d40000 0x100>;
468 interrupts = <0 70 0>;
471 dma-names = "tx", "rx";
472 #address-cells = <1>;
474 pinctrl-names = "default";
475 pinctrl-0 = <&spi2_bus>;
476 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
477 clock-names = "spi", "spi_busclk0";
481 uart_0: serial@12C00000 {
482 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
483 clock-names = "uart", "clk_uart_baud0";
486 uart_1: serial@12C10000 {
487 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
488 clock-names = "uart", "clk_uart_baud0";
491 uart_2: serial@12C20000 {
492 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
493 clock-names = "uart", "clk_uart_baud0";
496 uart_3: serial@12C30000 {
497 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
498 clock-names = "uart", "clk_uart_baud0";
502 compatible = "samsung,exynos4210-pwm";
503 reg = <0x12dd0000 0x100>;
504 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
506 clocks = <&clock CLK_PWM>;
507 clock-names = "timers";
510 dp_phy: video-phy@10040728 {
511 compatible = "samsung,exynos5250-dp-video-phy";
512 reg = <0x10040728 4>;
516 dp: dp-controller@145B0000 {
517 clocks = <&clock CLK_DP1>;
523 mipi_phy: video-phy@10040714 {
524 compatible = "samsung,s5pv210-mipi-video-phy";
525 reg = <0x10040714 12>;
530 compatible = "samsung,exynos5410-mipi-dsi";
531 reg = <0x14500000 0x10000>;
532 interrupts = <0 82 0>;
533 samsung,power-domain = <&disp_pd>;
534 phys = <&mipi_phy 1>;
536 clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>;
537 clock-names = "bus_clk", "pll_clk";
538 #address-cells = <1>;
543 fimd: fimd@14400000 {
544 samsung,power-domain = <&disp_pd>;
545 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
546 clock-names = "sclk_fimd", "fimd";
550 compatible = "samsung,exynos-adc-v2";
551 reg = <0x12D10000 0x100>, <0x10040720 0x4>;
552 interrupts = <0 106 0>;
553 clocks = <&clock CLK_TSADC>;
555 #io-channel-cells = <1>;
560 i2c_0: i2c@12C60000 {
561 compatible = "samsung,s3c2440-i2c";
562 reg = <0x12C60000 0x100>;
563 interrupts = <0 56 0>;
564 #address-cells = <1>;
566 clocks = <&clock CLK_I2C0>;
568 pinctrl-names = "default";
569 pinctrl-0 = <&i2c0_bus>;
573 i2c_1: i2c@12C70000 {
574 compatible = "samsung,s3c2440-i2c";
575 reg = <0x12C70000 0x100>;
576 interrupts = <0 57 0>;
577 #address-cells = <1>;
579 clocks = <&clock CLK_I2C1>;
581 pinctrl-names = "default";
582 pinctrl-0 = <&i2c1_bus>;
586 i2c_2: i2c@12C80000 {
587 compatible = "samsung,s3c2440-i2c";
588 reg = <0x12C80000 0x100>;
589 interrupts = <0 58 0>;
590 #address-cells = <1>;
592 clocks = <&clock CLK_I2C2>;
594 pinctrl-names = "default";
595 pinctrl-0 = <&i2c2_bus>;
599 i2c_3: i2c@12C90000 {
600 compatible = "samsung,s3c2440-i2c";
601 reg = <0x12C90000 0x100>;
602 interrupts = <0 59 0>;
603 #address-cells = <1>;
605 clocks = <&clock CLK_I2C3>;
607 pinctrl-names = "default";
608 pinctrl-0 = <&i2c3_bus>;
612 hsi2c_4: i2c@12CA0000 {
613 compatible = "samsung,exynos5-hsi2c";
614 reg = <0x12CA0000 0x1000>;
615 interrupts = <0 60 0>;
616 #address-cells = <1>;
618 pinctrl-names = "default";
619 pinctrl-0 = <&i2c4_hs_bus>;
620 clocks = <&clock CLK_USI0>;
621 clock-names = "hsi2c";
625 hsi2c_5: i2c@12CB0000 {
626 compatible = "samsung,exynos5-hsi2c";
627 reg = <0x12CB0000 0x1000>;
628 interrupts = <0 61 0>;
629 #address-cells = <1>;
631 pinctrl-names = "default";
632 pinctrl-0 = <&i2c5_hs_bus>;
633 clocks = <&clock CLK_USI1>;
634 clock-names = "hsi2c";
638 hsi2c_6: i2c@12CC0000 {
639 compatible = "samsung,exynos5-hsi2c";
640 reg = <0x12CC0000 0x1000>;
641 interrupts = <0 62 0>;
642 #address-cells = <1>;
644 pinctrl-names = "default";
645 pinctrl-0 = <&i2c6_hs_bus>;
646 clocks = <&clock CLK_USI2>;
647 clock-names = "hsi2c";
651 hsi2c_7: i2c@12CD0000 {
652 compatible = "samsung,exynos5-hsi2c";
653 reg = <0x12CD0000 0x1000>;
654 interrupts = <0 63 0>;
655 #address-cells = <1>;
657 pinctrl-names = "default";
658 pinctrl-0 = <&i2c7_hs_bus>;
659 clocks = <&clock CLK_USI3>;
660 clock-names = "hsi2c";
664 hsi2c_8: i2c@12E00000 {
665 compatible = "samsung,exynos5-hsi2c";
666 reg = <0x12E00000 0x1000>;
667 interrupts = <0 87 0>;
668 #address-cells = <1>;
670 pinctrl-names = "default";
671 pinctrl-0 = <&i2c8_hs_bus>;
672 clocks = <&clock CLK_USI4>;
673 clock-names = "hsi2c";
677 hsi2c_9: i2c@12E10000 {
678 compatible = "samsung,exynos5-hsi2c";
679 reg = <0x12E10000 0x1000>;
680 interrupts = <0 88 0>;
681 #address-cells = <1>;
683 pinctrl-names = "default";
684 pinctrl-0 = <&i2c9_hs_bus>;
685 clocks = <&clock CLK_USI5>;
686 clock-names = "hsi2c";
690 hsi2c_10: i2c@12E20000 {
691 compatible = "samsung,exynos5-hsi2c";
692 reg = <0x12E20000 0x1000>;
693 interrupts = <0 203 0>;
694 #address-cells = <1>;
696 pinctrl-names = "default";
697 pinctrl-0 = <&i2c10_hs_bus>;
698 clocks = <&clock CLK_USI6>;
699 clock-names = "hsi2c";
703 hdmi: hdmi@14530000 {
704 compatible = "samsung,exynos5420-hdmi";
705 reg = <0x14530000 0x70000>;
706 interrupts = <0 95 0>;
707 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
708 <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
709 <&clock CLK_MOUT_HDMI>;
710 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
711 "sclk_hdmiphy", "mout_hdmi";
713 samsung,syscon-phandle = <&pmu_system_controller>;
717 hdmiphy: hdmiphy@145D0000 {
718 reg = <0x145D0000 0x20>;
721 mixer: mixer@14450000 {
722 compatible = "samsung,exynos5420-mixer";
723 reg = <0x14450000 0x10000>;
724 interrupts = <0 94 0>;
725 clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>;
726 clock-names = "mixer", "sclk_hdmi";
729 gsc_0: video-scaler@13e00000 {
730 compatible = "samsung,exynos5-gsc";
731 reg = <0x13e00000 0x1000>;
732 interrupts = <0 85 0>;
733 clocks = <&clock CLK_GSCL0>;
734 clock-names = "gscl";
735 samsung,power-domain = <&gsc_pd>;
738 gsc_1: video-scaler@13e10000 {
739 compatible = "samsung,exynos5-gsc";
740 reg = <0x13e10000 0x1000>;
741 interrupts = <0 86 0>;
742 clocks = <&clock CLK_GSCL1>;
743 clock-names = "gscl";
744 samsung,power-domain = <&gsc_pd>;
747 pmu_system_controller: system-controller@10040000 {
748 compatible = "samsung,exynos5420-pmu", "syscon";
749 reg = <0x10040000 0x5000>;
750 clock-names = "clkout16";
751 clocks = <&clock CLK_FIN_PLL>;
755 sysreg_system_controller: syscon@10050000 {
756 compatible = "samsung,exynos5-sysreg", "syscon";
757 reg = <0x10050000 0x5000>;
760 tmu_cpu0: tmu@10060000 {
761 compatible = "samsung,exynos5420-tmu";
762 reg = <0x10060000 0x100>;
763 interrupts = <0 65 0>;
764 clocks = <&clock CLK_TMU>;
765 clock-names = "tmu_apbif";
768 tmu_cpu1: tmu@10064000 {
769 compatible = "samsung,exynos5420-tmu";
770 reg = <0x10064000 0x100>;
771 interrupts = <0 183 0>;
772 clocks = <&clock CLK_TMU>;
773 clock-names = "tmu_apbif";
776 tmu_cpu2: tmu@10068000 {
777 compatible = "samsung,exynos5420-tmu-ext-triminfo";
778 reg = <0x10068000 0x100>, <0x1006c000 0x4>;
779 interrupts = <0 184 0>;
780 clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
781 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
784 tmu_cpu3: tmu@1006c000 {
785 compatible = "samsung,exynos5420-tmu-ext-triminfo";
786 reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
787 interrupts = <0 185 0>;
788 clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
789 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
792 tmu_gpu: tmu@100a0000 {
793 compatible = "samsung,exynos5420-tmu-ext-triminfo";
794 reg = <0x100a0000 0x100>, <0x10068000 0x4>;
795 interrupts = <0 215 0>;
796 clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
797 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
800 watchdog: watchdog@101D0000 {
801 compatible = "samsung,exynos5420-wdt";
802 reg = <0x101D0000 0x100>;
803 interrupts = <0 42 0>;
804 clocks = <&clock CLK_WDT>;
805 clock-names = "watchdog";
806 samsung,syscon-phandle = <&pmu_system_controller>;
810 compatible = "samsung,exynos4210-secss";
811 reg = <0x10830000 0x10000>;
812 interrupts = <0 112 0>;
813 clocks = <&clock CLK_SSS>;
814 clock-names = "secss";
817 usbdrd3_0: usb@12000000 {
818 compatible = "samsung,exynos5250-dwusb3";
819 clocks = <&clock CLK_USBD300>;
820 clock-names = "usbdrd30";
821 #address-cells = <1>;
826 compatible = "snps,dwc3";
827 reg = <0x12000000 0x10000>;
828 interrupts = <0 72 0>;
829 phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
830 phy-names = "usb2-phy", "usb3-phy";
834 usbdrd_phy0: phy@12100000 {
835 compatible = "samsung,exynos5420-usbdrd-phy";
836 reg = <0x12100000 0x100>;
837 clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
838 clock-names = "phy", "ref";
839 samsung,pmu-syscon = <&pmu_system_controller>;
843 usbdrd3_1: usb@12400000 {
844 compatible = "samsung,exynos5250-dwusb3";
845 clocks = <&clock CLK_USBD301>;
846 clock-names = "usbdrd30";
847 #address-cells = <1>;
852 compatible = "snps,dwc3";
853 reg = <0x12400000 0x10000>;
854 interrupts = <0 73 0>;
855 phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>;
856 phy-names = "usb2-phy", "usb3-phy";
860 usbdrd_phy1: phy@12500000 {
861 compatible = "samsung,exynos5420-usbdrd-phy";
862 reg = <0x12500000 0x100>;
863 clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
864 clock-names = "phy", "ref";
865 samsung,pmu-syscon = <&pmu_system_controller>;
869 usbhost2: usb@12110000 {
870 compatible = "samsung,exynos4210-ehci";
871 reg = <0x12110000 0x100>;
872 interrupts = <0 71 0>;
874 clocks = <&clock CLK_USBH20>;
875 clock-names = "usbhost";
876 #address-cells = <1>;
880 phys = <&usb2_phy 1>;
884 usbhost1: usb@12120000 {
885 compatible = "samsung,exynos4210-ohci";
886 reg = <0x12120000 0x100>;
887 interrupts = <0 71 0>;
889 clocks = <&clock CLK_USBH20>;
890 clock-names = "usbhost";
891 #address-cells = <1>;
895 phys = <&usb2_phy 1>;
899 usb2_phy: phy@12130000 {
900 compatible = "samsung,exynos5250-usb2-phy";
901 reg = <0x12130000 0x100>;
902 clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
903 clock-names = "phy", "ref";
905 samsung,sysreg-phandle = <&sysreg_system_controller>;
906 samsung,pmureg-phandle = <&pmu_system_controller>;