2 * SAMSUNG EXYNOS5420 SoC device tree source
4 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
8 * EXYNOS5420 based board files can include this file and provide
9 * values for board specfic bindings.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <dt-bindings/clock/exynos5420.h>
17 #include "exynos5.dtsi"
18 #include "exynos5420-pinctrl.dtsi"
20 #include <dt-bindings/clock/exynos-audss-clk.h>
23 compatible = "samsung,exynos5420", "samsung,exynos5";
29 pinctrl0 = &pinctrl_0;
30 pinctrl1 = &pinctrl_1;
31 pinctrl2 = &pinctrl_2;
32 pinctrl3 = &pinctrl_3;
33 pinctrl4 = &pinctrl_4;
50 usbdrdphy0 = &usbdrd_phy0;
51 usbdrdphy1 = &usbdrd_phy1;
60 compatible = "arm,cortex-a15";
62 clock-frequency = <1800000000>;
63 cci-control-port = <&cci_control1>;
68 compatible = "arm,cortex-a15";
70 clock-frequency = <1800000000>;
71 cci-control-port = <&cci_control1>;
76 compatible = "arm,cortex-a15";
78 clock-frequency = <1800000000>;
79 cci-control-port = <&cci_control1>;
84 compatible = "arm,cortex-a15";
86 clock-frequency = <1800000000>;
87 cci-control-port = <&cci_control1>;
92 compatible = "arm,cortex-a7";
94 clock-frequency = <1000000000>;
95 cci-control-port = <&cci_control0>;
100 compatible = "arm,cortex-a7";
102 clock-frequency = <1000000000>;
103 cci-control-port = <&cci_control0>;
108 compatible = "arm,cortex-a7";
110 clock-frequency = <1000000000>;
111 cci-control-port = <&cci_control0>;
116 compatible = "arm,cortex-a7";
118 clock-frequency = <1000000000>;
119 cci-control-port = <&cci_control0>;
124 compatible = "arm,cci-400";
125 #address-cells = <1>;
127 reg = <0x10d20000 0x1000>;
128 ranges = <0x0 0x10d20000 0x6000>;
130 cci_control0: slave-if@4000 {
131 compatible = "arm,cci-400-ctrl-if";
132 interface-type = "ace";
133 reg = <0x4000 0x1000>;
135 cci_control1: slave-if@5000 {
136 compatible = "arm,cci-400-ctrl-if";
137 interface-type = "ace";
138 reg = <0x5000 0x1000>;
143 compatible = "mmio-sram";
144 reg = <0x02020000 0x54000>;
145 #address-cells = <1>;
147 ranges = <0 0x02020000 0x54000>;
150 compatible = "samsung,exynos4210-sysram";
155 compatible = "samsung,exynos4210-sysram-ns";
156 reg = <0x53000 0x1000>;
160 clock: clock-controller@10010000 {
161 compatible = "samsung,exynos5420-clock";
162 reg = <0x10010000 0x30000>;
166 clock_audss: audss-clock-controller@3810000 {
167 compatible = "samsung,exynos5420-audss-clock";
168 reg = <0x03810000 0x0C>;
170 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
171 <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
172 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
175 mfc: codec@11000000 {
176 compatible = "samsung,mfc-v7";
177 reg = <0x11000000 0x10000>;
178 interrupts = <0 96 0>;
179 clocks = <&clock CLK_MFC>;
181 samsung,power-domain = <&mfc_pd>;
184 mmc_0: mmc@12200000 {
185 compatible = "samsung,exynos5420-dw-mshc-smu";
186 interrupts = <0 75 0>;
187 #address-cells = <1>;
189 reg = <0x12200000 0x2000>;
190 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
191 clock-names = "biu", "ciu";
196 mmc_1: mmc@12210000 {
197 compatible = "samsung,exynos5420-dw-mshc-smu";
198 interrupts = <0 76 0>;
199 #address-cells = <1>;
201 reg = <0x12210000 0x2000>;
202 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
203 clock-names = "biu", "ciu";
208 mmc_2: mmc@12220000 {
209 compatible = "samsung,exynos5420-dw-mshc";
210 interrupts = <0 77 0>;
211 #address-cells = <1>;
213 reg = <0x12220000 0x1000>;
214 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
215 clock-names = "biu", "ciu";
221 compatible = "samsung,exynos4210-mct";
222 reg = <0x101C0000 0x800>;
223 interrupt-controller;
224 #interrups-cells = <1>;
225 interrupt-parent = <&mct_map>;
226 interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
227 <8>, <9>, <10>, <11>;
228 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
229 clock-names = "fin_pll", "mct";
232 #interrupt-cells = <1>;
233 #address-cells = <0>;
235 interrupt-map = <0 &combiner 23 3>,
250 gsc_pd: power-domain@10044000 {
251 compatible = "samsung,exynos4210-pd";
252 reg = <0x10044000 0x20>;
255 isp_pd: power-domain@10044020 {
256 compatible = "samsung,exynos4210-pd";
257 reg = <0x10044020 0x20>;
260 mfc_pd: power-domain@10044060 {
261 compatible = "samsung,exynos4210-pd";
262 reg = <0x10044060 0x20>;
263 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK333>,
264 <&clock CLK_MOUT_USER_ACLK333>;
265 clock-names = "oscclk", "pclk0", "clk0";
268 disp_pd: power-domain@100440C0 {
269 compatible = "samsung,exynos4210-pd";
270 reg = <0x100440C0 0x20>;
273 msc_pd: power-domain@10044120 {
274 compatible = "samsung,exynos4210-pd";
275 reg = <0x10044120 0x20>;
278 pinctrl_0: pinctrl@13400000 {
279 compatible = "samsung,exynos5420-pinctrl";
280 reg = <0x13400000 0x1000>;
281 interrupts = <0 45 0>;
283 wakeup-interrupt-controller {
284 compatible = "samsung,exynos4210-wakeup-eint";
285 interrupt-parent = <&gic>;
286 interrupts = <0 32 0>;
290 pinctrl_1: pinctrl@13410000 {
291 compatible = "samsung,exynos5420-pinctrl";
292 reg = <0x13410000 0x1000>;
293 interrupts = <0 78 0>;
296 pinctrl_2: pinctrl@14000000 {
297 compatible = "samsung,exynos5420-pinctrl";
298 reg = <0x14000000 0x1000>;
299 interrupts = <0 46 0>;
302 pinctrl_3: pinctrl@14010000 {
303 compatible = "samsung,exynos5420-pinctrl";
304 reg = <0x14010000 0x1000>;
305 interrupts = <0 50 0>;
308 pinctrl_4: pinctrl@03860000 {
309 compatible = "samsung,exynos5420-pinctrl";
310 reg = <0x03860000 0x1000>;
311 interrupts = <0 47 0>;
315 clocks = <&clock CLK_RTC>;
321 #address-cells = <1>;
323 compatible = "arm,amba-bus";
324 interrupt-parent = <&gic>;
327 adma: adma@03880000 {
328 compatible = "arm,pl330", "arm,primecell";
329 reg = <0x03880000 0x1000>;
330 interrupts = <0 110 0>;
331 clocks = <&clock_audss EXYNOS_ADMA>;
332 clock-names = "apb_pclk";
335 #dma-requests = <16>;
338 pdma0: pdma@121A0000 {
339 compatible = "arm,pl330", "arm,primecell";
340 reg = <0x121A0000 0x1000>;
341 interrupts = <0 34 0>;
342 clocks = <&clock CLK_PDMA0>;
343 clock-names = "apb_pclk";
346 #dma-requests = <32>;
349 pdma1: pdma@121B0000 {
350 compatible = "arm,pl330", "arm,primecell";
351 reg = <0x121B0000 0x1000>;
352 interrupts = <0 35 0>;
353 clocks = <&clock CLK_PDMA1>;
354 clock-names = "apb_pclk";
357 #dma-requests = <32>;
360 mdma0: mdma@10800000 {
361 compatible = "arm,pl330", "arm,primecell";
362 reg = <0x10800000 0x1000>;
363 interrupts = <0 33 0>;
364 clocks = <&clock CLK_MDMA0>;
365 clock-names = "apb_pclk";
371 mdma1: mdma@11C10000 {
372 compatible = "arm,pl330", "arm,primecell";
373 reg = <0x11C10000 0x1000>;
374 interrupts = <0 124 0>;
375 clocks = <&clock CLK_MDMA1>;
376 clock-names = "apb_pclk";
381 * MDMA1 can support both secure and non-secure
382 * AXI transactions. When this is enabled in the kernel
383 * for boards that run in secure mode, we are getting
384 * imprecise external aborts causing the kernel to oops.
391 compatible = "samsung,exynos5420-i2s";
392 reg = <0x03830000 0x100>;
396 dma-names = "tx", "rx", "tx-sec";
397 clocks = <&clock_audss EXYNOS_I2S_BUS>,
398 <&clock_audss EXYNOS_I2S_BUS>,
399 <&clock_audss EXYNOS_SCLK_I2S>;
400 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
401 samsung,idma-addr = <0x03000000>;
402 pinctrl-names = "default";
403 pinctrl-0 = <&i2s0_bus>;
408 compatible = "samsung,exynos5420-i2s";
409 reg = <0x12D60000 0x100>;
412 dma-names = "tx", "rx";
413 clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
414 clock-names = "iis", "i2s_opclk0";
415 pinctrl-names = "default";
416 pinctrl-0 = <&i2s1_bus>;
421 compatible = "samsung,exynos5420-i2s";
422 reg = <0x12D70000 0x100>;
425 dma-names = "tx", "rx";
426 clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
427 clock-names = "iis", "i2s_opclk0";
428 pinctrl-names = "default";
429 pinctrl-0 = <&i2s2_bus>;
433 spi_0: spi@12d20000 {
434 compatible = "samsung,exynos4210-spi";
435 reg = <0x12d20000 0x100>;
436 interrupts = <0 68 0>;
439 dma-names = "tx", "rx";
440 #address-cells = <1>;
442 pinctrl-names = "default";
443 pinctrl-0 = <&spi0_bus>;
444 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
445 clock-names = "spi", "spi_busclk0";
449 spi_1: spi@12d30000 {
450 compatible = "samsung,exynos4210-spi";
451 reg = <0x12d30000 0x100>;
452 interrupts = <0 69 0>;
455 dma-names = "tx", "rx";
456 #address-cells = <1>;
458 pinctrl-names = "default";
459 pinctrl-0 = <&spi1_bus>;
460 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
461 clock-names = "spi", "spi_busclk0";
465 spi_2: spi@12d40000 {
466 compatible = "samsung,exynos4210-spi";
467 reg = <0x12d40000 0x100>;
468 interrupts = <0 70 0>;
471 dma-names = "tx", "rx";
472 #address-cells = <1>;
474 pinctrl-names = "default";
475 pinctrl-0 = <&spi2_bus>;
476 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
477 clock-names = "spi", "spi_busclk0";
481 uart_0: serial@12C00000 {
482 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
483 clock-names = "uart", "clk_uart_baud0";
486 uart_1: serial@12C10000 {
487 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
488 clock-names = "uart", "clk_uart_baud0";
491 uart_2: serial@12C20000 {
492 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
493 clock-names = "uart", "clk_uart_baud0";
496 uart_3: serial@12C30000 {
497 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
498 clock-names = "uart", "clk_uart_baud0";
502 compatible = "samsung,exynos4210-pwm";
503 reg = <0x12dd0000 0x100>;
504 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
506 clocks = <&clock CLK_PWM>;
507 clock-names = "timers";
510 dp_phy: video-phy@10040728 {
511 compatible = "samsung,exynos5250-dp-video-phy";
512 reg = <0x10040728 4>;
516 dp: dp-controller@145B0000 {
517 clocks = <&clock CLK_DP1>;
523 fimd: fimd@14400000 {
524 samsung,power-domain = <&disp_pd>;
525 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
526 clock-names = "sclk_fimd", "fimd";
530 compatible = "samsung,exynos-adc-v2";
531 reg = <0x12D10000 0x100>, <0x10040720 0x4>;
532 interrupts = <0 106 0>;
533 clocks = <&clock CLK_TSADC>;
535 #io-channel-cells = <1>;
540 i2c_0: i2c@12C60000 {
541 compatible = "samsung,s3c2440-i2c";
542 reg = <0x12C60000 0x100>;
543 interrupts = <0 56 0>;
544 #address-cells = <1>;
546 clocks = <&clock CLK_I2C0>;
548 pinctrl-names = "default";
549 pinctrl-0 = <&i2c0_bus>;
553 i2c_1: i2c@12C70000 {
554 compatible = "samsung,s3c2440-i2c";
555 reg = <0x12C70000 0x100>;
556 interrupts = <0 57 0>;
557 #address-cells = <1>;
559 clocks = <&clock CLK_I2C1>;
561 pinctrl-names = "default";
562 pinctrl-0 = <&i2c1_bus>;
566 i2c_2: i2c@12C80000 {
567 compatible = "samsung,s3c2440-i2c";
568 reg = <0x12C80000 0x100>;
569 interrupts = <0 58 0>;
570 #address-cells = <1>;
572 clocks = <&clock CLK_I2C2>;
574 pinctrl-names = "default";
575 pinctrl-0 = <&i2c2_bus>;
579 i2c_3: i2c@12C90000 {
580 compatible = "samsung,s3c2440-i2c";
581 reg = <0x12C90000 0x100>;
582 interrupts = <0 59 0>;
583 #address-cells = <1>;
585 clocks = <&clock CLK_I2C3>;
587 pinctrl-names = "default";
588 pinctrl-0 = <&i2c3_bus>;
592 hsi2c_4: i2c@12CA0000 {
593 compatible = "samsung,exynos5-hsi2c";
594 reg = <0x12CA0000 0x1000>;
595 interrupts = <0 60 0>;
596 #address-cells = <1>;
598 pinctrl-names = "default";
599 pinctrl-0 = <&i2c4_hs_bus>;
600 clocks = <&clock CLK_USI0>;
601 clock-names = "hsi2c";
605 hsi2c_5: i2c@12CB0000 {
606 compatible = "samsung,exynos5-hsi2c";
607 reg = <0x12CB0000 0x1000>;
608 interrupts = <0 61 0>;
609 #address-cells = <1>;
611 pinctrl-names = "default";
612 pinctrl-0 = <&i2c5_hs_bus>;
613 clocks = <&clock CLK_USI1>;
614 clock-names = "hsi2c";
618 hsi2c_6: i2c@12CC0000 {
619 compatible = "samsung,exynos5-hsi2c";
620 reg = <0x12CC0000 0x1000>;
621 interrupts = <0 62 0>;
622 #address-cells = <1>;
624 pinctrl-names = "default";
625 pinctrl-0 = <&i2c6_hs_bus>;
626 clocks = <&clock CLK_USI2>;
627 clock-names = "hsi2c";
631 hsi2c_7: i2c@12CD0000 {
632 compatible = "samsung,exynos5-hsi2c";
633 reg = <0x12CD0000 0x1000>;
634 interrupts = <0 63 0>;
635 #address-cells = <1>;
637 pinctrl-names = "default";
638 pinctrl-0 = <&i2c7_hs_bus>;
639 clocks = <&clock CLK_USI3>;
640 clock-names = "hsi2c";
644 hsi2c_8: i2c@12E00000 {
645 compatible = "samsung,exynos5-hsi2c";
646 reg = <0x12E00000 0x1000>;
647 interrupts = <0 87 0>;
648 #address-cells = <1>;
650 pinctrl-names = "default";
651 pinctrl-0 = <&i2c8_hs_bus>;
652 clocks = <&clock CLK_USI4>;
653 clock-names = "hsi2c";
657 hsi2c_9: i2c@12E10000 {
658 compatible = "samsung,exynos5-hsi2c";
659 reg = <0x12E10000 0x1000>;
660 interrupts = <0 88 0>;
661 #address-cells = <1>;
663 pinctrl-names = "default";
664 pinctrl-0 = <&i2c9_hs_bus>;
665 clocks = <&clock CLK_USI5>;
666 clock-names = "hsi2c";
670 hsi2c_10: i2c@12E20000 {
671 compatible = "samsung,exynos5-hsi2c";
672 reg = <0x12E20000 0x1000>;
673 interrupts = <0 203 0>;
674 #address-cells = <1>;
676 pinctrl-names = "default";
677 pinctrl-0 = <&i2c10_hs_bus>;
678 clocks = <&clock CLK_USI6>;
679 clock-names = "hsi2c";
683 hdmi: hdmi@14530000 {
684 compatible = "samsung,exynos5420-hdmi";
685 reg = <0x14530000 0x70000>;
686 interrupts = <0 95 0>;
687 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
688 <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
689 <&clock CLK_MOUT_HDMI>;
690 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
691 "sclk_hdmiphy", "mout_hdmi";
693 samsung,syscon-phandle = <&pmu_system_controller>;
697 hdmiphy: hdmiphy@145D0000 {
698 reg = <0x145D0000 0x20>;
701 mixer: mixer@14450000 {
702 compatible = "samsung,exynos5420-mixer";
703 reg = <0x14450000 0x10000>;
704 interrupts = <0 94 0>;
705 clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>;
706 clock-names = "mixer", "sclk_hdmi";
709 gsc_0: video-scaler@13e00000 {
710 compatible = "samsung,exynos5-gsc";
711 reg = <0x13e00000 0x1000>;
712 interrupts = <0 85 0>;
713 clocks = <&clock CLK_GSCL0>;
714 clock-names = "gscl";
715 samsung,power-domain = <&gsc_pd>;
718 gsc_1: video-scaler@13e10000 {
719 compatible = "samsung,exynos5-gsc";
720 reg = <0x13e10000 0x1000>;
721 interrupts = <0 86 0>;
722 clocks = <&clock CLK_GSCL1>;
723 clock-names = "gscl";
724 samsung,power-domain = <&gsc_pd>;
727 pmu_system_controller: system-controller@10040000 {
728 compatible = "samsung,exynos5420-pmu", "syscon";
729 reg = <0x10040000 0x5000>;
732 sysreg_system_controller: syscon@10050000 {
733 compatible = "samsung,exynos5-sysreg", "syscon";
734 reg = <0x10050000 0x5000>;
737 tmu_cpu0: tmu@10060000 {
738 compatible = "samsung,exynos5420-tmu";
739 reg = <0x10060000 0x100>;
740 interrupts = <0 65 0>;
741 clocks = <&clock CLK_TMU>;
742 clock-names = "tmu_apbif";
745 tmu_cpu1: tmu@10064000 {
746 compatible = "samsung,exynos5420-tmu";
747 reg = <0x10064000 0x100>;
748 interrupts = <0 183 0>;
749 clocks = <&clock CLK_TMU>;
750 clock-names = "tmu_apbif";
753 tmu_cpu2: tmu@10068000 {
754 compatible = "samsung,exynos5420-tmu-ext-triminfo";
755 reg = <0x10068000 0x100>, <0x1006c000 0x4>;
756 interrupts = <0 184 0>;
757 clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
758 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
761 tmu_cpu3: tmu@1006c000 {
762 compatible = "samsung,exynos5420-tmu-ext-triminfo";
763 reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
764 interrupts = <0 185 0>;
765 clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
766 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
769 tmu_gpu: tmu@100a0000 {
770 compatible = "samsung,exynos5420-tmu-ext-triminfo";
771 reg = <0x100a0000 0x100>, <0x10068000 0x4>;
772 interrupts = <0 215 0>;
773 clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
774 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
777 watchdog: watchdog@101D0000 {
778 compatible = "samsung,exynos5420-wdt";
779 reg = <0x101D0000 0x100>;
780 interrupts = <0 42 0>;
781 clocks = <&clock CLK_WDT>;
782 clock-names = "watchdog";
783 samsung,syscon-phandle = <&pmu_system_controller>;
787 compatible = "samsung,exynos4210-secss";
788 reg = <0x10830000 0x10000>;
789 interrupts = <0 112 0>;
790 clocks = <&clock CLK_SSS>;
791 clock-names = "secss";
794 usbdrd3_0: usb@12000000 {
795 compatible = "samsung,exynos5250-dwusb3";
796 clocks = <&clock CLK_USBD300>;
797 clock-names = "usbdrd30";
798 #address-cells = <1>;
803 compatible = "snps,dwc3";
804 reg = <0x12000000 0x10000>;
805 interrupts = <0 72 0>;
806 phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
807 phy-names = "usb2-phy", "usb3-phy";
811 usbdrd_phy0: phy@12100000 {
812 compatible = "samsung,exynos5420-usbdrd-phy";
813 reg = <0x12100000 0x100>;
814 clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
815 clock-names = "phy", "ref";
816 samsung,pmu-syscon = <&pmu_system_controller>;
820 usbdrd3_1: usb@12400000 {
821 compatible = "samsung,exynos5250-dwusb3";
822 clocks = <&clock CLK_USBD301>;
823 clock-names = "usbdrd30";
824 #address-cells = <1>;
829 compatible = "snps,dwc3";
830 reg = <0x12400000 0x10000>;
831 interrupts = <0 73 0>;
832 phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>;
833 phy-names = "usb2-phy", "usb3-phy";
837 usbdrd_phy1: phy@12500000 {
838 compatible = "samsung,exynos5420-usbdrd-phy";
839 reg = <0x12500000 0x100>;
840 clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
841 clock-names = "phy", "ref";
842 samsung,pmu-syscon = <&pmu_system_controller>;
846 usbhost2: usb@12110000 {
847 compatible = "samsung,exynos4210-ehci";
848 reg = <0x12110000 0x100>;
849 interrupts = <0 71 0>;
851 clocks = <&clock CLK_USBH20>;
852 clock-names = "usbhost";
853 #address-cells = <1>;
857 phys = <&usb2_phy 1>;
861 usbhost1: usb@12120000 {
862 compatible = "samsung,exynos4210-ohci";
863 reg = <0x12120000 0x100>;
864 interrupts = <0 71 0>;
866 clocks = <&clock CLK_USBH20>;
867 clock-names = "usbhost";
868 #address-cells = <1>;
872 phys = <&usb2_phy 1>;
876 usb2_phy: phy@12130000 {
877 compatible = "samsung,exynos5250-usb2-phy";
878 reg = <0x12130000 0x100>;
879 clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
880 clock-names = "phy", "ref";
882 samsung,sysreg-phandle = <&sysreg_system_controller>;
883 samsung,pmureg-phandle = <&pmu_system_controller>;