2 * SAMSUNG EXYNOS5420 SoC device tree source
4 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
8 * EXYNOS5420 based board files can include this file and provide
9 * values for board specfic bindings.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <dt-bindings/clock/exynos5420.h>
17 #include "exynos5.dtsi"
18 #include "exynos5420-pinctrl.dtsi"
20 #include <dt-bindings/clock/exynos-audss-clk.h>
23 compatible = "samsung,exynos5420", "samsung,exynos5";
29 pinctrl0 = &pinctrl_0;
30 pinctrl1 = &pinctrl_1;
31 pinctrl2 = &pinctrl_2;
32 pinctrl3 = &pinctrl_3;
33 pinctrl4 = &pinctrl_4;
50 usbdrdphy0 = &usbdrd_phy0;
51 usbdrdphy1 = &usbdrd_phy1;
60 compatible = "arm,cortex-a15";
62 clock-frequency = <1800000000>;
63 cci-control-port = <&cci_control1>;
68 compatible = "arm,cortex-a15";
70 clock-frequency = <1800000000>;
71 cci-control-port = <&cci_control1>;
76 compatible = "arm,cortex-a15";
78 clock-frequency = <1800000000>;
79 cci-control-port = <&cci_control1>;
84 compatible = "arm,cortex-a15";
86 clock-frequency = <1800000000>;
87 cci-control-port = <&cci_control1>;
92 compatible = "arm,cortex-a7";
94 clock-frequency = <1000000000>;
95 cci-control-port = <&cci_control0>;
100 compatible = "arm,cortex-a7";
102 clock-frequency = <1000000000>;
103 cci-control-port = <&cci_control0>;
108 compatible = "arm,cortex-a7";
110 clock-frequency = <1000000000>;
111 cci-control-port = <&cci_control0>;
116 compatible = "arm,cortex-a7";
118 clock-frequency = <1000000000>;
119 cci-control-port = <&cci_control0>;
124 compatible = "arm,cci-400";
125 #address-cells = <1>;
127 reg = <0x10d20000 0x1000>;
128 ranges = <0x0 0x10d20000 0x6000>;
130 cci_control0: slave-if@4000 {
131 compatible = "arm,cci-400-ctrl-if";
132 interface-type = "ace";
133 reg = <0x4000 0x1000>;
135 cci_control1: slave-if@5000 {
136 compatible = "arm,cci-400-ctrl-if";
137 interface-type = "ace";
138 reg = <0x5000 0x1000>;
143 compatible = "mmio-sram";
144 reg = <0x02020000 0x54000>;
145 #address-cells = <1>;
147 ranges = <0 0x02020000 0x54000>;
150 compatible = "samsung,exynos4210-sysram";
155 compatible = "samsung,exynos4210-sysram-ns";
156 reg = <0x53000 0x1000>;
160 clock: clock-controller@10010000 {
161 compatible = "samsung,exynos5420-clock";
162 reg = <0x10010000 0x30000>;
166 clock_audss: audss-clock-controller@3810000 {
167 compatible = "samsung,exynos5420-audss-clock";
168 reg = <0x03810000 0x0C>;
170 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
171 <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
172 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
175 mfc: codec@11000000 {
176 compatible = "samsung,mfc-v7";
177 reg = <0x11000000 0x10000>;
178 interrupts = <0 96 0>;
179 clocks = <&clock CLK_MFC>;
181 samsung,power-domain = <&mfc_pd>;
184 mmc_0: mmc@12200000 {
185 compatible = "samsung,exynos5420-dw-mshc-smu";
186 interrupts = <0 75 0>;
187 #address-cells = <1>;
189 reg = <0x12200000 0x2000>;
190 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
191 clock-names = "biu", "ciu";
196 mmc_1: mmc@12210000 {
197 compatible = "samsung,exynos5420-dw-mshc-smu";
198 interrupts = <0 76 0>;
199 #address-cells = <1>;
201 reg = <0x12210000 0x2000>;
202 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
203 clock-names = "biu", "ciu";
208 mmc_2: mmc@12220000 {
209 compatible = "samsung,exynos5420-dw-mshc";
210 interrupts = <0 77 0>;
211 #address-cells = <1>;
213 reg = <0x12220000 0x1000>;
214 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
215 clock-names = "biu", "ciu";
221 compatible = "samsung,exynos4210-mct";
222 reg = <0x101C0000 0x800>;
223 interrupt-controller;
224 #interrups-cells = <1>;
225 interrupt-parent = <&mct_map>;
226 interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
227 <8>, <9>, <10>, <11>;
228 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
229 clock-names = "fin_pll", "mct";
232 #interrupt-cells = <1>;
233 #address-cells = <0>;
235 interrupt-map = <0 &combiner 23 3>,
250 gsc_pd: power-domain@10044000 {
251 compatible = "samsung,exynos4210-pd";
252 reg = <0x10044000 0x20>;
255 isp_pd: power-domain@10044020 {
256 compatible = "samsung,exynos4210-pd";
257 reg = <0x10044020 0x20>;
260 mfc_pd: power-domain@10044060 {
261 compatible = "samsung,exynos4210-pd";
262 reg = <0x10044060 0x20>;
263 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK333>,
264 <&clock CLK_MOUT_USER_ACLK333>;
265 clock-names = "oscclk", "pclk0", "clk0";
268 msc_pd: power-domain@10044120 {
269 compatible = "samsung,exynos4210-pd";
270 reg = <0x10044120 0x20>;
273 pinctrl_0: pinctrl@13400000 {
274 compatible = "samsung,exynos5420-pinctrl";
275 reg = <0x13400000 0x1000>;
276 interrupts = <0 45 0>;
278 wakeup-interrupt-controller {
279 compatible = "samsung,exynos4210-wakeup-eint";
280 interrupt-parent = <&gic>;
281 interrupts = <0 32 0>;
285 pinctrl_1: pinctrl@13410000 {
286 compatible = "samsung,exynos5420-pinctrl";
287 reg = <0x13410000 0x1000>;
288 interrupts = <0 78 0>;
291 pinctrl_2: pinctrl@14000000 {
292 compatible = "samsung,exynos5420-pinctrl";
293 reg = <0x14000000 0x1000>;
294 interrupts = <0 46 0>;
297 pinctrl_3: pinctrl@14010000 {
298 compatible = "samsung,exynos5420-pinctrl";
299 reg = <0x14010000 0x1000>;
300 interrupts = <0 50 0>;
303 pinctrl_4: pinctrl@03860000 {
304 compatible = "samsung,exynos5420-pinctrl";
305 reg = <0x03860000 0x1000>;
306 interrupts = <0 47 0>;
310 clocks = <&clock CLK_RTC>;
316 #address-cells = <1>;
318 compatible = "arm,amba-bus";
319 interrupt-parent = <&gic>;
322 adma: adma@03880000 {
323 compatible = "arm,pl330", "arm,primecell";
324 reg = <0x03880000 0x1000>;
325 interrupts = <0 110 0>;
326 clocks = <&clock_audss EXYNOS_ADMA>;
327 clock-names = "apb_pclk";
330 #dma-requests = <16>;
333 pdma0: pdma@121A0000 {
334 compatible = "arm,pl330", "arm,primecell";
335 reg = <0x121A0000 0x1000>;
336 interrupts = <0 34 0>;
337 clocks = <&clock CLK_PDMA0>;
338 clock-names = "apb_pclk";
341 #dma-requests = <32>;
344 pdma1: pdma@121B0000 {
345 compatible = "arm,pl330", "arm,primecell";
346 reg = <0x121B0000 0x1000>;
347 interrupts = <0 35 0>;
348 clocks = <&clock CLK_PDMA1>;
349 clock-names = "apb_pclk";
352 #dma-requests = <32>;
355 mdma0: mdma@10800000 {
356 compatible = "arm,pl330", "arm,primecell";
357 reg = <0x10800000 0x1000>;
358 interrupts = <0 33 0>;
359 clocks = <&clock CLK_MDMA0>;
360 clock-names = "apb_pclk";
366 mdma1: mdma@11C10000 {
367 compatible = "arm,pl330", "arm,primecell";
368 reg = <0x11C10000 0x1000>;
369 interrupts = <0 124 0>;
370 clocks = <&clock CLK_MDMA1>;
371 clock-names = "apb_pclk";
376 * MDMA1 can support both secure and non-secure
377 * AXI transactions. When this is enabled in the kernel
378 * for boards that run in secure mode, we are getting
379 * imprecise external aborts causing the kernel to oops.
386 compatible = "samsung,exynos5420-i2s";
387 reg = <0x03830000 0x100>;
391 dma-names = "tx", "rx", "tx-sec";
392 clocks = <&clock_audss EXYNOS_I2S_BUS>,
393 <&clock_audss EXYNOS_I2S_BUS>,
394 <&clock_audss EXYNOS_SCLK_I2S>;
395 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
396 samsung,idma-addr = <0x03000000>;
397 pinctrl-names = "default";
398 pinctrl-0 = <&i2s0_bus>;
403 compatible = "samsung,exynos5420-i2s";
404 reg = <0x12D60000 0x100>;
407 dma-names = "tx", "rx";
408 clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
409 clock-names = "iis", "i2s_opclk0";
410 pinctrl-names = "default";
411 pinctrl-0 = <&i2s1_bus>;
416 compatible = "samsung,exynos5420-i2s";
417 reg = <0x12D70000 0x100>;
420 dma-names = "tx", "rx";
421 clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
422 clock-names = "iis", "i2s_opclk0";
423 pinctrl-names = "default";
424 pinctrl-0 = <&i2s2_bus>;
428 spi_0: spi@12d20000 {
429 compatible = "samsung,exynos4210-spi";
430 reg = <0x12d20000 0x100>;
431 interrupts = <0 68 0>;
434 dma-names = "tx", "rx";
435 #address-cells = <1>;
437 pinctrl-names = "default";
438 pinctrl-0 = <&spi0_bus>;
439 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
440 clock-names = "spi", "spi_busclk0";
444 spi_1: spi@12d30000 {
445 compatible = "samsung,exynos4210-spi";
446 reg = <0x12d30000 0x100>;
447 interrupts = <0 69 0>;
450 dma-names = "tx", "rx";
451 #address-cells = <1>;
453 pinctrl-names = "default";
454 pinctrl-0 = <&spi1_bus>;
455 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
456 clock-names = "spi", "spi_busclk0";
460 spi_2: spi@12d40000 {
461 compatible = "samsung,exynos4210-spi";
462 reg = <0x12d40000 0x100>;
463 interrupts = <0 70 0>;
466 dma-names = "tx", "rx";
467 #address-cells = <1>;
469 pinctrl-names = "default";
470 pinctrl-0 = <&spi2_bus>;
471 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
472 clock-names = "spi", "spi_busclk0";
476 uart_0: serial@12C00000 {
477 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
478 clock-names = "uart", "clk_uart_baud0";
481 uart_1: serial@12C10000 {
482 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
483 clock-names = "uart", "clk_uart_baud0";
486 uart_2: serial@12C20000 {
487 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
488 clock-names = "uart", "clk_uart_baud0";
491 uart_3: serial@12C30000 {
492 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
493 clock-names = "uart", "clk_uart_baud0";
497 compatible = "samsung,exynos4210-pwm";
498 reg = <0x12dd0000 0x100>;
499 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
501 clocks = <&clock CLK_PWM>;
502 clock-names = "timers";
505 dp_phy: video-phy@10040728 {
506 compatible = "samsung,exynos5250-dp-video-phy";
507 reg = <0x10040728 4>;
511 dp: dp-controller@145B0000 {
512 clocks = <&clock CLK_DP1>;
518 mipi_phy: video-phy@10040714 {
519 compatible = "samsung,s5pv210-mipi-video-phy";
520 reg = <0x10040714 12>;
525 compatible = "samsung,exynos5410-mipi-dsi";
526 reg = <0x14500000 0x10000>;
527 interrupts = <0 82 0>;
528 phys = <&mipi_phy 1>;
530 clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>;
531 clock-names = "bus_clk", "pll_clk";
532 #address-cells = <1>;
537 fimd: fimd@14400000 {
538 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
539 clock-names = "sclk_fimd", "fimd";
543 compatible = "samsung,exynos-adc-v2";
544 reg = <0x12D10000 0x100>, <0x10040720 0x4>;
545 interrupts = <0 106 0>;
546 clocks = <&clock CLK_TSADC>;
548 #io-channel-cells = <1>;
553 i2c_0: i2c@12C60000 {
554 compatible = "samsung,s3c2440-i2c";
555 reg = <0x12C60000 0x100>;
556 interrupts = <0 56 0>;
557 #address-cells = <1>;
559 clocks = <&clock CLK_I2C0>;
561 pinctrl-names = "default";
562 pinctrl-0 = <&i2c0_bus>;
566 i2c_1: i2c@12C70000 {
567 compatible = "samsung,s3c2440-i2c";
568 reg = <0x12C70000 0x100>;
569 interrupts = <0 57 0>;
570 #address-cells = <1>;
572 clocks = <&clock CLK_I2C1>;
574 pinctrl-names = "default";
575 pinctrl-0 = <&i2c1_bus>;
579 i2c_2: i2c@12C80000 {
580 compatible = "samsung,s3c2440-i2c";
581 reg = <0x12C80000 0x100>;
582 interrupts = <0 58 0>;
583 #address-cells = <1>;
585 clocks = <&clock CLK_I2C2>;
587 pinctrl-names = "default";
588 pinctrl-0 = <&i2c2_bus>;
592 i2c_3: i2c@12C90000 {
593 compatible = "samsung,s3c2440-i2c";
594 reg = <0x12C90000 0x100>;
595 interrupts = <0 59 0>;
596 #address-cells = <1>;
598 clocks = <&clock CLK_I2C3>;
600 pinctrl-names = "default";
601 pinctrl-0 = <&i2c3_bus>;
605 hsi2c_4: i2c@12CA0000 {
606 compatible = "samsung,exynos5-hsi2c";
607 reg = <0x12CA0000 0x1000>;
608 interrupts = <0 60 0>;
609 #address-cells = <1>;
611 pinctrl-names = "default";
612 pinctrl-0 = <&i2c4_hs_bus>;
613 clocks = <&clock CLK_USI0>;
614 clock-names = "hsi2c";
618 hsi2c_5: i2c@12CB0000 {
619 compatible = "samsung,exynos5-hsi2c";
620 reg = <0x12CB0000 0x1000>;
621 interrupts = <0 61 0>;
622 #address-cells = <1>;
624 pinctrl-names = "default";
625 pinctrl-0 = <&i2c5_hs_bus>;
626 clocks = <&clock CLK_USI1>;
627 clock-names = "hsi2c";
631 hsi2c_6: i2c@12CC0000 {
632 compatible = "samsung,exynos5-hsi2c";
633 reg = <0x12CC0000 0x1000>;
634 interrupts = <0 62 0>;
635 #address-cells = <1>;
637 pinctrl-names = "default";
638 pinctrl-0 = <&i2c6_hs_bus>;
639 clocks = <&clock CLK_USI2>;
640 clock-names = "hsi2c";
644 hsi2c_7: i2c@12CD0000 {
645 compatible = "samsung,exynos5-hsi2c";
646 reg = <0x12CD0000 0x1000>;
647 interrupts = <0 63 0>;
648 #address-cells = <1>;
650 pinctrl-names = "default";
651 pinctrl-0 = <&i2c7_hs_bus>;
652 clocks = <&clock CLK_USI3>;
653 clock-names = "hsi2c";
657 hsi2c_8: i2c@12E00000 {
658 compatible = "samsung,exynos5-hsi2c";
659 reg = <0x12E00000 0x1000>;
660 interrupts = <0 87 0>;
661 #address-cells = <1>;
663 pinctrl-names = "default";
664 pinctrl-0 = <&i2c8_hs_bus>;
665 clocks = <&clock CLK_USI4>;
666 clock-names = "hsi2c";
670 hsi2c_9: i2c@12E10000 {
671 compatible = "samsung,exynos5-hsi2c";
672 reg = <0x12E10000 0x1000>;
673 interrupts = <0 88 0>;
674 #address-cells = <1>;
676 pinctrl-names = "default";
677 pinctrl-0 = <&i2c9_hs_bus>;
678 clocks = <&clock CLK_USI5>;
679 clock-names = "hsi2c";
683 hsi2c_10: i2c@12E20000 {
684 compatible = "samsung,exynos5-hsi2c";
685 reg = <0x12E20000 0x1000>;
686 interrupts = <0 203 0>;
687 #address-cells = <1>;
689 pinctrl-names = "default";
690 pinctrl-0 = <&i2c10_hs_bus>;
691 clocks = <&clock CLK_USI6>;
692 clock-names = "hsi2c";
696 hdmi: hdmi@14530000 {
697 compatible = "samsung,exynos5420-hdmi";
698 reg = <0x14530000 0x70000>;
699 interrupts = <0 95 0>;
700 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
701 <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
702 <&clock CLK_MOUT_HDMI>;
703 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
704 "sclk_hdmiphy", "mout_hdmi";
706 samsung,syscon-phandle = <&pmu_system_controller>;
710 hdmiphy: hdmiphy@145D0000 {
711 reg = <0x145D0000 0x20>;
714 mixer: mixer@14450000 {
715 compatible = "samsung,exynos5420-mixer";
716 reg = <0x14450000 0x10000>;
717 interrupts = <0 94 0>;
718 clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>;
719 clock-names = "mixer", "sclk_hdmi";
722 gsc_0: video-scaler@13e00000 {
723 compatible = "samsung,exynos5-gsc";
724 reg = <0x13e00000 0x1000>;
725 interrupts = <0 85 0>;
726 clocks = <&clock CLK_GSCL0>;
727 clock-names = "gscl";
728 samsung,power-domain = <&gsc_pd>;
731 gsc_1: video-scaler@13e10000 {
732 compatible = "samsung,exynos5-gsc";
733 reg = <0x13e10000 0x1000>;
734 interrupts = <0 86 0>;
735 clocks = <&clock CLK_GSCL1>;
736 clock-names = "gscl";
737 samsung,power-domain = <&gsc_pd>;
740 pmu_system_controller: system-controller@10040000 {
741 compatible = "samsung,exynos5420-pmu", "syscon";
742 reg = <0x10040000 0x5000>;
743 clock-names = "clkout16";
744 clocks = <&clock CLK_FIN_PLL>;
748 sysreg_system_controller: syscon@10050000 {
749 compatible = "samsung,exynos5-sysreg", "syscon";
750 reg = <0x10050000 0x5000>;
753 tmu_cpu0: tmu@10060000 {
754 compatible = "samsung,exynos5420-tmu";
755 reg = <0x10060000 0x100>;
756 interrupts = <0 65 0>;
757 clocks = <&clock CLK_TMU>;
758 clock-names = "tmu_apbif";
761 tmu_cpu1: tmu@10064000 {
762 compatible = "samsung,exynos5420-tmu";
763 reg = <0x10064000 0x100>;
764 interrupts = <0 183 0>;
765 clocks = <&clock CLK_TMU>;
766 clock-names = "tmu_apbif";
769 tmu_cpu2: tmu@10068000 {
770 compatible = "samsung,exynos5420-tmu-ext-triminfo";
771 reg = <0x10068000 0x100>, <0x1006c000 0x4>;
772 interrupts = <0 184 0>;
773 clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
774 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
777 tmu_cpu3: tmu@1006c000 {
778 compatible = "samsung,exynos5420-tmu-ext-triminfo";
779 reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
780 interrupts = <0 185 0>;
781 clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
782 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
785 tmu_gpu: tmu@100a0000 {
786 compatible = "samsung,exynos5420-tmu-ext-triminfo";
787 reg = <0x100a0000 0x100>, <0x10068000 0x4>;
788 interrupts = <0 215 0>;
789 clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
790 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
793 watchdog: watchdog@101D0000 {
794 compatible = "samsung,exynos5420-wdt";
795 reg = <0x101D0000 0x100>;
796 interrupts = <0 42 0>;
797 clocks = <&clock CLK_WDT>;
798 clock-names = "watchdog";
799 samsung,syscon-phandle = <&pmu_system_controller>;
803 compatible = "samsung,exynos4210-secss";
804 reg = <0x10830000 0x10000>;
805 interrupts = <0 112 0>;
806 clocks = <&clock CLK_SSS>;
807 clock-names = "secss";
810 usbdrd3_0: usb@12000000 {
811 compatible = "samsung,exynos5250-dwusb3";
812 clocks = <&clock CLK_USBD300>;
813 clock-names = "usbdrd30";
814 #address-cells = <1>;
818 usbdrd_dwc3_0: dwc3 {
819 compatible = "snps,dwc3";
820 reg = <0x12000000 0x10000>;
821 interrupts = <0 72 0>;
822 phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
823 phy-names = "usb2-phy", "usb3-phy";
827 usbdrd_phy0: phy@12100000 {
828 compatible = "samsung,exynos5420-usbdrd-phy";
829 reg = <0x12100000 0x100>;
830 clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
831 clock-names = "phy", "ref";
832 samsung,pmu-syscon = <&pmu_system_controller>;
836 usbdrd3_1: usb@12400000 {
837 compatible = "samsung,exynos5250-dwusb3";
838 clocks = <&clock CLK_USBD301>;
839 clock-names = "usbdrd30";
840 #address-cells = <1>;
844 usbdrd_dwc3_1: dwc3 {
845 compatible = "snps,dwc3";
846 reg = <0x12400000 0x10000>;
847 interrupts = <0 73 0>;
848 phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>;
849 phy-names = "usb2-phy", "usb3-phy";
853 usbdrd_phy1: phy@12500000 {
854 compatible = "samsung,exynos5420-usbdrd-phy";
855 reg = <0x12500000 0x100>;
856 clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
857 clock-names = "phy", "ref";
858 samsung,pmu-syscon = <&pmu_system_controller>;
862 usbhost2: usb@12110000 {
863 compatible = "samsung,exynos4210-ehci";
864 reg = <0x12110000 0x100>;
865 interrupts = <0 71 0>;
867 clocks = <&clock CLK_USBH20>;
868 clock-names = "usbhost";
869 #address-cells = <1>;
873 phys = <&usb2_phy 1>;
877 usbhost1: usb@12120000 {
878 compatible = "samsung,exynos4210-ohci";
879 reg = <0x12120000 0x100>;
880 interrupts = <0 71 0>;
882 clocks = <&clock CLK_USBH20>;
883 clock-names = "usbhost";
884 #address-cells = <1>;
888 phys = <&usb2_phy 1>;
892 usb2_phy: phy@12130000 {
893 compatible = "samsung,exynos5250-usb2-phy";
894 reg = <0x12130000 0x100>;
895 clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
896 clock-names = "phy", "ref";
898 samsung,sysreg-phandle = <&sysreg_system_controller>;
899 samsung,pmureg-phandle = <&pmu_system_controller>;