2 * SAMSUNG EXYNOS5420 SoC device tree source
4 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
8 * EXYNOS5420 based board files can include this file and provide
9 * values for board specfic bindings.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include "exynos5.dtsi"
17 #include "exynos5420-pinctrl.dtsi"
19 #include <dt-bindings/clk/exynos-audss-clk.h>
22 compatible = "samsung,exynos5420";
25 pinctrl0 = &pinctrl_0;
26 pinctrl1 = &pinctrl_1;
27 pinctrl2 = &pinctrl_2;
28 pinctrl3 = &pinctrl_3;
29 pinctrl4 = &pinctrl_4;
38 compatible = "arm,cortex-a15";
40 clock-frequency = <1800000000>;
45 compatible = "arm,cortex-a15";
47 clock-frequency = <1800000000>;
52 compatible = "arm,cortex-a15";
54 clock-frequency = <1800000000>;
59 compatible = "arm,cortex-a15";
61 clock-frequency = <1800000000>;
65 clock: clock-controller@10010000 {
66 compatible = "samsung,exynos5420-clock";
67 reg = <0x10010000 0x30000>;
71 clock_audss: audss-clock-controller@3810000 {
72 compatible = "samsung,exynos5420-audss-clock";
73 reg = <0x03810000 0x0C>;
75 clocks = <&clock 148>;
76 clock-names = "sclk_audio";
80 compatible = "samsung,mfc-v7";
81 reg = <0x11000000 0x10000>;
82 interrupts = <0 96 0>;
83 clocks = <&clock 401>;
88 compatible = "samsung,exynos4210-mct";
89 reg = <0x101C0000 0x800>;
91 #interrups-cells = <1>;
92 interrupt-parent = <&mct_map>;
93 interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>;
94 clocks = <&clock 1>, <&clock 315>;
95 clock-names = "fin_pll", "mct";
98 #interrupt-cells = <1>;
101 interrupt-map = <0 &combiner 23 3>,
112 gsc_pd: power-domain@10044000 {
113 compatible = "samsung,exynos4210-pd";
114 reg = <0x10044000 0x20>;
117 isp_pd: power-domain@10044020 {
118 compatible = "samsung,exynos4210-pd";
119 reg = <0x10044020 0x20>;
122 mfc_pd: power-domain@10044060 {
123 compatible = "samsung,exynos4210-pd";
124 reg = <0x10044060 0x20>;
127 disp_pd: power-domain@100440C0 {
128 compatible = "samsung,exynos4210-pd";
129 reg = <0x100440C0 0x20>;
132 mau_pd: power-domain@100440E0 {
133 compatible = "samsung,exynos4210-pd";
134 reg = <0x100440E0 0x20>;
137 g2d_pd: power-domain@10044100 {
138 compatible = "samsung,exynos4210-pd";
139 reg = <0x10044100 0x20>;
142 msc_pd: power-domain@10044120 {
143 compatible = "samsung,exynos4210-pd";
144 reg = <0x10044120 0x20>;
147 pinctrl_0: pinctrl@13400000 {
148 compatible = "samsung,exynos5420-pinctrl";
149 reg = <0x13400000 0x1000>;
150 interrupts = <0 45 0>;
152 wakeup-interrupt-controller {
153 compatible = "samsung,exynos4210-wakeup-eint";
154 interrupt-parent = <&gic>;
155 interrupts = <0 32 0>;
159 pinctrl_1: pinctrl@13410000 {
160 compatible = "samsung,exynos5420-pinctrl";
161 reg = <0x13410000 0x1000>;
162 interrupts = <0 78 0>;
165 pinctrl_2: pinctrl@14000000 {
166 compatible = "samsung,exynos5420-pinctrl";
167 reg = <0x14000000 0x1000>;
168 interrupts = <0 46 0>;
171 pinctrl_3: pinctrl@14010000 {
172 compatible = "samsung,exynos5420-pinctrl";
173 reg = <0x14010000 0x1000>;
174 interrupts = <0 50 0>;
177 pinctrl_4: pinctrl@03860000 {
178 compatible = "samsung,exynos5420-pinctrl";
179 reg = <0x03860000 0x1000>;
180 interrupts = <0 47 0>;
184 clocks = <&clock 257>, <&clock 128>;
185 clock-names = "uart", "clk_uart_baud0";
189 clocks = <&clock 258>, <&clock 129>;
190 clock-names = "uart", "clk_uart_baud0";
194 clocks = <&clock 259>, <&clock 130>;
195 clock-names = "uart", "clk_uart_baud0";
199 clocks = <&clock 260>, <&clock 131>;
200 clock-names = "uart", "clk_uart_baud0";
203 dp_phy: video-phy@10040728 {
204 compatible = "samsung,exynos5250-dp-video-phy";
205 reg = <0x10040728 4>;
209 dp-controller@145B0000 {
210 clocks = <&clock 412>;
217 samsung,power-domain = <&disp_pd>;
218 clocks = <&clock 147>, <&clock 421>;
219 clock-names = "sclk_fimd", "fimd";