2 * SAMSUNG EXYNOS5440 SoC device tree source
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include "skeleton.dtsi"
15 compatible = "samsung,exynos5440";
17 interrupt-parent = <&gic>;
23 clock: clock-controller@0x160000 {
24 compatible = "samsung,exynos5440-clock";
25 reg = <0x160000 0x1000>;
29 gic:interrupt-controller@2E0000 {
30 compatible = "arm,cortex-a15-gic";
31 #interrupt-cells = <3>;
33 reg = <0x2E1000 0x1000>,
37 interrupts = <1 9 0xf04>;
46 compatible = "arm,cortex-a15";
51 compatible = "arm,cortex-a15";
56 compatible = "arm,cortex-a15";
61 compatible = "arm,cortex-a15";
67 compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";
68 interrupts = <0 52 4>,
75 compatible = "arm,cortex-a15-timer",
77 interrupts = <1 13 0xf08>,
81 clock-frequency = <50000000>;
85 compatible = "samsung,exynos5440-cpufreq";
86 reg = <0x160000 0x1000>;
87 interrupts = <0 57 0>;
102 compatible = "samsung,exynos4210-uart";
103 reg = <0xB0000 0x1000>;
104 interrupts = <0 2 0>;
105 clocks = <&clock 21>, <&clock 21>;
106 clock-names = "uart", "clk_uart_baud0";
110 compatible = "samsung,exynos4210-uart";
111 reg = <0xC0000 0x1000>;
112 interrupts = <0 3 0>;
113 clocks = <&clock 21>, <&clock 21>;
114 clock-names = "uart", "clk_uart_baud0";
118 compatible = "samsung,exynos5440-spi";
119 reg = <0xD0000 0x100>;
120 interrupts = <0 4 0>;
121 #address-cells = <1>;
123 samsung,spi-src-clk = <0>;
125 clocks = <&clock 21>, <&clock 16>;
126 clock-names = "spi", "spi_busclk0";
130 compatible = "samsung,exynos5440-pinctrl";
131 reg = <0xE0000 0x1000>;
132 interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>,
133 <0 41 0>, <0 42 0>, <0 43 0>, <0 44 0>;
134 interrupt-controller;
135 #interrupt-cells = <2>;
139 samsung,exynos5440-pin-function = <1>;
143 samsung,exynos5440-pin-function = <2>;
147 samsung,exynos5440-pin-function = <3>;
151 samsung,exynos5440-pin-function = <4>;
156 compatible = "samsung,exynos5440-i2c";
157 reg = <0xF0000 0x1000>;
158 interrupts = <0 5 0>;
159 #address-cells = <1>;
161 clocks = <&clock 21>;
166 compatible = "samsung,exynos5440-i2c";
167 reg = <0x100000 0x1000>;
168 interrupts = <0 6 0>;
169 #address-cells = <1>;
171 clocks = <&clock 21>;
176 compatible = "samsung,s3c2410-wdt";
177 reg = <0x110000 0x1000>;
178 interrupts = <0 1 0>;
179 clocks = <&clock 21>;
180 clock-names = "watchdog";
183 gmac: ethernet@00230000 {
184 compatible = "snps,dwmac-3.70a";
185 reg = <0x00230000 0x8000>;
186 interrupt-parent = <&gic>;
187 interrupts = <0 31 4>;
188 interrupt-names = "macirq";
190 clocks = <&clock 25>;
191 clock-names = "stmmaceth";
195 #address-cells = <1>;
197 compatible = "arm,amba-bus";
198 interrupt-parent = <&gic>;
203 compatible = "samsung,s3c6410-rtc";
204 reg = <0x130000 0x1000>;
205 interrupts = <0 17 0>, <0 16 0>;
206 clocks = <&clock 21>;
211 compatible = "snps,exynos5440-ahci";
212 reg = <0x210000 0x10000>;
213 interrupts = <0 30 0>;
214 clocks = <&clock 23>;
215 clock-names = "sata";
219 compatible = "samsung,exynos5440-ohci";
220 reg = <0x220000 0x1000>;
221 interrupts = <0 29 0>;
222 clocks = <&clock 24>;
223 clock-names = "usbhost";
227 compatible = "samsung,exynos5440-ehci";
228 reg = <0x221000 0x1000>;
229 interrupts = <0 29 0>;
230 clocks = <&clock 24>;
231 clock-names = "usbhost";
235 compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
236 reg = <0x290000 0x1000
239 interrupts = <0 20 0>, <0 21 0>, <0 22 0>;
240 clocks = <&clock 28>, <&clock 27>;
241 clock-names = "pcie", "pcie_bus";
242 #address-cells = <3>;
245 ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000 /* configuration space */
246 0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */
247 0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */
248 #interrupt-cells = <1>;
249 interrupt-map-mask = <0 0 0 0>;
250 interrupt-map = <0x0 0 &gic 53>;
254 compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
255 reg = <0x2a0000 0x1000
258 interrupts = <0 23 0>, <0 24 0>, <0 25 0>;
259 clocks = <&clock 29>, <&clock 27>;
260 clock-names = "pcie", "pcie_bus";
261 #address-cells = <3>;
264 ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000 /* configuration space */
265 0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */
266 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */
267 #interrupt-cells = <1>;
268 interrupt-map-mask = <0 0 0 0>;
269 interrupt-map = <0x0 0 &gic 56>;