arch/arm/boot/dts/highbank.dts

   1 /*
   2  * Copyright 2011-2012 Calxeda, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 /dts-v1/;
  18
  19 /* First 4KB has pen for secondary cores. */
  20 /memreserve/ 0x00000000 0x0001000;
  21
  22 / {
  23         model = "Calxeda Highbank";
  24         compatible = "calxeda,highbank";
  25         #address-cells = <1>;
  26         #size-cells = <1>;
  27         clock-ranges;
  28
  29         cpus {
  30                 #address-cells = <1>;
  31                 #size-cells = <0>;
  32
  33                 cpu@0 {
  34                         compatible = "arm,cortex-a9";
  35                         reg = <0>;
  36                         next-level-cache = <&L2>;
  37                         clocks = <&a9pll>;
  38                         clock-names = "cpu";
  39                 };
  40
  41                 cpu@1 {
  42                         compatible = "arm,cortex-a9";
  43                         reg = <1>;
  44                         next-level-cache = <&L2>;
  45                         clocks = <&a9pll>;
  46                         clock-names = "cpu";
  47                 };
  48
  49                 cpu@2 {
  50                         compatible = "arm,cortex-a9";
  51                         reg = <2>;
  52                         next-level-cache = <&L2>;
  53                         clocks = <&a9pll>;
  54                         clock-names = "cpu";
  55                 };
  56
  57                 cpu@3 {
  58                         compatible = "arm,cortex-a9";
  59                         reg = <3>;
  60                         next-level-cache = <&L2>;
  61                         clocks = <&a9pll>;
  62                         clock-names = "cpu";
  63                 };
  64         };
  65
  66         memory {
  67                 name = "memory";
  68                 device_type = "memory";
  69                 reg = <0x00000000 0xff900000>;
  70         };
  71
  72         chosen {
  73                 bootargs = "console=ttyAMA0";
  74         };
  75
  76         soc {
  77                 #address-cells = <1>;
  78                 #size-cells = <1>;
  79                 compatible = "simple-bus";
  80                 interrupt-parent = <&intc>;
  81                 ranges;
  82
  83                 timer@fff10600 {
  84                         compatible = "arm,cortex-a9-twd-timer";
  85                         reg = <0xfff10600 0x20>;
  86                         interrupts = <1 13 0xf01>;
  87                         clocks = <&a9periphclk>;
  88                 };
  89
  90                 watchdog@fff10620 {
  91                         compatible = "arm,cortex-a9-twd-wdt";
  92                         reg = <0xfff10620 0x20>;
  93                         interrupts = <1 14 0xf01>;
  94                         clocks = <&a9periphclk>;
  95                 };
  96
  97                 intc: interrupt-controller@fff11000 {
  98                         compatible = "arm,cortex-a9-gic";
  99                         #interrupt-cells = <3>;
 100                         #size-cells = <0>;
 101                         #address-cells = <1>;
 102                         interrupt-controller;
 103                         reg = <0xfff11000 0x1000>,
 104                               <0xfff10100 0x100>;
 105                 };
 106
 107                 L2: l2-cache {
 108                         compatible = "arm,pl310-cache";
 109                         reg = <0xfff12000 0x1000>;
 110                         interrupts = <0 70 4>;
 111                         cache-unified;
 112                         cache-level = <2>;
 113                 };
 114
 115                 pmu {
 116                         compatible = "arm,cortex-a9-pmu";
 117                         interrupts = <0 76 4  0 75 4  0 74 4  0 73 4>;
 118                 };
 119
 120                 sata@ffe08000 {
 121                         compatible = "calxeda,hb-ahci";
 122                         reg = <0xffe08000 0x10000>;
 123                         interrupts = <0 83 4>;
 124                         calxeda,port-phys = <&combophy5 0 &combophy0 0
 125                                              &combophy0 1 &combophy0 2
 126                                              &combophy0 3>;
 127                         dma-coherent;
 128                 };
 129
 130                 sdhci@ffe0e000 {
 131                         compatible = "calxeda,hb-sdhci";
 132                         reg = <0xffe0e000 0x1000>;
 133                         interrupts = <0 90 4>;
 134                         clocks = <&eclk>;
 135                 };
 136
 137                 memory-controller@fff00000 {
 138                         compatible = "calxeda,hb-ddr-ctrl";
 139                         reg = <0xfff00000 0x1000>;
 140                         interrupts = <0 91 4>;
 141                 };
 142
 143                 ipc@fff20000 {
 144                         compatible = "arm,pl320", "arm,primecell";
 145                         reg = <0xfff20000 0x1000>;
 146                         interrupts = <0 7 4>;
 147                         clocks = <&pclk>;
 148                         clock-names = "apb_pclk";
 149                 };
 150
 151                 gpioe: gpio@fff30000 {
 152                         #gpio-cells = <2>;
 153                         compatible = "arm,pl061", "arm,primecell";
 154                         gpio-controller;
 155                         reg = <0xfff30000 0x1000>;
 156                         interrupts = <0 14 4>;
 157                         clocks = <&pclk>;
 158                         clock-names = "apb_pclk";
 159                 };
 160
 161                 gpiof: gpio@fff31000 {
 162                         #gpio-cells = <2>;
 163                         compatible = "arm,pl061", "arm,primecell";
 164                         gpio-controller;
 165                         reg = <0xfff31000 0x1000>;
 166                         interrupts = <0 15 4>;
 167                         clocks = <&pclk>;
 168                         clock-names = "apb_pclk";
 169                 };
 170
 171                 gpiog: gpio@fff32000 {
 172                         #gpio-cells = <2>;
 173                         compatible = "arm,pl061", "arm,primecell";
 174                         gpio-controller;
 175                         reg = <0xfff32000 0x1000>;
 176                         interrupts = <0 16 4>;
 177                         clocks = <&pclk>;
 178                         clock-names = "apb_pclk";
 179                 };
 180
 181                 gpioh: gpio@fff33000 {
 182                         #gpio-cells = <2>;
 183                         compatible = "arm,pl061", "arm,primecell";
 184                         gpio-controller;
 185                         reg = <0xfff33000 0x1000>;
 186                         interrupts = <0 17 4>;
 187                         clocks = <&pclk>;
 188                         clock-names = "apb_pclk";
 189                 };
 190
 191                 timer {
 192                         compatible = "arm,sp804", "arm,primecell";
 193                         reg = <0xfff34000 0x1000>;
 194                         interrupts = <0 18 4>;
 195                         clocks = <&pclk>;
 196                         clock-names = "apb_pclk";
 197                 };
 198
 199                 rtc@fff35000 {
 200                         compatible = "arm,pl031", "arm,primecell";
 201                         reg = <0xfff35000 0x1000>;
 202                         interrupts = <0 19 4>;
 203                         clocks = <&pclk>;
 204                         clock-names = "apb_pclk";
 205                 };
 206
 207                 serial@fff36000 {
 208                         compatible = "arm,pl011", "arm,primecell";
 209                         reg = <0xfff36000 0x1000>;
 210                         interrupts = <0 20 4>;
 211                         clocks = <&pclk>;
 212                         clock-names = "apb_pclk";
 213                 };
 214
 215                 smic@fff3a000 {
 216                         compatible = "ipmi-smic";
 217                         device_type = "ipmi";
 218                         reg = <0xfff3a000 0x1000>;
 219                         interrupts = <0 24 4>;
 220                         reg-size = <4>;
 221                         reg-spacing = <4>;
 222                 };
 223
 224                 sregs@fff3c000 {
 225                         compatible = "calxeda,hb-sregs";
 226                         reg = <0xfff3c000 0x1000>;
 227
 228                         clocks {
 229                                 #address-cells = <1>;
 230                                 #size-cells = <0>;
 231
 232                                 osc: oscillator {
 233                                         #clock-cells = <0>;
 234                                         compatible = "fixed-clock";
 235                                         clock-frequency = <33333000>;
 236                                 };
 237
 238                                 ddrpll: ddrpll {
 239                                         #clock-cells = <0>;
 240                                         compatible = "calxeda,hb-pll-clock";
 241                                         clocks = <&osc>;
 242                                         reg = <0x108>;
 243                                 };
 244
 245                                 a9pll: a9pll {
 246                                         #clock-cells = <0>;
 247                                         compatible = "calxeda,hb-pll-clock";
 248                                         clocks = <&osc>;
 249                                         reg = <0x100>;
 250                                 };
 251
 252                                 a9periphclk: a9periphclk {
 253                                         #clock-cells = <0>;
 254                                         compatible = "calxeda,hb-a9periph-clock";
 255                                         clocks = <&a9pll>;
 256                                         reg = <0x104>;
 257                                 };
 258
 259                                 a9bclk: a9bclk {
 260                                         #clock-cells = <0>;
 261                                         compatible = "calxeda,hb-a9bus-clock";
 262                                         clocks = <&a9pll>;
 263                                         reg = <0x104>;
 264                                 };
 265
 266                                 emmcpll: emmcpll {
 267                                         #clock-cells = <0>;
 268                                         compatible = "calxeda,hb-pll-clock";
 269                                         clocks = <&osc>;
 270                                         reg = <0x10C>;
 271                                 };
 272
 273                                 eclk: eclk {
 274                                         #clock-cells = <0>;
 275                                         compatible = "calxeda,hb-emmc-clock";
 276                                         clocks = <&emmcpll>;
 277                                         reg = <0x114>;
 278                                 };
 279
 280                                 pclk: pclk {
 281                                         #clock-cells = <0>;
 282                                         compatible = "fixed-clock";
 283                                         clock-frequency = <150000000>;
 284                                 };
 285                         };
 286                 };
 287
 288                 sregs@fff3c200 {
 289                         compatible = "calxeda,hb-sregs-l2-ecc";
 290                         reg = <0xfff3c200 0x100>;
 291                         interrupts = <0 71 4  0 72 4>;
 292                 };
 293
 294                 dma@fff3d000 {
 295                         compatible = "arm,pl330", "arm,primecell";
 296                         reg = <0xfff3d000 0x1000>;
 297                         interrupts = <0 92 4>;
 298                         clocks = <&pclk>;
 299                         clock-names = "apb_pclk";
 300                 };
 301
 302                 ethernet@fff50000 {
 303                         compatible = "calxeda,hb-xgmac";
 304                         reg = <0xfff50000 0x1000>;
 305                         interrupts = <0 77 4  0 78 4  0 79 4>;
 306                 };
 307
 308                 ethernet@fff51000 {
 309                         compatible = "calxeda,hb-xgmac";
 310                         reg = <0xfff51000 0x1000>;
 311                         interrupts = <0 80 4  0 81 4  0 82 4>;
 312                 };
 313
 314                 combophy0: combo-phy@fff58000 {
 315                         compatible = "calxeda,hb-combophy";
 316                         #phy-cells = <1>;
 317                         reg = <0xfff58000 0x1000>;
 318                         phydev = <5>;
 319                 };
 320
 321                 combophy5: combo-phy@fff5d000 {
 322                         compatible = "calxeda,hb-combophy";
 323                         #phy-cells = <1>;
 324                         reg = <0xfff5d000 0x1000>;
 325                         phydev = <31>;
 326                 };
 327         };
 328 };