2 * Copyright 2011-2012 Calxeda, Inc.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
19 /* First 4KB has pen for secondary cores. */
20 /memreserve/ 0x00000000 0x0001000;
23 model = "Calxeda Highbank";
24 compatible = "calxeda,highbank";
34 compatible = "arm,cortex-a9";
37 next-level-cache = <&L2>;
43 compatible = "arm,cortex-a9";
46 next-level-cache = <&L2>;
52 compatible = "arm,cortex-a9";
55 next-level-cache = <&L2>;
61 compatible = "arm,cortex-a9";
64 next-level-cache = <&L2>;
72 device_type = "memory";
73 reg = <0x00000000 0xff900000>;
77 ranges = <0x00000000 0x00000000 0xffffffff>;
80 compatible = "arm,cortex-a9-twd-timer";
81 reg = <0xfff10600 0x20>;
82 interrupts = <1 13 0xf01>;
83 clocks = <&a9periphclk>;
87 compatible = "arm,cortex-a9-twd-wdt";
88 reg = <0xfff10620 0x20>;
89 interrupts = <1 14 0xf01>;
90 clocks = <&a9periphclk>;
93 intc: interrupt-controller@fff11000 {
94 compatible = "arm,cortex-a9-gic";
95 #interrupt-cells = <3>;
99 reg = <0xfff11000 0x1000>,
104 compatible = "arm,pl310-cache";
105 reg = <0xfff12000 0x1000>;
106 interrupts = <0 70 4>;
112 compatible = "arm,cortex-a9-pmu";
113 interrupts = <0 76 4 0 75 4 0 74 4 0 73 4>;
118 compatible = "calxeda,hb-sregs-l2-ecc";
119 reg = <0xfff3c200 0x100>;
120 interrupts = <0 71 4 0 72 4>;
126 /include/ "ecx-common.dtsi"