arch/arm/boot/dts/imx27-phytec-phycore-som.dts

   1 /*
   2  * Copyright 2012 Sascha Hauer, Pengutronix
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License. You may obtain a copy of the GNU General Public License
   6  * Version 2 or later at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  */
  11
  12 /dts-v1/;
  13 #include "imx27.dtsi"
  14
  15 / {
  16         model = "Phytec pcm038";
  17         compatible = "phytec,imx27-pcm038", "fsl,imx27";
  18
  19         memory {
  20                 reg = <0xa0000000 0x08000000>;
  21         };
  22 };
  23
  24 &audmux {
  25         status = "okay";
  26
  27         /* SSI0 <=> PINS_4 (MC13783 Audio) */
  28         ssi0 {
  29                 fsl,audmux-port = <0>;
  30                 fsl,port-config = <0xcb205000>;
  31         };
  32
  33         pins4 {
  34                 fsl,audmux-port = <2>;
  35                 fsl,port-config = <0x00001000>;
  36         };
  37 };
  38
  39 &cspi1 {
  40         fsl,spi-num-chipselects = <1>;
  41         cs-gpios = <&gpio4 28 0>;
  42         status = "okay";
  43
  44         pmic: mc13783@0 {
  45                 #address-cells = <1>;
  46                 #size-cells = <0>;
  47                 compatible = "fsl,mc13783";
  48                 spi-max-frequency = <20000000>;
  49                 reg = <0>;
  50                 interrupt-parent = <&gpio2>;
  51                 interrupts = <23 0x4>;
  52                 fsl,mc13xxx-uses-adc;
  53                 fsl,mc13xxx-uses-rtc;
  54
  55                 regulators {
  56                         /* SW1A and SW1B joined operation */
  57                         sw1_reg: sw1a {
  58                                 regulator-min-microvolt = <1200000>;
  59                                 regulator-max-microvolt = <1520000>;
  60                                 regulator-always-on;
  61                                 regulator-boot-on;
  62                         };
  63
  64                         /* SW2A and SW2B joined operation */
  65                         sw2_reg: sw2a {
  66                                 regulator-min-microvolt = <1800000>;
  67                                 regulator-max-microvolt = <1800000>;
  68                                 regulator-always-on;
  69                                 regulator-boot-on;
  70                         };
  71
  72                         sw3_reg: sw3 {
  73                                 regulator-min-microvolt = <5000000>;
  74                                 regulator-max-microvolt = <5000000>;
  75                                 regulator-always-on;
  76                                 regulator-boot-on;
  77                         };
  78
  79                         vaudio_reg: vaudio {
  80                                 regulator-always-on;
  81                                 regulator-boot-on;
  82                         };
  83
  84                         violo_reg: violo {
  85                                 regulator-min-microvolt = <1800000>;
  86                                 regulator-max-microvolt = <1800000>;
  87                                 regulator-always-on;
  88                                 regulator-boot-on;
  89                         };
  90
  91                         viohi_reg: viohi {
  92                                 regulator-always-on;
  93                                 regulator-boot-on;
  94                         };
  95
  96                         vgen_reg: vgen {
  97                                 regulator-min-microvolt = <1500000>;
  98                                 regulator-max-microvolt = <1500000>;
  99                                 regulator-always-on;
 100                                 regulator-boot-on;
 101                         };
 102
 103                         vcam_reg: vcam {
 104                                 regulator-min-microvolt = <2800000>;
 105                                 regulator-max-microvolt = <2800000>;
 106                         };
 107
 108                         vrf1_reg: vrf1 {
 109                                 regulator-min-microvolt = <2775000>;
 110                                 regulator-max-microvolt = <2775000>;
 111                                 regulator-always-on;
 112                                 regulator-boot-on;
 113                         };
 114
 115                         vrf2_reg: vrf2 {
 116                                 regulator-min-microvolt = <2775000>;
 117                                 regulator-max-microvolt = <2775000>;
 118                                 regulator-always-on;
 119                                 regulator-boot-on;
 120                         };
 121
 122                         vmmc1_reg: vmmc1 {
 123                                 regulator-min-microvolt = <1600000>;
 124                                 regulator-max-microvolt = <3000000>;
 125                         };
 126
 127                         gpo1_reg: gpo1 { };
 128
 129                         pwgt1spi_reg: pwgt1spi {
 130                                 regulator-always-on;
 131                         };
 132                 };
 133         };
 134 };
 135
 136 &fec {
 137         phy-reset-gpios = <&gpio3 30 0>;
 138         pinctrl-names = "default";
 139         pinctrl-0 = <&pinctrl_fec1>;
 140         status = "okay";
 141 };
 142
 143 &i2c2 {
 144         clock-frequency = <400000>;
 145         pinctrl-names = "default";
 146         pinctrl-0 = <&pinctrl_i2c2>;
 147         status = "okay";
 148
 149         at24@52 {
 150                 compatible = "at,24c32";
 151                 pagesize = <32>;
 152                 reg = <0x52>;
 153         };
 154
 155         pcf8563@51 {
 156                 compatible = "nxp,pcf8563";
 157                 reg = <0x51>;
 158         };
 159
 160         lm75@4a {
 161                 compatible = "national,lm75";
 162                 reg = <0x4a>;
 163         };
 164 };
 165
 166 &iomuxc {
 167         imx27_phycore_som {
 168                 pinctrl_fec1: fec1grp {
 169                         fsl,pins = <
 170                                 MX27_PAD_SD3_CMD__FEC_TXD0 0x0
 171                                 MX27_PAD_SD3_CLK__FEC_TXD1 0x0
 172                                 MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
 173                                 MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
 174                                 MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
 175                                 MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
 176                                 MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
 177                                 MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
 178                                 MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
 179                                 MX27_PAD_ATA_DATA7__FEC_MDC 0x0
 180                                 MX27_PAD_ATA_DATA8__FEC_CRS 0x0
 181                                 MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
 182                                 MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
 183                                 MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
 184                                 MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
 185                                 MX27_PAD_ATA_DATA13__FEC_COL 0x0
 186                                 MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
 187                                 MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
 188                                 MX27_PAD_SSI3_TXDAT__GPIO3_30   0x0 /* FEC RST */
 189                         >;
 190                 };
 191
 192                 pinctrl_i2c2: i2c2grp {
 193                         fsl,pins = <
 194                                 MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
 195                                 MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
 196                         >;
 197                 };
 198         };
 199 };
 200
 201 &nfc {
 202         nand-bus-width = <8>;
 203         nand-ecc-mode = "hw";
 204         status = "okay";
 205 };
 206
 207 &weim {
 208         status = "okay";
 209
 210         nor: nor@c0000000 {
 211                 compatible = "cfi-flash";
 212                 reg = <0 0x00000000 0x02000000>;
 213                 bank-width = <2>;
 214                 linux,mtd-name = "physmap-flash.0";
 215                 fsl,weim-cs-timing = <0x22c2cf00 0x75000d01 0x00000900>;
 216                 #address-cells = <1>;
 217                 #size-cells = <1>;
 218         };
 219
 220         sram: sram@c8000000 {
 221                 compatible = "mtd-ram";
 222                 reg = <1 0x00000000 0x00800000>;
 223                 bank-width = <2>;
 224                 linux,mtd-name = "mtd-ram.0";
 225                 fsl,weim-cs-timing = <0x0000d843 0x22252521 0x22220a00>;
 226                 #address-cells = <1>;
 227                 #size-cells = <1>;
 228         };
 229 };