2 * Copyright 2012 Sascha Hauer, Pengutronix
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
12 #include "skeleton.dtsi"
13 #include "imx27-pinfunc.h"
14 #include <dt-bindings/interrupt-controller/irq.h>
15 #include <dt-bindings/gpio/gpio.h>
38 aitc: aitc-interrupt-controller@e0000000 {
39 compatible = "fsl,imx27-aitc", "fsl,avic";
41 #interrupt-cells = <1>;
42 reg = <0x10040000 0x1000>;
50 compatible = "fsl,imx-osc26m", "fixed-clock";
51 clock-frequency = <26000000>;
61 compatible = "arm,arm926ej-s";
67 clock-latency = <62500>;
69 voltage-tolerance = <5>;
74 compatible = "simple-bus";
79 compatible = "usb-nop-xceiv";
82 clock-names = "main_clk";
86 compatible = "usb-nop-xceiv";
89 clock-names = "main_clk";
96 compatible = "simple-bus";
97 interrupt-parent = <&aitc>;
100 aipi@10000000 { /* AIPI1 */
101 compatible = "fsl,aipi-bus", "simple-bus";
102 #address-cells = <1>;
104 reg = <0x10000000 0x20000>;
108 compatible = "fsl,imx27-dma";
109 reg = <0x10001000 0x1000>;
111 clocks = <&clks 50>, <&clks 70>;
112 clock-names = "ipg", "ahb";
114 #dma-channels = <16>;
117 wdog: wdog@10002000 {
118 compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
119 reg = <0x10002000 0x1000>;
124 gpt1: timer@10003000 {
125 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
126 reg = <0x10003000 0x1000>;
128 clocks = <&clks 46>, <&clks 61>;
129 clock-names = "ipg", "per";
132 gpt2: timer@10004000 {
133 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
134 reg = <0x10004000 0x1000>;
136 clocks = <&clks 45>, <&clks 61>;
137 clock-names = "ipg", "per";
140 gpt3: timer@10005000 {
141 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
142 reg = <0x10005000 0x1000>;
144 clocks = <&clks 44>, <&clks 61>;
145 clock-names = "ipg", "per";
150 compatible = "fsl,imx27-pwm";
151 reg = <0x10006000 0x1000>;
153 clocks = <&clks 34>, <&clks 61>;
154 clock-names = "ipg", "per";
158 compatible = "fsl,imx27-kpp", "fsl,imx21-kpp";
159 reg = <0x10008000 0x1000>;
165 owire: owire@10009000 {
166 compatible = "fsl,imx27-owire", "fsl,imx21-owire";
167 reg = <0x10009000 0x1000>;
172 uart1: serial@1000a000 {
173 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
174 reg = <0x1000a000 0x1000>;
176 clocks = <&clks 81>, <&clks 61>;
177 clock-names = "ipg", "per";
181 uart2: serial@1000b000 {
182 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
183 reg = <0x1000b000 0x1000>;
185 clocks = <&clks 80>, <&clks 61>;
186 clock-names = "ipg", "per";
190 uart3: serial@1000c000 {
191 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
192 reg = <0x1000c000 0x1000>;
194 clocks = <&clks 79>, <&clks 61>;
195 clock-names = "ipg", "per";
199 uart4: serial@1000d000 {
200 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
201 reg = <0x1000d000 0x1000>;
203 clocks = <&clks 78>, <&clks 61>;
204 clock-names = "ipg", "per";
208 cspi1: cspi@1000e000 {
209 #address-cells = <1>;
211 compatible = "fsl,imx27-cspi";
212 reg = <0x1000e000 0x1000>;
214 clocks = <&clks 53>, <&clks 60>;
215 clock-names = "ipg", "per";
219 cspi2: cspi@1000f000 {
220 #address-cells = <1>;
222 compatible = "fsl,imx27-cspi";
223 reg = <0x1000f000 0x1000>;
225 clocks = <&clks 52>, <&clks 60>;
226 clock-names = "ipg", "per";
231 #sound-dai-cells = <0>;
232 compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
233 reg = <0x10010000 0x1000>;
236 dmas = <&dma 12>, <&dma 13>, <&dma 14>, <&dma 15>;
237 dma-names = "rx0", "tx0", "rx1", "tx1";
238 fsl,fifo-depth = <8>;
243 #sound-dai-cells = <0>;
244 compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
245 reg = <0x10011000 0x1000>;
248 dmas = <&dma 8>, <&dma 9>, <&dma 10>, <&dma 11>;
249 dma-names = "rx0", "tx0", "rx1", "tx1";
250 fsl,fifo-depth = <8>;
255 #address-cells = <1>;
257 compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
258 reg = <0x10012000 0x1000>;
264 sdhci1: sdhci@10013000 {
265 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
266 reg = <0x10013000 0x1000>;
268 clocks = <&clks 30>, <&clks 60>;
269 clock-names = "ipg", "per";
275 sdhci2: sdhci@10014000 {
276 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
277 reg = <0x10014000 0x1000>;
279 clocks = <&clks 29>, <&clks 60>;
280 clock-names = "ipg", "per";
286 iomuxc: iomuxc@10015000 {
287 compatible = "fsl,imx27-iomuxc";
288 reg = <0x10015000 0x600>;
289 #address-cells = <1>;
293 gpio1: gpio@10015000 {
294 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
295 reg = <0x10015000 0x100>;
299 interrupt-controller;
300 #interrupt-cells = <2>;
303 gpio2: gpio@10015100 {
304 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
305 reg = <0x10015100 0x100>;
309 interrupt-controller;
310 #interrupt-cells = <2>;
313 gpio3: gpio@10015200 {
314 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
315 reg = <0x10015200 0x100>;
319 interrupt-controller;
320 #interrupt-cells = <2>;
323 gpio4: gpio@10015300 {
324 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
325 reg = <0x10015300 0x100>;
329 interrupt-controller;
330 #interrupt-cells = <2>;
333 gpio5: gpio@10015400 {
334 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
335 reg = <0x10015400 0x100>;
339 interrupt-controller;
340 #interrupt-cells = <2>;
343 gpio6: gpio@10015500 {
344 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
345 reg = <0x10015500 0x100>;
349 interrupt-controller;
350 #interrupt-cells = <2>;
354 audmux: audmux@10016000 {
355 compatible = "fsl,imx27-audmux", "fsl,imx21-audmux";
356 reg = <0x10016000 0x1000>;
358 clock-names = "audmux";
362 cspi3: cspi@10017000 {
363 #address-cells = <1>;
365 compatible = "fsl,imx27-cspi";
366 reg = <0x10017000 0x1000>;
368 clocks = <&clks 51>, <&clks 60>;
369 clock-names = "ipg", "per";
373 gpt4: timer@10019000 {
374 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
375 reg = <0x10019000 0x1000>;
377 clocks = <&clks 43>, <&clks 61>;
378 clock-names = "ipg", "per";
381 gpt5: timer@1001a000 {
382 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
383 reg = <0x1001a000 0x1000>;
385 clocks = <&clks 42>, <&clks 61>;
386 clock-names = "ipg", "per";
389 uart5: serial@1001b000 {
390 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
391 reg = <0x1001b000 0x1000>;
393 clocks = <&clks 77>, <&clks 61>;
394 clock-names = "ipg", "per";
398 uart6: serial@1001c000 {
399 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
400 reg = <0x1001c000 0x1000>;
402 clocks = <&clks 78>, <&clks 61>;
403 clock-names = "ipg", "per";
408 #address-cells = <1>;
410 compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
411 reg = <0x1001d000 0x1000>;
417 sdhci3: sdhci@1001e000 {
418 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
419 reg = <0x1001e000 0x1000>;
421 clocks = <&clks 28>, <&clks 60>;
422 clock-names = "ipg", "per";
428 gpt6: timer@1001f000 {
429 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
430 reg = <0x1001f000 0x1000>;
432 clocks = <&clks 41>, <&clks 61>;
433 clock-names = "ipg", "per";
437 aipi@10020000 { /* AIPI2 */
438 compatible = "fsl,aipi-bus", "simple-bus";
439 #address-cells = <1>;
441 reg = <0x10020000 0x20000>;
445 compatible = "fsl,imx27-fb", "fsl,imx21-fb";
447 reg = <0x10021000 0x1000>;
448 clocks = <&clks 36>, <&clks 65>, <&clks 59>;
449 clock-names = "ipg", "ahb", "per";
453 coda: coda@10023000 {
454 compatible = "fsl,imx27-vpu";
455 reg = <0x10023000 0x0200>;
457 clocks = <&clks 57>, <&clks 66>;
458 clock-names = "per", "ahb";
462 usbotg: usb@10024000 {
463 compatible = "fsl,imx27-usb";
464 reg = <0x10024000 0x200>;
467 fsl,usbmisc = <&usbmisc 0>;
468 fsl,usbphy = <&usbphy0>;
472 usbh1: usb@10024200 {
473 compatible = "fsl,imx27-usb";
474 reg = <0x10024200 0x200>;
477 fsl,usbmisc = <&usbmisc 1>;
481 usbh2: usb@10024400 {
482 compatible = "fsl,imx27-usb";
483 reg = <0x10024400 0x200>;
486 fsl,usbmisc = <&usbmisc 2>;
487 fsl,usbphy = <&usbphy2>;
491 usbmisc: usbmisc@10024600 {
493 compatible = "fsl,imx27-usbmisc";
494 reg = <0x10024600 0x200>;
498 sahara2: sahara@10025000 {
499 compatible = "fsl,imx27-sahara";
500 reg = <0x10025000 0x1000>;
502 clocks = <&clks 32>, <&clks 64>;
503 clock-names = "ipg", "ahb";
507 compatible = "fsl,imx27-ccm";
508 reg = <0x10027000 0x1000>;
513 compatible = "fsl,imx27-iim";
514 reg = <0x10028000 0x1000>;
519 fec: ethernet@1002b000 {
520 compatible = "fsl,imx27-fec";
521 reg = <0x1002b000 0x4000>;
523 clocks = <&clks 48>, <&clks 67>;
524 clock-names = "ipg", "ahb";
530 #address-cells = <1>;
532 compatible = "fsl,imx27-nand";
533 reg = <0xd8000000 0x1000>;
539 weim: weim@d8002000 {
540 #address-cells = <2>;
542 compatible = "fsl,imx27-weim";
543 reg = <0xd8002000 0x1000>;
546 0 0 0xc0000000 0x08000000
547 1 0 0xc8000000 0x08000000
548 2 0 0xd0000000 0x02000000
549 3 0 0xd2000000 0x02000000
550 4 0 0xd4000000 0x02000000
551 5 0 0xd6000000 0x02000000
556 iram: iram@ffff4c00 {
557 compatible = "mmio-sram";
558 reg = <0xffff4c00 0xb400>;