arch/arm/boot/dts/imx27.dtsi

   1 /*
   2  * Copyright 2012 Sascha Hauer, Pengutronix
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License. You may obtain a copy of the GNU General Public License
   6  * Version 2 or later at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  */
  11
  12 #include "skeleton.dtsi"
  13
  14 / {
  15         aliases {
  16                 gpio0 = &gpio1;
  17                 gpio1 = &gpio2;
  18                 gpio2 = &gpio3;
  19                 gpio3 = &gpio4;
  20                 gpio4 = &gpio5;
  21                 gpio5 = &gpio6;
  22                 i2c0 = &i2c1;
  23                 i2c1 = &i2c2;
  24                 serial0 = &uart1;
  25                 serial1 = &uart2;
  26                 serial2 = &uart3;
  27                 serial3 = &uart4;
  28                 serial4 = &uart5;
  29                 serial5 = &uart6;
  30                 spi0 = &cspi1;
  31                 spi1 = &cspi2;
  32                 spi2 = &cspi3;
  33         };
  34
  35         aitc: aitc-interrupt-controller@e0000000 {
  36                 compatible = "fsl,imx27-aitc", "fsl,avic";
  37                 interrupt-controller;
  38                 #interrupt-cells = <1>;
  39                 reg = <0x10040000 0x1000>;
  40         };
  41
  42         clocks {
  43                 #address-cells = <1>;
  44                 #size-cells = <0>;
  45
  46                 osc26m {
  47                         compatible = "fsl,imx-osc26m", "fixed-clock";
  48                         clock-frequency = <26000000>;
  49                 };
  50         };
  51
  52         cpus {
  53                 #size-cells = <0>;
  54                 #address-cells = <1>;
  55
  56                 cpu: cpu@0 {
  57                         device_type = "cpu";
  58                         compatible = "arm,arm926ej-s";
  59                         operating-points = <
  60                                 /* kHz uV */
  61                                 266000 1300000
  62                                 399000 1450000
  63                         >;
  64                         clock-latency = <62500>;
  65                         clocks = <&clks 18>;
  66                         voltage-tolerance = <5>;
  67                 };
  68         };
  69
  70         soc {
  71                 #address-cells = <1>;
  72                 #size-cells = <1>;
  73                 compatible = "simple-bus";
  74                 interrupt-parent = <&aitc>;
  75                 ranges;
  76
  77                 aipi@10000000 { /* AIPI1 */
  78                         compatible = "fsl,aipi-bus", "simple-bus";
  79                         #address-cells = <1>;
  80                         #size-cells = <1>;
  81                         reg = <0x10000000 0x20000>;
  82                         ranges;
  83
  84                         dma: dma@10001000 {
  85                                 compatible = "fsl,imx27-dma";
  86                                 reg = <0x10001000 0x1000>;
  87                                 interrupts = <32>;
  88                                 clocks = <&clks 50>, <&clks 70>;
  89                                 clock-names = "ipg", "ahb";
  90                                 #dma-cells = <1>;
  91                                 #dma-channels = <16>;
  92                         };
  93
  94                         wdog: wdog@10002000 {
  95                                 compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
  96                                 reg = <0x10002000 0x1000>;
  97                                 interrupts = <27>;
  98                                 clocks = <&clks 74>;
  99                         };
 100
 101                         gpt1: timer@10003000 {
 102                                 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
 103                                 reg = <0x10003000 0x1000>;
 104                                 interrupts = <26>;
 105                                 clocks = <&clks 46>, <&clks 61>;
 106                                 clock-names = "ipg", "per";
 107                         };
 108
 109                         gpt2: timer@10004000 {
 110                                 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
 111                                 reg = <0x10004000 0x1000>;
 112                                 interrupts = <25>;
 113                                 clocks = <&clks 45>, <&clks 61>;
 114                                 clock-names = "ipg", "per";
 115                         };
 116
 117                         gpt3: timer@10005000 {
 118                                 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
 119                                 reg = <0x10005000 0x1000>;
 120                                 interrupts = <24>;
 121                                 clocks = <&clks 44>, <&clks 61>;
 122                                 clock-names = "ipg", "per";
 123                         };
 124
 125                         pwm: pwm@10006000 {
 126                                 #pwm-cells = <2>;
 127                                 compatible = "fsl,imx27-pwm";
 128                                 reg = <0x10006000 0x1000>;
 129                                 interrupts = <23>;
 130                                 clocks = <&clks 34>, <&clks 61>;
 131                                 clock-names = "ipg", "per";
 132                         };
 133
 134                         kpp: kpp@10008000 {
 135                                 compatible = "fsl,imx27-kpp", "fsl,imx21-kpp";
 136                                 reg = <0x10008000 0x1000>;
 137                                 interrupts = <21>;
 138                                 clocks = <&clks 37>;
 139                                 status = "disabled";
 140                         };
 141
 142                         owire: owire@10009000 {
 143                                 compatible = "fsl,imx27-owire", "fsl,imx21-owire";
 144                                 reg = <0x10009000 0x1000>;
 145                                 clocks = <&clks 35>;
 146                                 status = "disabled";
 147                         };
 148
 149                         uart1: serial@1000a000 {
 150                                 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
 151                                 reg = <0x1000a000 0x1000>;
 152                                 interrupts = <20>;
 153                                 clocks = <&clks 81>, <&clks 61>;
 154                                 clock-names = "ipg", "per";
 155                                 status = "disabled";
 156                         };
 157
 158                         uart2: serial@1000b000 {
 159                                 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
 160                                 reg = <0x1000b000 0x1000>;
 161                                 interrupts = <19>;
 162                                 clocks = <&clks 80>, <&clks 61>;
 163                                 clock-names = "ipg", "per";
 164                                 status = "disabled";
 165                         };
 166
 167                         uart3: serial@1000c000 {
 168                                 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
 169                                 reg = <0x1000c000 0x1000>;
 170                                 interrupts = <18>;
 171                                 clocks = <&clks 79>, <&clks 61>;
 172                                 clock-names = "ipg", "per";
 173                                 status = "disabled";
 174                         };
 175
 176                         uart4: serial@1000d000 {
 177                                 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
 178                                 reg = <0x1000d000 0x1000>;
 179                                 interrupts = <17>;
 180                                 clocks = <&clks 78>, <&clks 61>;
 181                                 clock-names = "ipg", "per";
 182                                 status = "disabled";
 183                         };
 184
 185                         cspi1: cspi@1000e000 {
 186                                 #address-cells = <1>;
 187                                 #size-cells = <0>;
 188                                 compatible = "fsl,imx27-cspi";
 189                                 reg = <0x1000e000 0x1000>;
 190                                 interrupts = <16>;
 191                                 clocks = <&clks 53>, <&clks 60>;
 192                                 clock-names = "ipg", "per";
 193                                 status = "disabled";
 194                         };
 195
 196                         cspi2: cspi@1000f000 {
 197                                 #address-cells = <1>;
 198                                 #size-cells = <0>;
 199                                 compatible = "fsl,imx27-cspi";
 200                                 reg = <0x1000f000 0x1000>;
 201                                 interrupts = <15>;
 202                                 clocks = <&clks 52>, <&clks 60>;
 203                                 clock-names = "ipg", "per";
 204                                 status = "disabled";
 205                         };
 206
 207                         i2c1: i2c@10012000 {
 208                                 #address-cells = <1>;
 209                                 #size-cells = <0>;
 210                                 compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
 211                                 reg = <0x10012000 0x1000>;
 212                                 interrupts = <12>;
 213                                 clocks = <&clks 40>;
 214                                 status = "disabled";
 215                         };
 216
 217                         sdhci1: sdhci@10013000 {
 218                                 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
 219                                 reg = <0x10013000 0x1000>;
 220                                 interrupts = <11>;
 221                                 clocks = <&clks 30>, <&clks 60>;
 222                                 clock-names = "ipg", "per";
 223                                 dmas = <&dma 7>;
 224                                 dma-names = "rx-tx";
 225                                 status = "disabled";
 226                         };
 227
 228                         sdhci2: sdhci@10014000 {
 229                                 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
 230                                 reg = <0x10014000 0x1000>;
 231                                 interrupts = <10>;
 232                                 clocks = <&clks 29>, <&clks 60>;
 233                                 clock-names = "ipg", "per";
 234                                 dmas = <&dma 6>;
 235                                 dma-names = "rx-tx";
 236                                 status = "disabled";
 237                         };
 238
 239                         iomuxc: iomuxc@10015000 {
 240                                 compatible = "fsl,imx27-iomuxc";
 241                                 reg = <0x10015000 0x600>;
 242                                 #address-cells = <1>;
 243                                 #size-cells = <1>;
 244                                 ranges;
 245
 246                                 gpio1: gpio@10015000 {
 247                                         compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
 248                                         reg = <0x10015000 0x100>;
 249                                         interrupts = <8>;
 250                                         gpio-controller;
 251                                         #gpio-cells = <2>;
 252                                         interrupt-controller;
 253                                         #interrupt-cells = <2>;
 254                                 };
 255
 256                                 gpio2: gpio@10015100 {
 257                                         compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
 258                                         reg = <0x10015100 0x100>;
 259                                         interrupts = <8>;
 260                                         gpio-controller;
 261                                         #gpio-cells = <2>;
 262                                         interrupt-controller;
 263                                         #interrupt-cells = <2>;
 264                                 };
 265
 266                                 gpio3: gpio@10015200 {
 267                                         compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
 268                                         reg = <0x10015200 0x100>;
 269                                         interrupts = <8>;
 270                                         gpio-controller;
 271                                         #gpio-cells = <2>;
 272                                         interrupt-controller;
 273                                         #interrupt-cells = <2>;
 274                                 };
 275
 276                                 gpio4: gpio@10015300 {
 277                                         compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
 278                                         reg = <0x10015300 0x100>;
 279                                         interrupts = <8>;
 280                                         gpio-controller;
 281                                         #gpio-cells = <2>;
 282                                         interrupt-controller;
 283                                         #interrupt-cells = <2>;
 284                                 };
 285
 286                                 gpio5: gpio@10015400 {
 287                                         compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
 288                                         reg = <0x10015400 0x100>;
 289                                         interrupts = <8>;
 290                                         gpio-controller;
 291                                         #gpio-cells = <2>;
 292                                         interrupt-controller;
 293                                         #interrupt-cells = <2>;
 294                                 };
 295
 296                                 gpio6: gpio@10015500 {
 297                                         compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
 298                                         reg = <0x10015500 0x100>;
 299                                         interrupts = <8>;
 300                                         gpio-controller;
 301                                         #gpio-cells = <2>;
 302                                         interrupt-controller;
 303                                         #interrupt-cells = <2>;
 304                                 };
 305                         };
 306
 307                         audmux: audmux@10016000 {
 308                                 compatible = "fsl,imx27-audmux", "fsl,imx21-audmux";
 309                                 reg = <0x10016000 0x1000>;
 310                                 clocks = <&clks 0>;
 311                                 clock-names = "audmux";
 312                                 status = "disabled";
 313                         };
 314
 315                         cspi3: cspi@10017000 {
 316                                 #address-cells = <1>;
 317                                 #size-cells = <0>;
 318                                 compatible = "fsl,imx27-cspi";
 319                                 reg = <0x10017000 0x1000>;
 320                                 interrupts = <6>;
 321                                 clocks = <&clks 51>, <&clks 60>;
 322                                 clock-names = "ipg", "per";
 323                                 status = "disabled";
 324                         };
 325
 326                         gpt4: timer@10019000 {
 327                                 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
 328                                 reg = <0x10019000 0x1000>;
 329                                 interrupts = <4>;
 330                                 clocks = <&clks 43>, <&clks 61>;
 331                                 clock-names = "ipg", "per";
 332                         };
 333
 334                         gpt5: timer@1001a000 {
 335                                 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
 336                                 reg = <0x1001a000 0x1000>;
 337                                 interrupts = <3>;
 338                                 clocks = <&clks 42>, <&clks 61>;
 339                                 clock-names = "ipg", "per";
 340                         };
 341
 342                         uart5: serial@1001b000 {
 343                                 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
 344                                 reg = <0x1001b000 0x1000>;
 345                                 interrupts = <49>;
 346                                 clocks = <&clks 77>, <&clks 61>;
 347                                 clock-names = "ipg", "per";
 348                                 status = "disabled";
 349                         };
 350
 351                         uart6: serial@1001c000 {
 352                                 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
 353                                 reg = <0x1001c000 0x1000>;
 354                                 interrupts = <48>;
 355                                 clocks = <&clks 78>, <&clks 61>;
 356                                 clock-names = "ipg", "per";
 357                                 status = "disabled";
 358                         };
 359
 360                         i2c2: i2c@1001d000 {
 361                                 #address-cells = <1>;
 362                                 #size-cells = <0>;
 363                                 compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
 364                                 reg = <0x1001d000 0x1000>;
 365                                 interrupts = <1>;
 366                                 clocks = <&clks 39>;
 367                                 status = "disabled";
 368                         };
 369
 370                         sdhci3: sdhci@1001e000 {
 371                                 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
 372                                 reg = <0x1001e000 0x1000>;
 373                                 interrupts = <9>;
 374                                 clocks = <&clks 28>, <&clks 60>;
 375                                 clock-names = "ipg", "per";
 376                                 dmas = <&dma 36>;
 377                                 dma-names = "rx-tx";
 378                                 status = "disabled";
 379                         };
 380
 381                         gpt6: timer@1001f000 {
 382                                 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
 383                                 reg = <0x1001f000 0x1000>;
 384                                 interrupts = <2>;
 385                                 clocks = <&clks 41>, <&clks 61>;
 386                                 clock-names = "ipg", "per";
 387                         };
 388                 };
 389
 390                 aipi@10020000 { /* AIPI2 */
 391                         compatible = "fsl,aipi-bus", "simple-bus";
 392                         #address-cells = <1>;
 393                         #size-cells = <1>;
 394                         reg = <0x10020000 0x20000>;
 395                         ranges;
 396
 397                         fb: fb@10021000 {
 398                                 compatible = "fsl,imx27-fb", "fsl,imx21-fb";
 399                                 interrupts = <61>;
 400                                 reg = <0x10021000 0x1000>;
 401                                 clocks = <&clks 36>, <&clks 65>, <&clks 59>;
 402                                 clock-names = "ipg", "ahb", "per";
 403                                 status = "disabled";
 404                         };
 405
 406                         coda: coda@10023000 {
 407                                 compatible = "fsl,imx27-vpu";
 408                                 reg = <0x10023000 0x0200>;
 409                                 interrupts = <53>;
 410                                 clocks = <&clks 57>, <&clks 66>;
 411                                 clock-names = "per", "ahb";
 412                                 iram = <&iram>;
 413                         };
 414
 415                         sahara2: sahara@10025000 {
 416                                 compatible = "fsl,imx27-sahara";
 417                                 reg = <0x10025000 0x1000>;
 418                                 interrupts = <59>;
 419                                 clocks = <&clks 32>, <&clks 64>;
 420                                 clock-names = "ipg", "ahb";
 421                         };
 422
 423                         clks: ccm@10027000{
 424                                 compatible = "fsl,imx27-ccm";
 425                                 reg = <0x10027000 0x1000>;
 426                                 #clock-cells = <1>;
 427                         };
 428
 429                         iim: iim@10028000 {
 430                                 compatible = "fsl,imx27-iim";
 431                                 reg = <0x10028000 0x1000>;
 432                                 interrupts = <62>;
 433                                 clocks = <&clks 38>;
 434                         };
 435
 436                         fec: ethernet@1002b000 {
 437                                 compatible = "fsl,imx27-fec";
 438                                 reg = <0x1002b000 0x4000>;
 439                                 interrupts = <50>;
 440                                 clocks = <&clks 48>, <&clks 67>;
 441                                 clock-names = "ipg", "ahb";
 442                                 status = "disabled";
 443                         };
 444                 };
 445
 446                 nfc: nand@d8000000 {
 447                         #address-cells = <1>;
 448                         #size-cells = <1>;
 449                         compatible = "fsl,imx27-nand";
 450                         reg = <0xd8000000 0x1000>;
 451                         interrupts = <29>;
 452                         clocks = <&clks 54>;
 453                         status = "disabled";
 454                 };
 455
 456                 weim: weim@d8002000 {
 457                         #address-cells = <2>;
 458                         #size-cells = <1>;
 459                         compatible = "fsl,imx27-weim";
 460                         reg = <0xd8002000 0x1000>;
 461                         clocks = <&clks 0>;
 462                         ranges = <
 463                                 0 0 0xc0000000 0x08000000
 464                                 1 0 0xc8000000 0x08000000
 465                                 2 0 0xd0000000 0x02000000
 466                                 3 0 0xd2000000 0x02000000
 467                                 4 0 0xd4000000 0x02000000
 468                                 5 0 0xd6000000 0x02000000
 469                         >;
 470                         status = "disabled";
 471                 };
 472
 473                 iram: iram@ffff4c00 {
 474                         compatible = "mmio-sram";
 475                         reg = <0xffff4c00 0xb400>;
 476                 };
 477         };
 478 };