2 * Copyright 2012 Sascha Hauer, Pengutronix
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
12 #include "skeleton.dtsi"
33 avic: avic-interrupt-controller@e0000000 {
34 compatible = "fsl,imx27-avic", "fsl,avic";
36 #interrupt-cells = <1>;
37 reg = <0x10040000 0x1000>;
45 compatible = "fsl,imx-osc26m", "fixed-clock";
46 clock-frequency = <26000000>;
53 compatible = "simple-bus";
54 interrupt-parent = <&avic>;
57 aipi@10000000 { /* AIPI1 */
58 compatible = "fsl,aipi-bus", "simple-bus";
61 reg = <0x10000000 0x20000>;
65 compatible = "fsl,imx27-dma";
66 reg = <0x10001000 0x1000>;
68 clocks = <&clks 50>, <&clks 70>;
69 clock-names = "ipg", "ahb";
75 compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
76 reg = <0x10002000 0x1000>;
81 gpt1: timer@10003000 {
82 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
83 reg = <0x10003000 0x1000>;
85 clocks = <&clks 46>, <&clks 61>;
86 clock-names = "ipg", "per";
89 gpt2: timer@10004000 {
90 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
91 reg = <0x10004000 0x1000>;
93 clocks = <&clks 45>, <&clks 61>;
94 clock-names = "ipg", "per";
97 gpt3: timer@10005000 {
98 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
99 reg = <0x10005000 0x1000>;
101 clocks = <&clks 44>, <&clks 61>;
102 clock-names = "ipg", "per";
106 compatible = "fsl,imx27-pwm";
107 reg = <0x10006000 0x1000>;
109 clocks = <&clks 34>, <&clks 61>;
110 clock-names = "ipg", "per";
113 uart1: serial@1000a000 {
114 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
115 reg = <0x1000a000 0x1000>;
117 clocks = <&clks 81>, <&clks 61>;
118 clock-names = "ipg", "per";
122 uart2: serial@1000b000 {
123 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
124 reg = <0x1000b000 0x1000>;
126 clocks = <&clks 80>, <&clks 61>;
127 clock-names = "ipg", "per";
131 uart3: serial@1000c000 {
132 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
133 reg = <0x1000c000 0x1000>;
135 clocks = <&clks 79>, <&clks 61>;
136 clock-names = "ipg", "per";
140 uart4: serial@1000d000 {
141 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
142 reg = <0x1000d000 0x1000>;
144 clocks = <&clks 78>, <&clks 61>;
145 clock-names = "ipg", "per";
149 cspi1: cspi@1000e000 {
150 #address-cells = <1>;
152 compatible = "fsl,imx27-cspi";
153 reg = <0x1000e000 0x1000>;
155 clocks = <&clks 53>, <&clks 53>;
156 clock-names = "ipg", "per";
160 cspi2: cspi@1000f000 {
161 #address-cells = <1>;
163 compatible = "fsl,imx27-cspi";
164 reg = <0x1000f000 0x1000>;
166 clocks = <&clks 52>, <&clks 52>;
167 clock-names = "ipg", "per";
172 #address-cells = <1>;
174 compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
175 reg = <0x10012000 0x1000>;
181 sdhci1: sdhci@10013000 {
182 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
183 reg = <0x10013000 0x1000>;
185 clocks = <&clks 30>, <&clks 60>;
186 clock-names = "ipg", "per";
192 sdhci2: sdhci@10014000 {
193 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
194 reg = <0x10014000 0x1000>;
196 clocks = <&clks 29>, <&clks 60>;
197 clock-names = "ipg", "per";
203 gpio1: gpio@10015000 {
204 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
205 reg = <0x10015000 0x100>;
209 interrupt-controller;
210 #interrupt-cells = <2>;
213 gpio2: gpio@10015100 {
214 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
215 reg = <0x10015100 0x100>;
219 interrupt-controller;
220 #interrupt-cells = <2>;
223 gpio3: gpio@10015200 {
224 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
225 reg = <0x10015200 0x100>;
229 interrupt-controller;
230 #interrupt-cells = <2>;
233 gpio4: gpio@10015300 {
234 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
235 reg = <0x10015300 0x100>;
239 interrupt-controller;
240 #interrupt-cells = <2>;
243 gpio5: gpio@10015400 {
244 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
245 reg = <0x10015400 0x100>;
249 interrupt-controller;
250 #interrupt-cells = <2>;
253 gpio6: gpio@10015500 {
254 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
255 reg = <0x10015500 0x100>;
259 interrupt-controller;
260 #interrupt-cells = <2>;
263 cspi3: cspi@10017000 {
264 #address-cells = <1>;
266 compatible = "fsl,imx27-cspi";
267 reg = <0x10017000 0x1000>;
269 clocks = <&clks 51>, <&clks 51>;
270 clock-names = "ipg", "per";
274 gpt4: timer@10019000 {
275 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
276 reg = <0x10019000 0x1000>;
278 clocks = <&clks 43>, <&clks 61>;
279 clock-names = "ipg", "per";
282 gpt5: timer@1001a000 {
283 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
284 reg = <0x1001a000 0x1000>;
286 clocks = <&clks 42>, <&clks 61>;
287 clock-names = "ipg", "per";
290 uart5: serial@1001b000 {
291 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
292 reg = <0x1001b000 0x1000>;
294 clocks = <&clks 77>, <&clks 61>;
295 clock-names = "ipg", "per";
299 uart6: serial@1001c000 {
300 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
301 reg = <0x1001c000 0x1000>;
303 clocks = <&clks 78>, <&clks 61>;
304 clock-names = "ipg", "per";
309 #address-cells = <1>;
311 compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
312 reg = <0x1001d000 0x1000>;
318 sdhci3: sdhci@1001e000 {
319 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
320 reg = <0x1001e000 0x1000>;
322 clocks = <&clks 28>, <&clks 60>;
323 clock-names = "ipg", "per";
329 gpt6: timer@1001f000 {
330 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
331 reg = <0x1001f000 0x1000>;
333 clocks = <&clks 41>, <&clks 61>;
334 clock-names = "ipg", "per";
338 aipi@10020000 { /* AIPI2 */
339 compatible = "fsl,aipi-bus", "simple-bus";
340 #address-cells = <1>;
342 reg = <0x10020000 0x20000>;
345 coda: coda@10023000 {
346 compatible = "fsl,imx27-vpu";
347 reg = <0x10023000 0x0200>;
349 clocks = <&clks 57>, <&clks 66>;
350 clock-names = "per", "ahb";
355 compatible = "fsl,imx27-ccm";
356 reg = <0x10027000 0x1000>;
360 fec: ethernet@1002b000 {
361 compatible = "fsl,imx27-fec";
362 reg = <0x1002b000 0x4000>;
364 clocks = <&clks 48>, <&clks 67>, <&clks 0>;
365 clock-names = "ipg", "ahb", "ptp";
370 iram: iram@ffff4c00 {
371 compatible = "mmio-sram";
372 reg = <0xffff4c00 0xb400>;
376 #address-cells = <1>;
378 compatible = "fsl,imx27-nand";
379 reg = <0xd8000000 0x1000>;