2 * Copyright 2012 Freescale Semiconductor, Inc.
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
12 /include/ "skeleton.dtsi"
15 interrupt-parent = <&icoll>;
39 compatible = "arm,arm926ej-s";
45 compatible = "simple-bus";
48 reg = <0x80000000 0x80000>;
52 compatible = "simple-bus";
55 reg = <0x80000000 0x3c900>;
58 icoll: interrupt-controller@80000000 {
59 compatible = "fsl,imx28-icoll", "fsl,icoll";
61 #interrupt-cells = <1>;
62 reg = <0x80000000 0x2000>;
66 reg = <0x80002000 0x2000>;
68 dmas = <&dma_apbh 12>;
73 dma_apbh: dma-apbh@80004000 {
74 compatible = "fsl,imx28-dma-apbh";
75 reg = <0x80004000 0x2000>;
76 interrupts = <82 83 84 85
80 interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3",
81 "gpmi0", "gmpi1", "gpmi2", "gmpi3",
82 "gpmi4", "gmpi5", "gpmi6", "gmpi7",
83 "hsadc", "lcdif", "empty", "empty";
90 reg = <0x80006000 0x800>;
96 compatible = "fsl,imx28-gpmi-nand";
99 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
100 reg-names = "gpmi-nand", "bch";
101 interrupts = <88>, <41>;
102 interrupt-names = "gpmi-dma", "bch";
104 clock-names = "gpmi_io";
105 dmas = <&dma_apbh 4>;
107 fsl,gpmi-dma-channel = <4>;
112 #address-cells = <1>;
114 reg = <0x80010000 0x2000>;
115 interrupts = <96 82>;
117 dmas = <&dma_apbh 0>;
119 fsl,ssp-dma-channel = <0>;
124 #address-cells = <1>;
126 reg = <0x80012000 0x2000>;
127 interrupts = <97 83>;
129 dmas = <&dma_apbh 1>;
131 fsl,ssp-dma-channel = <1>;
136 #address-cells = <1>;
138 reg = <0x80014000 0x2000>;
139 interrupts = <98 84>;
141 dmas = <&dma_apbh 2>;
143 fsl,ssp-dma-channel = <2>;
148 #address-cells = <1>;
150 reg = <0x80016000 0x2000>;
151 interrupts = <99 85>;
153 dmas = <&dma_apbh 3>;
155 fsl,ssp-dma-channel = <3>;
160 #address-cells = <1>;
162 compatible = "fsl,imx28-pinctrl", "simple-bus";
163 reg = <0x80018000 0x2000>;
166 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
170 interrupt-controller;
171 #interrupt-cells = <2>;
175 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
179 interrupt-controller;
180 #interrupt-cells = <2>;
184 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
188 interrupt-controller;
189 #interrupt-cells = <2>;
193 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
197 interrupt-controller;
198 #interrupt-cells = <2>;
202 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
206 interrupt-controller;
207 #interrupt-cells = <2>;
210 duart_pins_a: duart@0 {
213 0x3102 /* MX28_PAD_PWM0__DUART_RX */
214 0x3112 /* MX28_PAD_PWM1__DUART_TX */
216 fsl,drive-strength = <0>;
221 duart_pins_b: duart@1 {
224 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */
225 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */
227 fsl,drive-strength = <0>;
232 duart_4pins_a: duart-4pins@0 {
235 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */
236 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */
237 0x3002 /* MX28_PAD_AUART0_RX__DUART_CTS */
238 0x3012 /* MX28_PAD_AUART0_TX__DUART_RTS */
240 fsl,drive-strength = <0>;
245 gpmi_pins_a: gpmi-nand@0 {
248 0x0000 /* MX28_PAD_GPMI_D00__GPMI_D0 */
249 0x0010 /* MX28_PAD_GPMI_D01__GPMI_D1 */
250 0x0020 /* MX28_PAD_GPMI_D02__GPMI_D2 */
251 0x0030 /* MX28_PAD_GPMI_D03__GPMI_D3 */
252 0x0040 /* MX28_PAD_GPMI_D04__GPMI_D4 */
253 0x0050 /* MX28_PAD_GPMI_D05__GPMI_D5 */
254 0x0060 /* MX28_PAD_GPMI_D06__GPMI_D6 */
255 0x0070 /* MX28_PAD_GPMI_D07__GPMI_D7 */
256 0x0100 /* MX28_PAD_GPMI_CE0N__GPMI_CE0N */
257 0x0140 /* MX28_PAD_GPMI_RDY0__GPMI_READY0 */
258 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */
259 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */
260 0x01a0 /* MX28_PAD_GPMI_ALE__GPMI_ALE */
261 0x01b0 /* MX28_PAD_GPMI_CLE__GPMI_CLE */
262 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */
264 fsl,drive-strength = <0>;
269 gpmi_status_cfg: gpmi-status-cfg {
271 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */
272 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */
273 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */
275 fsl,drive-strength = <2>;
278 auart0_pins_a: auart0@0 {
281 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */
282 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */
283 0x3020 /* MX28_PAD_AUART0_CTS__AUART0_CTS */
284 0x3030 /* MX28_PAD_AUART0_RTS__AUART0_RTS */
286 fsl,drive-strength = <0>;
291 auart0_2pins_a: auart0-2pins@0 {
294 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */
295 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */
297 fsl,drive-strength = <0>;
302 auart1_pins_a: auart1@0 {
305 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */
306 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */
307 0x3060 /* MX28_PAD_AUART1_CTS__AUART1_CTS */
308 0x3070 /* MX28_PAD_AUART1_RTS__AUART1_RTS */
310 fsl,drive-strength = <0>;
315 auart1_2pins_a: auart1-2pins@0 {
318 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */
319 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */
321 fsl,drive-strength = <0>;
326 auart2_2pins_a: auart2-2pins@0 {
329 0x2101 /* MX28_PAD_SSP2_SCK__AUART2_RX */
330 0x2111 /* MX28_PAD_SSP2_MOSI__AUART2_TX */
332 fsl,drive-strength = <0>;
337 auart2_2pins_b: auart2-2pins@1 {
340 0x3080 /* MX28_PAD_AUART2_RX__AUART2_RX */
341 0x3090 /* MX28_PAD_AUART2_TX__AUART2_TX */
343 fsl,drive-strength = <0>;
348 auart3_pins_a: auart3@0 {
351 0x30c0 /* MX28_PAD_AUART3_RX__AUART3_RX */
352 0x30d0 /* MX28_PAD_AUART3_TX__AUART3_TX */
353 0x30e0 /* MX28_PAD_AUART3_CTS__AUART3_CTS */
354 0x30f0 /* MX28_PAD_AUART3_RTS__AUART3_RTS */
356 fsl,drive-strength = <0>;
361 auart3_2pins_a: auart3-2pins@0 {
364 0x2121 /* MX28_PAD_SSP2_MISO__AUART3_RX */
365 0x2131 /* MX28_PAD_SSP2_SS0__AUART3_TX */
367 fsl,drive-strength = <0>;
372 auart3_2pins_b: auart3-2pins@1 {
375 0x30c0 /* MX28_PAD_AUART3_RX__AUART3_RX */
376 0x30d0 /* MX28_PAD_AUART3_TX__AUART3_TX */
378 fsl,drive-strength = <0>;
383 auart4_2pins_a: auart4@0 {
386 0x2181 /* MX28_PAD_SSP3_SCK__AUART4_TX */
387 0x2191 /* MX28_PAD_SSP3_MOSI__AUART4_RX */
389 fsl,drive-strength = <0>;
394 mac0_pins_a: mac0@0 {
397 0x4000 /* MX28_PAD_ENET0_MDC__ENET0_MDC */
398 0x4010 /* MX28_PAD_ENET0_MDIO__ENET0_MDIO */
399 0x4020 /* MX28_PAD_ENET0_RX_EN__ENET0_RX_EN */
400 0x4030 /* MX28_PAD_ENET0_RXD0__ENET0_RXD0 */
401 0x4040 /* MX28_PAD_ENET0_RXD1__ENET0_RXD1 */
402 0x4060 /* MX28_PAD_ENET0_TX_EN__ENET0_TX_EN */
403 0x4070 /* MX28_PAD_ENET0_TXD0__ENET0_TXD0 */
404 0x4080 /* MX28_PAD_ENET0_TXD1__ENET0_TXD1 */
405 0x4100 /* MX28_PAD_ENET_CLK__CLKCTRL_ENET */
407 fsl,drive-strength = <1>;
412 mac1_pins_a: mac1@0 {
415 0x40f1 /* MX28_PAD_ENET0_CRS__ENET1_RX_EN */
416 0x4091 /* MX28_PAD_ENET0_RXD2__ENET1_RXD0 */
417 0x40a1 /* MX28_PAD_ENET0_RXD3__ENET1_RXD1 */
418 0x40e1 /* MX28_PAD_ENET0_COL__ENET1_TX_EN */
419 0x40b1 /* MX28_PAD_ENET0_TXD2__ENET1_TXD0 */
420 0x40c1 /* MX28_PAD_ENET0_TXD3__ENET1_TXD1 */
422 fsl,drive-strength = <1>;
427 mmc0_8bit_pins_a: mmc0-8bit@0 {
430 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */
431 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */
432 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */
433 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */
434 0x2040 /* MX28_PAD_SSP0_DATA4__SSP0_D4 */
435 0x2050 /* MX28_PAD_SSP0_DATA5__SSP0_D5 */
436 0x2060 /* MX28_PAD_SSP0_DATA6__SSP0_D6 */
437 0x2070 /* MX28_PAD_SSP0_DATA7__SSP0_D7 */
438 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */
439 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
440 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
442 fsl,drive-strength = <1>;
447 mmc0_4bit_pins_a: mmc0-4bit@0 {
450 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */
451 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */
452 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */
453 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */
454 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */
455 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
456 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
458 fsl,drive-strength = <1>;
463 mmc0_cd_cfg: mmc0-cd-cfg {
465 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
470 mmc0_sck_cfg: mmc0-sck-cfg {
472 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
474 fsl,drive-strength = <2>;
478 i2c0_pins_a: i2c0@0 {
481 0x3180 /* MX28_PAD_I2C0_SCL__I2C0_SCL */
482 0x3190 /* MX28_PAD_I2C0_SDA__I2C0_SDA */
484 fsl,drive-strength = <1>;
489 i2c0_pins_b: i2c0@1 {
492 0x3001 /* MX28_PAD_AUART0_RX__I2C0_SCL */
493 0x3011 /* MX28_PAD_AUART0_TX__I2C0_SDA */
495 fsl,drive-strength = <1>;
500 i2c1_pins_a: i2c1@0 {
503 0x3101 /* MX28_PAD_PWM0__I2C1_SCL */
504 0x3111 /* MX28_PAD_PWM1__I2C1_SDA */
506 fsl,drive-strength = <1>;
511 saif0_pins_a: saif0@0 {
514 0x3140 /* MX28_PAD_SAIF0_MCLK__SAIF0_MCLK */
515 0x3150 /* MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK */
516 0x3160 /* MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK */
517 0x3170 /* MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 */
519 fsl,drive-strength = <2>;
524 saif1_pins_a: saif1@0 {
527 0x31a0 /* MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 */
529 fsl,drive-strength = <2>;
534 pwm0_pins_a: pwm0@0 {
537 0x3100 /* MX28_PAD_PWM0__PWM_0 */
539 fsl,drive-strength = <0>;
544 pwm2_pins_a: pwm2@0 {
547 0x3120 /* MX28_PAD_PWM2__PWM_2 */
549 fsl,drive-strength = <0>;
554 pwm3_pins_a: pwm3@0 {
557 0x31c0 /* MX28_PAD_PWM3__PWM_3 */
559 fsl,drive-strength = <0>;
564 pwm3_pins_b: pwm3@1 {
567 0x3141 /* MX28_PAD_SAIF0_MCLK__PWM3 */
569 fsl,drive-strength = <0>;
574 pwm4_pins_a: pwm4@0 {
577 0x31d0 /* MX28_PAD_PWM4__PWM_4 */
579 fsl,drive-strength = <0>;
584 lcdif_24bit_pins_a: lcdif-24bit@0 {
587 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */
588 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */
589 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */
590 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */
591 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */
592 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */
593 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */
594 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */
595 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */
596 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */
597 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */
598 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */
599 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */
600 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */
601 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */
602 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */
603 0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */
604 0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */
605 0x1120 /* MX28_PAD_LCD_D18__LCD_D18 */
606 0x1130 /* MX28_PAD_LCD_D19__LCD_D19 */
607 0x1140 /* MX28_PAD_LCD_D20__LCD_D20 */
608 0x1150 /* MX28_PAD_LCD_D21__LCD_D21 */
609 0x1160 /* MX28_PAD_LCD_D22__LCD_D22 */
610 0x1170 /* MX28_PAD_LCD_D23__LCD_D23 */
612 fsl,drive-strength = <0>;
617 lcdif_16bit_pins_a: lcdif-16bit@0 {
620 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */
621 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */
622 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */
623 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */
624 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */
625 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */
626 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */
627 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */
628 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */
629 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */
630 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */
631 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */
632 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */
633 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */
634 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */
635 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */
637 fsl,drive-strength = <0>;
642 can0_pins_a: can0@0 {
645 0x0161 /* MX28_PAD_GPMI_RDY2__CAN0_TX */
646 0x0171 /* MX28_PAD_GPMI_RDY3__CAN0_RX */
648 fsl,drive-strength = <0>;
653 can1_pins_a: can1@0 {
656 0x0121 /* MX28_PAD_GPMI_CE2N__CAN1_TX */
657 0x0131 /* MX28_PAD_GPMI_CE3N__CAN1_RX */
659 fsl,drive-strength = <0>;
664 spi2_pins_a: spi2@0 {
667 0x2100 /* MX28_PAD_SSP2_SCK__SSP2_SCK */
668 0x2110 /* MX28_PAD_SSP2_MOSI__SSP2_CMD */
669 0x2120 /* MX28_PAD_SSP2_MISO__SSP2_D0 */
670 0x2130 /* MX28_PAD_SSP2_SS0__SSP2_D3 */
672 fsl,drive-strength = <1>;
677 usbphy0_pins_a: usbphy0@0 {
680 0x2152 /* MX28_PAD_SSP2_SS2__USB0_OVERCURRENT */
682 fsl,drive-strength = <2>;
687 usbphy0_pins_b: usbphy0@1 {
690 0x3061 /* MX28_PAD_AUART1_CTS__USB0_OVERCURRENT */
692 fsl,drive-strength = <2>;
697 usbphy1_pins_a: usbphy1@0 {
700 0x2142 /* MX28_PAD_SSP2_SS1__USB1_OVERCURRENT */
702 fsl,drive-strength = <2>;
709 compatible = "fsl,imx28-digctl", "fsl,imx23-digctl";
710 reg = <0x8001c000 0x2000>;
716 reg = <0x80022000 0x2000>;
720 dma_apbx: dma-apbx@80024000 {
721 compatible = "fsl,imx28-dma-apbx";
722 reg = <0x80024000 0x2000>;
723 interrupts = <78 79 66 0
727 interrupt-names = "auart4-rx", "aurat4-tx", "spdif-tx", "empty",
728 "saif0", "saif1", "i2c0", "i2c1",
729 "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx",
730 "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx";
737 reg = <0x80028000 0x2000>;
738 interrupts = <52 53 54>;
743 reg = <0x8002a000 0x2000>;
749 compatible = "fsl,ocotp";
750 reg = <0x8002c000 0x2000>;
755 reg = <0x8002e000 0x2000>;
760 compatible = "fsl,imx28-lcdif";
761 reg = <0x80030000 0x2000>;
762 interrupts = <38 86>;
764 dmas = <&dma_apbh 13>;
770 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
771 reg = <0x80032000 0x2000>;
773 clocks = <&clks 58>, <&clks 58>;
774 clock-names = "ipg", "per";
779 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
780 reg = <0x80034000 0x2000>;
782 clocks = <&clks 59>, <&clks 59>;
783 clock-names = "ipg", "per";
788 reg = <0x8003c000 0x200>;
792 simgpmisel@8003c200 {
793 reg = <0x8003c200 0x100>;
798 reg = <0x8003c300 0x100>;
803 reg = <0x8003c400 0x100>;
808 reg = <0x8003c500 0x100>;
813 reg = <0x8003c700 0x100>;
818 reg = <0x8003c800 0x100>;
824 compatible = "simple-bus";
825 #address-cells = <1>;
827 reg = <0x80040000 0x40000>;
830 clks: clkctrl@80040000 {
831 compatible = "fsl,imx28-clkctrl", "fsl,clkctrl";
832 reg = <0x80040000 0x2000>;
836 saif0: saif@80042000 {
837 compatible = "fsl,imx28-saif";
838 reg = <0x80042000 0x2000>;
839 interrupts = <59 80>;
841 dmas = <&dma_apbx 4>;
843 fsl,saif-dma-channel = <4>;
848 reg = <0x80044000 0x2000>;
852 saif1: saif@80046000 {
853 compatible = "fsl,imx28-saif";
854 reg = <0x80046000 0x2000>;
855 interrupts = <58 81>;
857 dmas = <&dma_apbx 5>;
859 fsl,saif-dma-channel = <5>;
864 compatible = "fsl,imx28-lradc";
865 reg = <0x80050000 0x2000>;
866 interrupts = <10 14 15 16 17 18 19
872 reg = <0x80054000 0x2000>;
873 interrupts = <45 66>;
874 dmas = <&dma_apbx 2>;
880 compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
881 reg = <0x80056000 0x2000>;
886 #address-cells = <1>;
888 compatible = "fsl,imx28-i2c";
889 reg = <0x80058000 0x2000>;
890 interrupts = <111 68>;
891 clock-frequency = <100000>;
892 dmas = <&dma_apbx 6>;
894 fsl,i2c-dma-channel = <6>;
899 #address-cells = <1>;
901 compatible = "fsl,imx28-i2c";
902 reg = <0x8005a000 0x2000>;
903 interrupts = <110 69>;
904 clock-frequency = <100000>;
905 dmas = <&dma_apbx 7>;
907 fsl,i2c-dma-channel = <7>;
912 compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
913 reg = <0x80064000 0x2000>;
916 fsl,pwm-number = <8>;
921 compatible = "fsl,imx28-timrot", "fsl,timrot";
922 reg = <0x80068000 0x2000>;
923 interrupts = <48 49 50 51>;
927 auart0: serial@8006a000 {
928 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
929 reg = <0x8006a000 0x2000>;
930 interrupts = <112 70 71>;
931 dmas = <&dma_apbx 8>, <&dma_apbx 9>;
932 dma-names = "rx", "tx";
933 fsl,auart-dma-channel = <8 9>;
938 auart1: serial@8006c000 {
939 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
940 reg = <0x8006c000 0x2000>;
941 interrupts = <113 72 73>;
942 dmas = <&dma_apbx 10>, <&dma_apbx 11>;
943 dma-names = "rx", "tx";
948 auart2: serial@8006e000 {
949 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
950 reg = <0x8006e000 0x2000>;
951 interrupts = <114 74 75>;
952 dmas = <&dma_apbx 12>, <&dma_apbx 13>;
953 dma-names = "rx", "tx";
958 auart3: serial@80070000 {
959 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
960 reg = <0x80070000 0x2000>;
961 interrupts = <115 76 77>;
962 dmas = <&dma_apbx 14>, <&dma_apbx 15>;
963 dma-names = "rx", "tx";
968 auart4: serial@80072000 {
969 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
970 reg = <0x80072000 0x2000>;
971 interrupts = <116 78 79>;
972 dmas = <&dma_apbx 0>, <&dma_apbx 1>;
973 dma-names = "rx", "tx";
978 duart: serial@80074000 {
979 compatible = "arm,pl011", "arm,primecell";
980 reg = <0x80074000 0x1000>;
982 clocks = <&clks 45>, <&clks 26>;
983 clock-names = "uart", "apb_pclk";
987 usbphy0: usbphy@8007c000 {
988 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
989 reg = <0x8007c000 0x2000>;
994 usbphy1: usbphy@8007e000 {
995 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
996 reg = <0x8007e000 0x2000>;
1004 compatible = "simple-bus";
1005 #address-cells = <1>;
1007 reg = <0x80080000 0x80000>;
1010 usb0: usb@80080000 {
1011 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
1012 reg = <0x80080000 0x10000>;
1014 clocks = <&clks 60>;
1015 fsl,usbphy = <&usbphy0>;
1016 status = "disabled";
1019 usb1: usb@80090000 {
1020 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
1021 reg = <0x80090000 0x10000>;
1023 clocks = <&clks 61>;
1024 fsl,usbphy = <&usbphy1>;
1025 status = "disabled";
1029 reg = <0x800c0000 0x10000>;
1030 status = "disabled";
1033 mac0: ethernet@800f0000 {
1034 compatible = "fsl,imx28-fec";
1035 reg = <0x800f0000 0x4000>;
1037 clocks = <&clks 57>, <&clks 57>, <&clks 64>;
1038 clock-names = "ipg", "ahb", "enet_out";
1039 status = "disabled";
1042 mac1: ethernet@800f4000 {
1043 compatible = "fsl,imx28-fec";
1044 reg = <0x800f4000 0x4000>;
1046 clocks = <&clks 57>, <&clks 57>;
1047 clock-names = "ipg", "ahb";
1048 status = "disabled";
1052 reg = <0x800f8000 0x8000>;
1053 status = "disabled";