2 * Copyright 2013 Greg Ungerer <gerg@uclinux.org>
3 * Copyright 2011 Freescale Semiconductor, Inc.
4 * Copyright 2011 Linaro Ltd.
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
14 #include "skeleton.dtsi"
15 #include "imx50-pinfunc.h"
16 #include <dt-bindings/clock/imx5-clock.h>
38 compatible = "arm,cortex-a8";
43 tzic: tz-interrupt-controller@0fffc000 {
44 compatible = "fsl,imx50-tzic", "fsl,imx53-tzic", "fsl,tzic";
46 #interrupt-cells = <1>;
47 reg = <0x0fffc000 0x4000>;
55 compatible = "fsl,imx-ckil", "fixed-clock";
56 clock-frequency = <32768>;
60 compatible = "fsl,imx-ckih1", "fixed-clock";
61 clock-frequency = <22579200>;
65 compatible = "fsl,imx-ckih2", "fixed-clock";
66 clock-frequency = <0>;
70 compatible = "fsl,imx-osc", "fixed-clock";
71 clock-frequency = <24000000>;
78 compatible = "simple-bus";
79 interrupt-parent = <&tzic>;
82 aips@50000000 { /* AIPS1 */
83 compatible = "fsl,aips-bus", "simple-bus";
86 reg = <0x50000000 0x10000000>;
90 compatible = "fsl,spba-bus", "simple-bus";
93 reg = <0x50000000 0x40000>;
96 esdhc1: esdhc@50004000 {
97 compatible = "fsl,imx50-esdhc";
98 reg = <0x50004000 0x4000>;
100 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
101 <&clks IMX5_CLK_DUMMY>,
102 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
103 clock-names = "ipg", "ahb", "per";
108 esdhc2: esdhc@50008000 {
109 compatible = "fsl,imx50-esdhc";
110 reg = <0x50008000 0x4000>;
112 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
113 <&clks IMX5_CLK_DUMMY>,
114 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
115 clock-names = "ipg", "ahb", "per";
120 uart3: serial@5000c000 {
121 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
122 reg = <0x5000c000 0x4000>;
124 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
125 <&clks IMX5_CLK_UART3_PER_GATE>;
126 clock-names = "ipg", "per";
130 ecspi1: ecspi@50010000 {
131 #address-cells = <1>;
133 compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
134 reg = <0x50010000 0x4000>;
136 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
137 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
138 clock-names = "ipg", "per";
143 compatible = "fsl,imx50-ssi",
146 reg = <0x50014000 0x4000>;
148 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
149 fsl,fifo-depth = <15>;
150 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
154 esdhc3: esdhc@50020000 {
155 compatible = "fsl,imx50-esdhc";
156 reg = <0x50020000 0x4000>;
158 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
159 <&clks IMX5_CLK_DUMMY>,
160 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
161 clock-names = "ipg", "ahb", "per";
166 esdhc4: esdhc@50024000 {
167 compatible = "fsl,imx50-esdhc";
168 reg = <0x50024000 0x4000>;
170 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
171 <&clks IMX5_CLK_DUMMY>,
172 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
173 clock-names = "ipg", "ahb", "per";
179 usbotg: usb@53f80000 {
180 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
181 reg = <0x53f80000 0x0200>;
183 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
187 usbh1: usb@53f80200 {
188 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
189 reg = <0x53f80200 0x0200>;
191 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
195 usbh2: usb@53f80400 {
196 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
197 reg = <0x53f80400 0x0200>;
199 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
203 usbh3: usb@53f80600 {
204 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
205 reg = <0x53f80600 0x0200>;
207 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
211 gpio1: gpio@53f84000 {
212 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
213 reg = <0x53f84000 0x4000>;
214 interrupts = <50 51>;
217 interrupt-controller;
218 #interrupt-cells = <2>;
221 gpio2: gpio@53f88000 {
222 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
223 reg = <0x53f88000 0x4000>;
224 interrupts = <52 53>;
227 interrupt-controller;
228 #interrupt-cells = <2>;
231 gpio3: gpio@53f8c000 {
232 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
233 reg = <0x53f8c000 0x4000>;
234 interrupts = <54 55>;
237 interrupt-controller;
238 #interrupt-cells = <2>;
241 gpio4: gpio@53f90000 {
242 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
243 reg = <0x53f90000 0x4000>;
244 interrupts = <56 57>;
247 interrupt-controller;
248 #interrupt-cells = <2>;
251 wdog1: wdog@53f98000 {
252 compatible = "fsl,imx50-wdt", "fsl,imx21-wdt";
253 reg = <0x53f98000 0x4000>;
255 clocks = <&clks IMX5_CLK_DUMMY>;
258 gpt: timer@53fa0000 {
259 compatible = "fsl,imx50-gpt", "fsl,imx31-gpt";
260 reg = <0x53fa0000 0x4000>;
262 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
263 <&clks IMX5_CLK_GPT_HF_GATE>;
264 clock-names = "ipg", "per";
267 iomuxc: iomuxc@53fa8000 {
268 compatible = "fsl,imx50-iomuxc", "fsl,imx53-iomuxc";
269 reg = <0x53fa8000 0x4000>;
272 gpr: iomuxc-gpr@53fa8000 {
273 compatible = "fsl,imx50-iomuxc-gpr", "syscon";
274 reg = <0x53fa8000 0xc>;
279 compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
280 reg = <0x53fb4000 0x4000>;
281 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
282 <&clks IMX5_CLK_PWM1_HF_GATE>;
283 clock-names = "ipg", "per";
289 compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
290 reg = <0x53fb8000 0x4000>;
291 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
292 <&clks IMX5_CLK_PWM2_HF_GATE>;
293 clock-names = "ipg", "per";
297 uart1: serial@53fbc000 {
298 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
299 reg = <0x53fbc000 0x4000>;
301 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
302 <&clks IMX5_CLK_UART1_PER_GATE>;
303 clock-names = "ipg", "per";
307 uart2: serial@53fc0000 {
308 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
309 reg = <0x53fc0000 0x4000>;
311 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
312 <&clks IMX5_CLK_UART2_PER_GATE>;
313 clock-names = "ipg", "per";
318 compatible = "fsl,imx50-src", "fsl,imx51-src";
319 reg = <0x53fd0000 0x4000>;
324 compatible = "fsl,imx50-ccm";
325 reg = <0x53fd4000 0x4000>;
326 interrupts = <0 71 0x04 0 72 0x04>;
330 gpio5: gpio@53fdc000 {
331 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
332 reg = <0x53fdc000 0x4000>;
333 interrupts = <103 104>;
336 interrupt-controller;
337 #interrupt-cells = <2>;
340 gpio6: gpio@53fe0000 {
341 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
342 reg = <0x53fe0000 0x4000>;
343 interrupts = <105 106>;
346 interrupt-controller;
347 #interrupt-cells = <2>;
351 #address-cells = <1>;
353 compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
354 reg = <0x53fec000 0x4000>;
356 clocks = <&clks IMX5_CLK_I2C3_GATE>;
360 uart4: serial@53ff0000 {
361 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
362 reg = <0x53ff0000 0x4000>;
364 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
365 <&clks IMX5_CLK_UART4_PER_GATE>;
366 clock-names = "ipg", "per";
371 aips@60000000 { /* AIPS2 */
372 compatible = "fsl,aips-bus", "simple-bus";
373 #address-cells = <1>;
375 reg = <0x60000000 0x10000000>;
378 uart5: serial@63f90000 {
379 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
380 reg = <0x63f90000 0x4000>;
382 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
383 <&clks IMX5_CLK_UART5_PER_GATE>;
384 clock-names = "ipg", "per";
388 owire: owire@63fa4000 {
389 compatible = "fsl,imx50-owire", "fsl,imx21-owire";
390 reg = <0x63fa4000 0x4000>;
391 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
395 ecspi2: ecspi@63fac000 {
396 #address-cells = <1>;
398 compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
399 reg = <0x63fac000 0x4000>;
401 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
402 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
403 clock-names = "ipg", "per";
407 sdma: sdma@63fb0000 {
408 compatible = "fsl,imx50-sdma", "fsl,imx35-sdma";
409 reg = <0x63fb0000 0x4000>;
411 clocks = <&clks IMX5_CLK_SDMA_GATE>,
412 <&clks IMX5_CLK_SDMA_GATE>;
413 clock-names = "ipg", "ahb";
414 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin";
417 cspi: cspi@63fc0000 {
418 #address-cells = <1>;
420 compatible = "fsl,imx50-cspi", "fsl,imx35-cspi";
421 reg = <0x63fc0000 0x4000>;
423 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
424 <&clks IMX5_CLK_CSPI_IPG_GATE>;
425 clock-names = "ipg", "per";
430 #address-cells = <1>;
432 compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
433 reg = <0x63fc4000 0x4000>;
435 clocks = <&clks IMX5_CLK_I2C2_GATE>;
440 #address-cells = <1>;
442 compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
443 reg = <0x63fc8000 0x4000>;
445 clocks = <&clks IMX5_CLK_I2C1_GATE>;
450 compatible = "fsl,imx50-ssi", "fsl,imx51-ssi",
452 reg = <0x63fcc000 0x4000>;
454 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
455 fsl,fifo-depth = <15>;
456 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
460 audmux: audmux@63fd0000 {
461 compatible = "fsl,imx50-audmux", "fsl,imx31-audmux";
462 reg = <0x63fd0000 0x4000>;
466 fec: ethernet@63fec000 {
467 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
468 reg = <0x63fec000 0x4000>;
470 clocks = <&clks IMX5_CLK_FEC_GATE>,
471 <&clks IMX5_CLK_FEC_GATE>,
472 <&clks IMX5_CLK_FEC_GATE>;
473 clock-names = "ipg", "ahb", "ptp";