2 * Copyright 2013 Greg Ungerer <gerg@uclinux.org>
3 * Copyright 2011 Freescale Semiconductor, Inc.
4 * Copyright 2011 Linaro Ltd.
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
14 #include "skeleton.dtsi"
15 #include "imx50-pinfunc.h"
16 #include <dt-bindings/clock/imx5-clock.h>
39 compatible = "arm,cortex-a8";
44 tzic: tz-interrupt-controller@0fffc000 {
45 compatible = "fsl,imx50-tzic", "fsl,imx53-tzic", "fsl,tzic";
47 #interrupt-cells = <1>;
48 reg = <0x0fffc000 0x4000>;
56 compatible = "fsl,imx-ckil", "fixed-clock";
58 clock-frequency = <32768>;
62 compatible = "fsl,imx-ckih1", "fixed-clock";
64 clock-frequency = <22579200>;
68 compatible = "fsl,imx-ckih2", "fixed-clock";
70 clock-frequency = <0>;
74 compatible = "fsl,imx-osc", "fixed-clock";
76 clock-frequency = <24000000>;
83 compatible = "simple-bus";
84 interrupt-parent = <&tzic>;
87 aips@50000000 { /* AIPS1 */
88 compatible = "fsl,aips-bus", "simple-bus";
91 reg = <0x50000000 0x10000000>;
95 compatible = "fsl,spba-bus", "simple-bus";
98 reg = <0x50000000 0x40000>;
101 esdhc1: esdhc@50004000 {
102 compatible = "fsl,imx50-esdhc";
103 reg = <0x50004000 0x4000>;
105 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
106 <&clks IMX5_CLK_DUMMY>,
107 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
108 clock-names = "ipg", "ahb", "per";
113 esdhc2: esdhc@50008000 {
114 compatible = "fsl,imx50-esdhc";
115 reg = <0x50008000 0x4000>;
117 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
118 <&clks IMX5_CLK_DUMMY>,
119 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
120 clock-names = "ipg", "ahb", "per";
125 uart3: serial@5000c000 {
126 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
127 reg = <0x5000c000 0x4000>;
129 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
130 <&clks IMX5_CLK_UART3_PER_GATE>;
131 clock-names = "ipg", "per";
135 ecspi1: ecspi@50010000 {
136 #address-cells = <1>;
138 compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
139 reg = <0x50010000 0x4000>;
141 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
142 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
143 clock-names = "ipg", "per";
148 compatible = "fsl,imx50-ssi",
151 reg = <0x50014000 0x4000>;
153 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
154 fsl,fifo-depth = <15>;
155 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
159 esdhc3: esdhc@50020000 {
160 compatible = "fsl,imx50-esdhc";
161 reg = <0x50020000 0x4000>;
163 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
164 <&clks IMX5_CLK_DUMMY>,
165 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
166 clock-names = "ipg", "ahb", "per";
171 esdhc4: esdhc@50024000 {
172 compatible = "fsl,imx50-esdhc";
173 reg = <0x50024000 0x4000>;
175 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
176 <&clks IMX5_CLK_DUMMY>,
177 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
178 clock-names = "ipg", "ahb", "per";
184 usbotg: usb@53f80000 {
185 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
186 reg = <0x53f80000 0x0200>;
188 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
192 usbh1: usb@53f80200 {
193 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
194 reg = <0x53f80200 0x0200>;
196 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
200 usbh2: usb@53f80400 {
201 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
202 reg = <0x53f80400 0x0200>;
204 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
208 usbh3: usb@53f80600 {
209 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
210 reg = <0x53f80600 0x0200>;
212 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
216 gpio1: gpio@53f84000 {
217 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
218 reg = <0x53f84000 0x4000>;
219 interrupts = <50 51>;
222 interrupt-controller;
223 #interrupt-cells = <2>;
226 gpio2: gpio@53f88000 {
227 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
228 reg = <0x53f88000 0x4000>;
229 interrupts = <52 53>;
232 interrupt-controller;
233 #interrupt-cells = <2>;
236 gpio3: gpio@53f8c000 {
237 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
238 reg = <0x53f8c000 0x4000>;
239 interrupts = <54 55>;
242 interrupt-controller;
243 #interrupt-cells = <2>;
246 gpio4: gpio@53f90000 {
247 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
248 reg = <0x53f90000 0x4000>;
249 interrupts = <56 57>;
252 interrupt-controller;
253 #interrupt-cells = <2>;
256 wdog1: wdog@53f98000 {
257 compatible = "fsl,imx50-wdt", "fsl,imx21-wdt";
258 reg = <0x53f98000 0x4000>;
260 clocks = <&clks IMX5_CLK_DUMMY>;
263 gpt: timer@53fa0000 {
264 compatible = "fsl,imx50-gpt", "fsl,imx31-gpt";
265 reg = <0x53fa0000 0x4000>;
267 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
268 <&clks IMX5_CLK_GPT_HF_GATE>;
269 clock-names = "ipg", "per";
272 iomuxc: iomuxc@53fa8000 {
273 compatible = "fsl,imx50-iomuxc", "fsl,imx53-iomuxc";
274 reg = <0x53fa8000 0x4000>;
277 gpr: iomuxc-gpr@53fa8000 {
278 compatible = "fsl,imx50-iomuxc-gpr", "syscon";
279 reg = <0x53fa8000 0xc>;
284 compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
285 reg = <0x53fb4000 0x4000>;
286 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
287 <&clks IMX5_CLK_PWM1_HF_GATE>;
288 clock-names = "ipg", "per";
294 compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
295 reg = <0x53fb8000 0x4000>;
296 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
297 <&clks IMX5_CLK_PWM2_HF_GATE>;
298 clock-names = "ipg", "per";
302 uart1: serial@53fbc000 {
303 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
304 reg = <0x53fbc000 0x4000>;
306 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
307 <&clks IMX5_CLK_UART1_PER_GATE>;
308 clock-names = "ipg", "per";
312 uart2: serial@53fc0000 {
313 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
314 reg = <0x53fc0000 0x4000>;
316 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
317 <&clks IMX5_CLK_UART2_PER_GATE>;
318 clock-names = "ipg", "per";
323 compatible = "fsl,imx50-src", "fsl,imx51-src";
324 reg = <0x53fd0000 0x4000>;
329 compatible = "fsl,imx50-ccm";
330 reg = <0x53fd4000 0x4000>;
331 interrupts = <0 71 0x04 0 72 0x04>;
335 gpio5: gpio@53fdc000 {
336 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
337 reg = <0x53fdc000 0x4000>;
338 interrupts = <103 104>;
341 interrupt-controller;
342 #interrupt-cells = <2>;
345 gpio6: gpio@53fe0000 {
346 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
347 reg = <0x53fe0000 0x4000>;
348 interrupts = <105 106>;
351 interrupt-controller;
352 #interrupt-cells = <2>;
356 #address-cells = <1>;
358 compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
359 reg = <0x53fec000 0x4000>;
361 clocks = <&clks IMX5_CLK_I2C3_GATE>;
365 uart4: serial@53ff0000 {
366 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
367 reg = <0x53ff0000 0x4000>;
369 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
370 <&clks IMX5_CLK_UART4_PER_GATE>;
371 clock-names = "ipg", "per";
376 aips@60000000 { /* AIPS2 */
377 compatible = "fsl,aips-bus", "simple-bus";
378 #address-cells = <1>;
380 reg = <0x60000000 0x10000000>;
383 uart5: serial@63f90000 {
384 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
385 reg = <0x63f90000 0x4000>;
387 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
388 <&clks IMX5_CLK_UART5_PER_GATE>;
389 clock-names = "ipg", "per";
393 owire: owire@63fa4000 {
394 compatible = "fsl,imx50-owire", "fsl,imx21-owire";
395 reg = <0x63fa4000 0x4000>;
396 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
400 ecspi2: ecspi@63fac000 {
401 #address-cells = <1>;
403 compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
404 reg = <0x63fac000 0x4000>;
406 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
407 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
408 clock-names = "ipg", "per";
412 sdma: sdma@63fb0000 {
413 compatible = "fsl,imx50-sdma", "fsl,imx35-sdma";
414 reg = <0x63fb0000 0x4000>;
416 clocks = <&clks IMX5_CLK_SDMA_GATE>,
417 <&clks IMX5_CLK_SDMA_GATE>;
418 clock-names = "ipg", "ahb";
419 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin";
422 cspi: cspi@63fc0000 {
423 #address-cells = <1>;
425 compatible = "fsl,imx50-cspi", "fsl,imx35-cspi";
426 reg = <0x63fc0000 0x4000>;
428 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
429 <&clks IMX5_CLK_CSPI_IPG_GATE>;
430 clock-names = "ipg", "per";
435 #address-cells = <1>;
437 compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
438 reg = <0x63fc4000 0x4000>;
440 clocks = <&clks IMX5_CLK_I2C2_GATE>;
445 #address-cells = <1>;
447 compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
448 reg = <0x63fc8000 0x4000>;
450 clocks = <&clks IMX5_CLK_I2C1_GATE>;
455 compatible = "fsl,imx50-ssi", "fsl,imx51-ssi",
457 reg = <0x63fcc000 0x4000>;
459 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
460 fsl,fifo-depth = <15>;
461 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
465 audmux: audmux@63fd0000 {
466 compatible = "fsl,imx50-audmux", "fsl,imx31-audmux";
467 reg = <0x63fd0000 0x4000>;
471 fec: ethernet@63fec000 {
472 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
473 reg = <0x63fec000 0x4000>;
475 clocks = <&clks IMX5_CLK_FEC_GATE>,
476 <&clks IMX5_CLK_FEC_GATE>,
477 <&clks IMX5_CLK_FEC_GATE>;
478 clock-names = "ipg", "ahb", "ptp";