arch/arm/boot/dts/imx51-babbage.dts

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 /dts-v1/;
  14 #include "imx51.dtsi"
  15
  16 / {
  17         model = "Freescale i.MX51 Babbage Board";
  18         compatible = "fsl,imx51-babbage", "fsl,imx51";
  19
  20         memory {
  21                 reg = <0x90000000 0x20000000>;
  22         };
  23
  24         clocks {
  25                 ckih1 {
  26                         clock-frequency = <22579200>;
  27                 };
  28
  29                 clk_26M: codec_clock {
  30                         compatible = "fixed-clock";
  31                         reg=<0>;
  32                         #clock-cells = <0>;
  33                         clock-frequency = <26000000>;
  34                         gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
  35                 };
  36         };
  37
  38         display0: display@di0 {
  39                 compatible = "fsl,imx-parallel-display";
  40                 interface-pix-fmt = "rgb24";
  41                 pinctrl-names = "default";
  42                 pinctrl-0 = <&pinctrl_ipu_disp1>;
  43                 display-timings {
  44                         native-mode = <&timing0>;
  45                         timing0: dvi {
  46                                 clock-frequency = <65000000>;
  47                                 hactive = <1024>;
  48                                 vactive = <768>;
  49                                 hback-porch = <220>;
  50                                 hfront-porch = <40>;
  51                                 vback-porch = <21>;
  52                                 vfront-porch = <7>;
  53                                 hsync-len = <60>;
  54                                 vsync-len = <10>;
  55                         };
  56                 };
  57
  58                 port {
  59                         display0_in: endpoint {
  60                                 remote-endpoint = <&ipu_di0_disp0>;
  61                         };
  62                 };
  63         };
  64
  65         display1: display@di1 {
  66                 compatible = "fsl,imx-parallel-display";
  67                 interface-pix-fmt = "rgb565";
  68                 pinctrl-names = "default";
  69                 pinctrl-0 = <&pinctrl_ipu_disp2>;
  70                 status = "disabled";
  71                 display-timings {
  72                         native-mode = <&timing1>;
  73                         timing1: claawvga {
  74                                 clock-frequency = <27000000>;
  75                                 hactive = <800>;
  76                                 vactive = <480>;
  77                                 hback-porch = <40>;
  78                                 hfront-porch = <60>;
  79                                 vback-porch = <10>;
  80                                 vfront-porch = <10>;
  81                                 hsync-len = <20>;
  82                                 vsync-len = <10>;
  83                                 hsync-active = <0>;
  84                                 vsync-active = <0>;
  85                                 de-active = <1>;
  86                                 pixelclk-active = <0>;
  87                         };
  88                 };
  89
  90                 port {
  91                         display1_in: endpoint {
  92                                 remote-endpoint = <&ipu_di1_disp1>;
  93                         };
  94                 };
  95         };
  96
  97         gpio-keys {
  98                 compatible = "gpio-keys";
  99                 pinctrl-names = "default";
 100                 pinctrl-0 = <&pinctrl_gpio_keys>;
 101
 102                 power {
 103                         label = "Power Button";
 104                         gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
 105                         linux,code = <KEY_POWER>;
 106                         gpio-key,wakeup;
 107                 };
 108         };
 109
 110         leds {
 111                 compatible = "gpio-leds";
 112                 pinctrl-names = "default";
 113                 pinctrl-0 = <&pinctrl_gpio_leds>;
 114
 115                 led-diagnostic {
 116                         label = "diagnostic";
 117                         gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
 118                 };
 119         };
 120
 121         regulators {
 122                 compatible = "simple-bus";
 123                 #address-cells = <1>;
 124                 #size-cells = <0>;
 125
 126                 reg_usbh1_vbus: regulator@0 {
 127                         compatible = "regulator-fixed";
 128                         pinctrl-names = "default";
 129                         pinctrl-0 = <&pinctrl_usbh1reg>;
 130                         reg = <0>;
 131                         regulator-name = "usbh1_vbus";
 132                         regulator-min-microvolt = <5000000>;
 133                         regulator-max-microvolt = <5000000>;
 134                         gpio = <&gpio2 5 GPIO_ACTIVE_HIGH>;
 135                         enable-active-high;
 136                 };
 137
 138                 reg_usbotg_vbus: regulator@1 {
 139                         compatible = "regulator-fixed";
 140                         pinctrl-names = "default";
 141                         pinctrl-0 = <&pinctrl_usbotgreg>;
 142                         reg = <1>;
 143                         regulator-name = "usbotg_vbus";
 144                         regulator-min-microvolt = <5000000>;
 145                         regulator-max-microvolt = <5000000>;
 146                         gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
 147                         enable-active-high;
 148                 };
 149         };
 150
 151         sound {
 152                 compatible = "fsl,imx51-babbage-sgtl5000",
 153                              "fsl,imx-audio-sgtl5000";
 154                 model = "imx51-babbage-sgtl5000";
 155                 ssi-controller = <&ssi2>;
 156                 audio-codec = <&sgtl5000>;
 157                 audio-routing =
 158                         "MIC_IN", "Mic Jack",
 159                         "Mic Jack", "Mic Bias",
 160                         "Headphone Jack", "HP_OUT";
 161                 mux-int-port = <2>;
 162                 mux-ext-port = <3>;
 163         };
 164
 165         usbphy {
 166                 #address-cells = <1>;
 167                 #size-cells = <0>;
 168                 compatible = "simple-bus";
 169
 170                 usbh1phy: usbh1phy@0 {
 171                         compatible = "usb-nop-xceiv";
 172                         reg = <0>;
 173                         clocks = <&clks 0>;
 174                         clock-names = "main_clk";
 175                 };
 176         };
 177 };
 178
 179 &audmux {
 180         pinctrl-names = "default";
 181         pinctrl-0 = <&pinctrl_audmux>;
 182         status = "okay";
 183 };
 184
 185 &ecspi1 {
 186         pinctrl-names = "default";
 187         pinctrl-0 = <&pinctrl_ecspi1>;
 188         fsl,spi-num-chipselects = <2>;
 189         cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>,
 190                    <&gpio4 25 GPIO_ACTIVE_LOW>;
 191         status = "okay";
 192
 193         pmic: mc13892@0 {
 194                 #address-cells = <1>;
 195                 #size-cells = <0>;
 196                 compatible = "fsl,mc13892";
 197                 pinctrl-names = "default";
 198                 pinctrl-0 = <&pinctrl_pmic>;
 199                 spi-max-frequency = <6000000>;
 200                 spi-cs-high;
 201                 reg = <0>;
 202                 interrupt-parent = <&gpio1>;
 203                 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
 204
 205                 regulators {
 206                         sw1_reg: sw1 {
 207                                 regulator-min-microvolt = <600000>;
 208                                 regulator-max-microvolt = <1375000>;
 209                                 regulator-boot-on;
 210                                 regulator-always-on;
 211                         };
 212
 213                         sw2_reg: sw2 {
 214                                 regulator-min-microvolt = <900000>;
 215                                 regulator-max-microvolt = <1850000>;
 216                                 regulator-boot-on;
 217                                 regulator-always-on;
 218                         };
 219
 220                         sw3_reg: sw3 {
 221                                 regulator-min-microvolt = <1100000>;
 222                                 regulator-max-microvolt = <1850000>;
 223                                 regulator-boot-on;
 224                                 regulator-always-on;
 225                         };
 226
 227                         sw4_reg: sw4 {
 228                                 regulator-min-microvolt = <1100000>;
 229                                 regulator-max-microvolt = <1850000>;
 230                                 regulator-boot-on;
 231                                 regulator-always-on;
 232                         };
 233
 234                         vpll_reg: vpll {
 235                                 regulator-min-microvolt = <1050000>;
 236                                 regulator-max-microvolt = <1800000>;
 237                                 regulator-boot-on;
 238                                 regulator-always-on;
 239                         };
 240
 241                         vdig_reg: vdig {
 242                                 regulator-min-microvolt = <1650000>;
 243                                 regulator-max-microvolt = <1650000>;
 244                                 regulator-boot-on;
 245                         };
 246
 247                         vsd_reg: vsd {
 248                                 regulator-min-microvolt = <1800000>;
 249                                 regulator-max-microvolt = <3150000>;
 250                         };
 251
 252                         vusb2_reg: vusb2 {
 253                                 regulator-min-microvolt = <2400000>;
 254                                 regulator-max-microvolt = <2775000>;
 255                                 regulator-boot-on;
 256                                 regulator-always-on;
 257                         };
 258
 259                         vvideo_reg: vvideo {
 260                                 regulator-min-microvolt = <2775000>;
 261                                 regulator-max-microvolt = <2775000>;
 262                         };
 263
 264                         vaudio_reg: vaudio {
 265                                 regulator-min-microvolt = <2300000>;
 266                                 regulator-max-microvolt = <3000000>;
 267                         };
 268
 269                         vcam_reg: vcam {
 270                                 regulator-min-microvolt = <2500000>;
 271                                 regulator-max-microvolt = <3000000>;
 272                         };
 273
 274                         vgen1_reg: vgen1 {
 275                                 regulator-min-microvolt = <1200000>;
 276                                 regulator-max-microvolt = <1200000>;
 277                         };
 278
 279                         vgen2_reg: vgen2 {
 280                                 regulator-min-microvolt = <1200000>;
 281                                 regulator-max-microvolt = <3150000>;
 282                                 regulator-always-on;
 283                         };
 284
 285                         vgen3_reg: vgen3 {
 286                                 regulator-min-microvolt = <1800000>;
 287                                 regulator-max-microvolt = <2900000>;
 288                                 regulator-always-on;
 289                         };
 290                 };
 291         };
 292
 293         flash: at45db321d@1 {
 294                 #address-cells = <1>;
 295                 #size-cells = <1>;
 296                 compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
 297                 spi-max-frequency = <25000000>;
 298                 reg = <1>;
 299
 300                 partition@0 {
 301                         label = "U-Boot";
 302                         reg = <0x0 0x40000>;
 303                         read-only;
 304                 };
 305
 306                 partition@40000 {
 307                         label = "Kernel";
 308                         reg = <0x40000 0x3c0000>;
 309                 };
 310         };
 311 };
 312
 313 &esdhc1 {
 314         pinctrl-names = "default";
 315         pinctrl-0 = <&pinctrl_esdhc1>;
 316         fsl,cd-controller;
 317         fsl,wp-controller;
 318         status = "okay";
 319 };
 320
 321 &esdhc2 {
 322         pinctrl-names = "default";
 323         pinctrl-0 = <&pinctrl_esdhc2>;
 324         cd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
 325         wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
 326         status = "okay";
 327 };
 328
 329 &fec {
 330         pinctrl-names = "default";
 331         pinctrl-0 = <&pinctrl_fec>;
 332         phy-mode = "mii";
 333         phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
 334         phy-reset-duration = <1>;
 335         status = "okay";
 336 };
 337
 338 &i2c2 {
 339         pinctrl-names = "default";
 340         pinctrl-0 = <&pinctrl_i2c2>;
 341         status = "okay";
 342
 343         sgtl5000: codec@0a {
 344                 compatible = "fsl,sgtl5000";
 345                 pinctrl-names = "default";
 346                 pinctrl-0 = <&pinctrl_clkcodec>;
 347                 reg = <0x0a>;
 348                 clocks = <&clk_26M>;
 349                 VDDA-supply = <&vdig_reg>;
 350                 VDDIO-supply = <&vvideo_reg>;
 351         };
 352 };
 353
 354 &ipu_di0_disp0 {
 355         remote-endpoint = <&display0_in>;
 356 };
 357
 358 &ipu_di1_disp1 {
 359         remote-endpoint = <&display1_in>;
 360 };
 361
 362 &kpp {
 363         pinctrl-names = "default";
 364         pinctrl-0 = <&pinctrl_kpp>;
 365         linux,keymap = <
 366                 MATRIX_KEY(0, 0, KEY_UP)
 367                 MATRIX_KEY(0, 1, KEY_DOWN)
 368                 MATRIX_KEY(0, 2, KEY_VOLUMEDOWN)
 369                 MATRIX_KEY(0, 3, KEY_HOME)
 370                 MATRIX_KEY(1, 0, KEY_RIGHT)
 371                 MATRIX_KEY(1, 1, KEY_LEFT)
 372                 MATRIX_KEY(1, 2, KEY_ENTER)
 373                 MATRIX_KEY(1, 3, KEY_VOLUMEUP)
 374                 MATRIX_KEY(2, 0, KEY_F6)
 375                 MATRIX_KEY(2, 1, KEY_F8)
 376                 MATRIX_KEY(2, 2, KEY_F9)
 377                 MATRIX_KEY(2, 3, KEY_F10)
 378                 MATRIX_KEY(3, 0, KEY_F1)
 379                 MATRIX_KEY(3, 1, KEY_F2)
 380                 MATRIX_KEY(3, 2, KEY_F3)
 381                 MATRIX_KEY(3, 3, KEY_POWER)
 382         >;
 383         status = "okay";
 384 };
 385
 386 &ssi2 {
 387         fsl,mode = "i2s-slave";
 388         status = "okay";
 389 };
 390
 391 &uart1 {
 392         pinctrl-names = "default";
 393         pinctrl-0 = <&pinctrl_uart1>;
 394         fsl,uart-has-rtscts;
 395         status = "okay";
 396 };
 397
 398 &uart2 {
 399         pinctrl-names = "default";
 400         pinctrl-0 = <&pinctrl_uart2>;
 401         status = "okay";
 402 };
 403
 404 &uart3 {
 405         pinctrl-names = "default";
 406         pinctrl-0 = <&pinctrl_uart3>;
 407         fsl,uart-has-rtscts;
 408         status = "okay";
 409 };
 410
 411 &usbh1 {
 412         pinctrl-names = "default";
 413         pinctrl-0 = <&pinctrl_usbh1>;
 414         vbus-supply = <&reg_usbh1_vbus>;
 415         fsl,usbphy = <&usbh1phy>;
 416         phy_type = "ulpi";
 417         status = "okay";
 418 };
 419
 420 &usbotg {
 421         dr_mode = "otg";
 422         disable-over-current;
 423         phy_type = "utmi_wide";
 424         vbus-supply = <&reg_usbotg_vbus>;
 425         status = "okay";
 426 };
 427
 428 &iomuxc {
 429         imx51-babbage {
 430                 pinctrl_audmux: audmuxgrp {
 431                         fsl,pins = <
 432                                 MX51_PAD_AUD3_BB_TXD__AUD3_TXD          0x80000000
 433                                 MX51_PAD_AUD3_BB_RXD__AUD3_RXD          0x80000000
 434                                 MX51_PAD_AUD3_BB_CK__AUD3_TXC           0x80000000
 435                                 MX51_PAD_AUD3_BB_FS__AUD3_TXFS          0x80000000
 436                         >;
 437                 };
 438
 439                 pinctrl_clkcodec: clkcodecgrp {
 440                         fsl,pins = <
 441                                 MX51_PAD_CSPI1_RDY__GPIO4_26            0x80000000
 442                         >;
 443                 };
 444
 445                 pinctrl_ecspi1: ecspi1grp {
 446                         fsl,pins = <
 447                                 MX51_PAD_CSPI1_MISO__ECSPI1_MISO        0x185
 448                                 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI        0x185
 449                                 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK        0x185
 450                                 MX51_PAD_CSPI1_SS0__GPIO4_24            0x85 /* CS0 */
 451                                 MX51_PAD_CSPI1_SS1__GPIO4_25            0x85 /* CS1 */
 452                         >;
 453                 };
 454
 455                 pinctrl_esdhc1: esdhc1grp {
 456                         fsl,pins = <
 457                                 MX51_PAD_SD1_CMD__SD1_CMD               0x400020d5
 458                                 MX51_PAD_SD1_CLK__SD1_CLK               0x20d5
 459                                 MX51_PAD_SD1_DATA0__SD1_DATA0           0x20d5
 460                                 MX51_PAD_SD1_DATA1__SD1_DATA1           0x20d5
 461                                 MX51_PAD_SD1_DATA2__SD1_DATA2           0x20d5
 462                                 MX51_PAD_SD1_DATA3__SD1_DATA3           0x20d5
 463                                 MX51_PAD_GPIO1_0__SD1_CD                0x20d5
 464                                 MX51_PAD_GPIO1_1__SD1_WP                0x20d5
 465                         >;
 466                 };
 467
 468                 pinctrl_esdhc2: esdhc2grp {
 469                         fsl,pins = <
 470                                 MX51_PAD_SD2_CMD__SD2_CMD               0x400020d5
 471                                 MX51_PAD_SD2_CLK__SD2_CLK               0x20d5
 472                                 MX51_PAD_SD2_DATA0__SD2_DATA0           0x20d5
 473                                 MX51_PAD_SD2_DATA1__SD2_DATA1           0x20d5
 474                                 MX51_PAD_SD2_DATA2__SD2_DATA2           0x20d5
 475                                 MX51_PAD_SD2_DATA3__SD2_DATA3           0x20d5
 476                                 MX51_PAD_GPIO1_5__GPIO1_5               0x100 /* WP */
 477                                 MX51_PAD_GPIO1_6__GPIO1_6               0x100 /* CD */
 478                         >;
 479                 };
 480
 481                 pinctrl_fec: fecgrp {
 482                         fsl,pins = <
 483                                 MX51_PAD_EIM_EB2__FEC_MDIO              0x80000000
 484                                 MX51_PAD_EIM_EB3__FEC_RDATA1            0x80000000
 485                                 MX51_PAD_EIM_CS2__FEC_RDATA2            0x80000000
 486                                 MX51_PAD_EIM_CS3__FEC_RDATA3            0x80000000
 487                                 MX51_PAD_EIM_CS4__FEC_RX_ER             0x80000000
 488                                 MX51_PAD_EIM_CS5__FEC_CRS               0x80000000
 489                                 MX51_PAD_NANDF_RB2__FEC_COL             0x80000000
 490                                 MX51_PAD_NANDF_RB3__FEC_RX_CLK          0x80000000
 491                                 MX51_PAD_NANDF_D9__FEC_RDATA0           0x80000000
 492                                 MX51_PAD_NANDF_D8__FEC_TDATA0           0x80000000
 493                                 MX51_PAD_NANDF_CS2__FEC_TX_ER           0x80000000
 494                                 MX51_PAD_NANDF_CS3__FEC_MDC             0x80000000
 495                                 MX51_PAD_NANDF_CS4__FEC_TDATA1          0x80000000
 496                                 MX51_PAD_NANDF_CS5__FEC_TDATA2          0x80000000
 497                                 MX51_PAD_NANDF_CS6__FEC_TDATA3          0x80000000
 498                                 MX51_PAD_NANDF_CS7__FEC_TX_EN           0x80000000
 499                                 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK      0x80000000
 500                                 MX51_PAD_EIM_A20__GPIO2_14              0x85 /* Reset */
 501                         >;
 502                 };
 503
 504                 pinctrl_gpio_keys: gpiokeysgrp {
 505                         fsl,pins = <
 506                                 MX51_PAD_EIM_A27__GPIO2_21              0x5
 507                         >;
 508                 };
 509
 510                 pinctrl_gpio_leds: gpioledsgrp {
 511                         fsl,pins = <
 512                                 MX51_PAD_EIM_D22__GPIO2_6               0x80000000
 513                         >;
 514                 };
 515
 516                 pinctrl_i2c2: i2c2grp {
 517                         fsl,pins = <
 518                                 MX51_PAD_KEY_COL4__I2C2_SCL             0x400001ed
 519                                 MX51_PAD_KEY_COL5__I2C2_SDA             0x400001ed
 520                         >;
 521                 };
 522
 523                 pinctrl_ipu_disp1: ipudisp1grp {
 524                         fsl,pins = <
 525                                 MX51_PAD_DISP1_DAT0__DISP1_DAT0         0x5
 526                                 MX51_PAD_DISP1_DAT1__DISP1_DAT1         0x5
 527                                 MX51_PAD_DISP1_DAT2__DISP1_DAT2         0x5
 528                                 MX51_PAD_DISP1_DAT3__DISP1_DAT3         0x5
 529                                 MX51_PAD_DISP1_DAT4__DISP1_DAT4         0x5
 530                                 MX51_PAD_DISP1_DAT5__DISP1_DAT5         0x5
 531                                 MX51_PAD_DISP1_DAT6__DISP1_DAT6         0x5
 532                                 MX51_PAD_DISP1_DAT7__DISP1_DAT7         0x5
 533                                 MX51_PAD_DISP1_DAT8__DISP1_DAT8         0x5
 534                                 MX51_PAD_DISP1_DAT9__DISP1_DAT9         0x5
 535                                 MX51_PAD_DISP1_DAT10__DISP1_DAT10       0x5
 536                                 MX51_PAD_DISP1_DAT11__DISP1_DAT11       0x5
 537                                 MX51_PAD_DISP1_DAT12__DISP1_DAT12       0x5
 538                                 MX51_PAD_DISP1_DAT13__DISP1_DAT13       0x5
 539                                 MX51_PAD_DISP1_DAT14__DISP1_DAT14       0x5
 540                                 MX51_PAD_DISP1_DAT15__DISP1_DAT15       0x5
 541                                 MX51_PAD_DISP1_DAT16__DISP1_DAT16       0x5
 542                                 MX51_PAD_DISP1_DAT17__DISP1_DAT17       0x5
 543                                 MX51_PAD_DISP1_DAT18__DISP1_DAT18       0x5
 544                                 MX51_PAD_DISP1_DAT19__DISP1_DAT19       0x5
 545                                 MX51_PAD_DISP1_DAT20__DISP1_DAT20       0x5
 546                                 MX51_PAD_DISP1_DAT21__DISP1_DAT21       0x5
 547                                 MX51_PAD_DISP1_DAT22__DISP1_DAT22       0x5
 548                                 MX51_PAD_DISP1_DAT23__DISP1_DAT23       0x5
 549                                 MX51_PAD_DI1_PIN2__DI1_PIN2             0x5
 550                                 MX51_PAD_DI1_PIN3__DI1_PIN3             0x5
 551                         >;
 552                 };
 553
 554                 pinctrl_ipu_disp2: ipudisp2grp {
 555                         fsl,pins = <
 556                                 MX51_PAD_DISP2_DAT0__DISP2_DAT0         0x5
 557                                 MX51_PAD_DISP2_DAT1__DISP2_DAT1         0x5
 558                                 MX51_PAD_DISP2_DAT2__DISP2_DAT2         0x5
 559                                 MX51_PAD_DISP2_DAT3__DISP2_DAT3         0x5
 560                                 MX51_PAD_DISP2_DAT4__DISP2_DAT4         0x5
 561                                 MX51_PAD_DISP2_DAT5__DISP2_DAT5         0x5
 562                                 MX51_PAD_DISP2_DAT6__DISP2_DAT6         0x5
 563                                 MX51_PAD_DISP2_DAT7__DISP2_DAT7         0x5
 564                                 MX51_PAD_DISP2_DAT8__DISP2_DAT8         0x5
 565                                 MX51_PAD_DISP2_DAT9__DISP2_DAT9         0x5
 566                                 MX51_PAD_DISP2_DAT10__DISP2_DAT10       0x5
 567                                 MX51_PAD_DISP2_DAT11__DISP2_DAT11       0x5
 568                                 MX51_PAD_DISP2_DAT12__DISP2_DAT12       0x5
 569                                 MX51_PAD_DISP2_DAT13__DISP2_DAT13       0x5
 570                                 MX51_PAD_DISP2_DAT14__DISP2_DAT14       0x5
 571                                 MX51_PAD_DISP2_DAT15__DISP2_DAT15       0x5
 572                                 MX51_PAD_DI2_PIN2__DI2_PIN2             0x5
 573                                 MX51_PAD_DI2_PIN3__DI2_PIN3             0x5
 574                                 MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK     0x5
 575                                 MX51_PAD_DI_GP4__DI2_PIN15              0x5
 576                         >;
 577                 };
 578
 579                 pinctrl_kpp: kppgrp {
 580                         fsl,pins = <
 581                                 MX51_PAD_KEY_ROW0__KEY_ROW0             0xe0
 582                                 MX51_PAD_KEY_ROW1__KEY_ROW1             0xe0
 583                                 MX51_PAD_KEY_ROW2__KEY_ROW2             0xe0
 584                                 MX51_PAD_KEY_ROW3__KEY_ROW3             0xe0
 585                                 MX51_PAD_KEY_COL0__KEY_COL0             0xe8
 586                                 MX51_PAD_KEY_COL1__KEY_COL1             0xe8
 587                                 MX51_PAD_KEY_COL2__KEY_COL2             0xe8
 588                                 MX51_PAD_KEY_COL3__KEY_COL3             0xe8
 589                         >;
 590                 };
 591
 592                 pinctrl_pmic: pmicgrp {
 593                         fsl,pins = <
 594                                 MX51_PAD_GPIO1_8__GPIO1_8               0xe5 /* IRQ */
 595                         >;
 596                 };
 597
 598                 pinctrl_uart1: uart1grp {
 599                         fsl,pins = <
 600                                 MX51_PAD_UART1_RXD__UART1_RXD           0x1c5
 601                                 MX51_PAD_UART1_TXD__UART1_TXD           0x1c5
 602                                 MX51_PAD_UART1_RTS__UART1_RTS           0x1c5
 603                                 MX51_PAD_UART1_CTS__UART1_CTS           0x1c5
 604                         >;
 605                 };
 606
 607                 pinctrl_uart2: uart2grp {
 608                         fsl,pins = <
 609                                 MX51_PAD_UART2_RXD__UART2_RXD           0x1c5
 610                                 MX51_PAD_UART2_TXD__UART2_TXD           0x1c5
 611                         >;
 612                 };
 613
 614                 pinctrl_uart3: uart3grp {
 615                         fsl,pins = <
 616                                 MX51_PAD_EIM_D25__UART3_RXD             0x1c5
 617                                 MX51_PAD_EIM_D26__UART3_TXD             0x1c5
 618                                 MX51_PAD_EIM_D27__UART3_RTS             0x1c5
 619                                 MX51_PAD_EIM_D24__UART3_CTS             0x1c5
 620                         >;
 621                 };
 622
 623                 pinctrl_usbh1: usbh1grp {
 624                         fsl,pins = <
 625                                 MX51_PAD_USBH1_CLK__USBH1_CLK           0x80000000
 626                                 MX51_PAD_USBH1_DIR__USBH1_DIR           0x80000000
 627                                 MX51_PAD_USBH1_NXT__USBH1_NXT           0x80000000
 628                                 MX51_PAD_USBH1_DATA0__USBH1_DATA0       0x80000000
 629                                 MX51_PAD_USBH1_DATA1__USBH1_DATA1       0x80000000
 630                                 MX51_PAD_USBH1_DATA2__USBH1_DATA2       0x80000000
 631                                 MX51_PAD_USBH1_DATA3__USBH1_DATA3       0x80000000
 632                                 MX51_PAD_USBH1_DATA4__USBH1_DATA4       0x80000000
 633                                 MX51_PAD_USBH1_DATA5__USBH1_DATA5       0x80000000
 634                                 MX51_PAD_USBH1_DATA6__USBH1_DATA6       0x80000000
 635                                 MX51_PAD_USBH1_DATA7__USBH1_DATA7       0x80000000
 636                         >;
 637                 };
 638
 639                 pinctrl_usbh1reg: usbh1reggrp {
 640                         fsl,pins = <
 641                                 MX51_PAD_EIM_D21__GPIO2_5               0x85
 642                         >;
 643                 };
 644
 645                 pinctrl_usbotgreg: usbotgreggrp {
 646                         fsl,pins = <
 647                                 MX51_PAD_GPIO1_7__GPIO1_7               0x85
 648                         >;
 649                 };
 650         };
 651 };