2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include "skeleton.dtsi"
14 #include "imx51-pinfunc.h"
15 #include <dt-bindings/clock/imx5-clock.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/input/input.h>
18 #include <dt-bindings/interrupt-controller/irq.h>
41 tzic: tz-interrupt-controller@e0000000 {
42 compatible = "fsl,imx51-tzic", "fsl,tzic";
44 #interrupt-cells = <1>;
45 reg = <0xe0000000 0x4000>;
53 compatible = "fsl,imx-ckil", "fixed-clock";
55 clock-frequency = <32768>;
59 compatible = "fsl,imx-ckih1", "fixed-clock";
61 clock-frequency = <0>;
65 compatible = "fsl,imx-ckih2", "fixed-clock";
67 clock-frequency = <0>;
71 compatible = "fsl,imx-osc", "fixed-clock";
73 clock-frequency = <24000000>;
82 compatible = "arm,cortex-a8";
84 clock-latency = <62500>;
85 clocks = <&clks IMX5_CLK_CPU_PODF>;
92 voltage-tolerance = <5>;
99 compatible = "simple-bus";
102 compatible = "usb-nop-xceiv";
104 clocks = <&clks IMX5_CLK_USB_PHY_GATE>;
105 clock-names = "main_clk";
110 compatible = "fsl,imx-display-subsystem";
111 ports = <&ipu_di0>, <&ipu_di1>;
115 #address-cells = <1>;
117 compatible = "simple-bus";
118 interrupt-parent = <&tzic>;
121 iram: iram@1ffe0000 {
122 compatible = "mmio-sram";
123 reg = <0x1ffe0000 0x20000>;
127 #address-cells = <1>;
129 compatible = "fsl,imx51-ipu";
130 reg = <0x40000000 0x20000000>;
131 interrupts = <11 10>;
132 clocks = <&clks IMX5_CLK_IPU_GATE>,
133 <&clks IMX5_CLK_IPU_DI0_GATE>,
134 <&clks IMX5_CLK_IPU_DI1_GATE>;
135 clock-names = "bus", "di0", "di1";
141 ipu_di0_disp0: endpoint {
148 ipu_di1_disp1: endpoint {
153 aips@70000000 { /* AIPS1 */
154 compatible = "fsl,aips-bus", "simple-bus";
155 #address-cells = <1>;
157 reg = <0x70000000 0x10000000>;
161 compatible = "fsl,spba-bus", "simple-bus";
162 #address-cells = <1>;
164 reg = <0x70000000 0x40000>;
167 esdhc1: esdhc@70004000 {
168 compatible = "fsl,imx51-esdhc";
169 reg = <0x70004000 0x4000>;
171 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
172 <&clks IMX5_CLK_DUMMY>,
173 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
174 clock-names = "ipg", "ahb", "per";
178 esdhc2: esdhc@70008000 {
179 compatible = "fsl,imx51-esdhc";
180 reg = <0x70008000 0x4000>;
182 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
183 <&clks IMX5_CLK_DUMMY>,
184 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
185 clock-names = "ipg", "ahb", "per";
190 uart3: serial@7000c000 {
191 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
192 reg = <0x7000c000 0x4000>;
194 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
195 <&clks IMX5_CLK_UART3_PER_GATE>;
196 clock-names = "ipg", "per";
200 ecspi1: ecspi@70010000 {
201 #address-cells = <1>;
203 compatible = "fsl,imx51-ecspi";
204 reg = <0x70010000 0x4000>;
206 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
207 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
208 clock-names = "ipg", "per";
213 #sound-dai-cells = <0>;
214 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
215 reg = <0x70014000 0x4000>;
217 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
218 dmas = <&sdma 24 1 0>,
220 dma-names = "rx", "tx";
221 fsl,fifo-depth = <15>;
225 esdhc3: esdhc@70020000 {
226 compatible = "fsl,imx51-esdhc";
227 reg = <0x70020000 0x4000>;
229 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
230 <&clks IMX5_CLK_DUMMY>,
231 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
232 clock-names = "ipg", "ahb", "per";
237 esdhc4: esdhc@70024000 {
238 compatible = "fsl,imx51-esdhc";
239 reg = <0x70024000 0x4000>;
241 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
242 <&clks IMX5_CLK_DUMMY>,
243 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
244 clock-names = "ipg", "ahb", "per";
250 usbotg: usb@73f80000 {
251 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
252 reg = <0x73f80000 0x0200>;
254 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
255 fsl,usbmisc = <&usbmisc 0>;
256 fsl,usbphy = <&usbphy0>;
260 usbh1: usb@73f80200 {
261 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
262 reg = <0x73f80200 0x0200>;
264 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
265 fsl,usbmisc = <&usbmisc 1>;
269 usbh2: usb@73f80400 {
270 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
271 reg = <0x73f80400 0x0200>;
273 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
274 fsl,usbmisc = <&usbmisc 2>;
278 usbh3: usb@73f80600 {
279 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
280 reg = <0x73f80600 0x0200>;
282 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
283 fsl,usbmisc = <&usbmisc 3>;
287 usbmisc: usbmisc@73f80800 {
289 compatible = "fsl,imx51-usbmisc";
290 reg = <0x73f80800 0x200>;
291 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
294 gpio1: gpio@73f84000 {
295 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
296 reg = <0x73f84000 0x4000>;
297 interrupts = <50 51>;
300 interrupt-controller;
301 #interrupt-cells = <2>;
304 gpio2: gpio@73f88000 {
305 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
306 reg = <0x73f88000 0x4000>;
307 interrupts = <52 53>;
310 interrupt-controller;
311 #interrupt-cells = <2>;
314 gpio3: gpio@73f8c000 {
315 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
316 reg = <0x73f8c000 0x4000>;
317 interrupts = <54 55>;
320 interrupt-controller;
321 #interrupt-cells = <2>;
324 gpio4: gpio@73f90000 {
325 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
326 reg = <0x73f90000 0x4000>;
327 interrupts = <56 57>;
330 interrupt-controller;
331 #interrupt-cells = <2>;
335 compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
336 reg = <0x73f94000 0x4000>;
338 clocks = <&clks IMX5_CLK_DUMMY>;
342 wdog1: wdog@73f98000 {
343 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
344 reg = <0x73f98000 0x4000>;
346 clocks = <&clks IMX5_CLK_DUMMY>;
349 wdog2: wdog@73f9c000 {
350 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
351 reg = <0x73f9c000 0x4000>;
353 clocks = <&clks IMX5_CLK_DUMMY>;
357 gpt: timer@73fa0000 {
358 compatible = "fsl,imx51-gpt", "fsl,imx31-gpt";
359 reg = <0x73fa0000 0x4000>;
361 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
362 <&clks IMX5_CLK_GPT_HF_GATE>;
363 clock-names = "ipg", "per";
366 iomuxc: iomuxc@73fa8000 {
367 compatible = "fsl,imx51-iomuxc";
368 reg = <0x73fa8000 0x4000>;
373 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
374 reg = <0x73fb4000 0x4000>;
375 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
376 <&clks IMX5_CLK_PWM1_HF_GATE>;
377 clock-names = "ipg", "per";
383 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
384 reg = <0x73fb8000 0x4000>;
385 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
386 <&clks IMX5_CLK_PWM2_HF_GATE>;
387 clock-names = "ipg", "per";
391 uart1: serial@73fbc000 {
392 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
393 reg = <0x73fbc000 0x4000>;
395 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
396 <&clks IMX5_CLK_UART1_PER_GATE>;
397 clock-names = "ipg", "per";
401 uart2: serial@73fc0000 {
402 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
403 reg = <0x73fc0000 0x4000>;
405 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
406 <&clks IMX5_CLK_UART2_PER_GATE>;
407 clock-names = "ipg", "per";
412 compatible = "fsl,imx51-src";
413 reg = <0x73fd0000 0x4000>;
418 compatible = "fsl,imx51-ccm";
419 reg = <0x73fd4000 0x4000>;
420 interrupts = <0 71 0x04 0 72 0x04>;
425 aips@80000000 { /* AIPS2 */
426 compatible = "fsl,aips-bus", "simple-bus";
427 #address-cells = <1>;
429 reg = <0x80000000 0x10000000>;
433 compatible = "fsl,imx51-iim", "fsl,imx27-iim";
434 reg = <0x83f98000 0x4000>;
436 clocks = <&clks IMX5_CLK_IIM_GATE>;
439 owire: owire@83fa4000 {
440 compatible = "fsl,imx51-owire", "fsl,imx21-owire";
441 reg = <0x83fa4000 0x4000>;
443 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
447 ecspi2: ecspi@83fac000 {
448 #address-cells = <1>;
450 compatible = "fsl,imx51-ecspi";
451 reg = <0x83fac000 0x4000>;
453 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
454 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
455 clock-names = "ipg", "per";
459 sdma: sdma@83fb0000 {
460 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
461 reg = <0x83fb0000 0x4000>;
463 clocks = <&clks IMX5_CLK_SDMA_GATE>,
464 <&clks IMX5_CLK_SDMA_GATE>;
465 clock-names = "ipg", "ahb";
467 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
470 cspi: cspi@83fc0000 {
471 #address-cells = <1>;
473 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
474 reg = <0x83fc0000 0x4000>;
476 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
477 <&clks IMX5_CLK_CSPI_IPG_GATE>;
478 clock-names = "ipg", "per";
483 #address-cells = <1>;
485 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
486 reg = <0x83fc4000 0x4000>;
488 clocks = <&clks IMX5_CLK_I2C2_GATE>;
493 #address-cells = <1>;
495 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
496 reg = <0x83fc8000 0x4000>;
498 clocks = <&clks IMX5_CLK_I2C1_GATE>;
503 #sound-dai-cells = <0>;
504 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
505 reg = <0x83fcc000 0x4000>;
507 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
508 dmas = <&sdma 28 0 0>,
510 dma-names = "rx", "tx";
511 fsl,fifo-depth = <15>;
515 audmux: audmux@83fd0000 {
516 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
517 reg = <0x83fd0000 0x4000>;
518 clocks = <&clks IMX5_CLK_DUMMY>;
519 clock-names = "audmux";
523 weim: weim@83fda000 {
524 #address-cells = <2>;
526 compatible = "fsl,imx51-weim";
527 reg = <0x83fda000 0x1000>;
528 clocks = <&clks IMX5_CLK_EMI_SLOW_GATE>;
530 0 0 0xb0000000 0x08000000
531 1 0 0xb8000000 0x08000000
532 2 0 0xc0000000 0x08000000
533 3 0 0xc8000000 0x04000000
534 4 0 0xcc000000 0x02000000
535 5 0 0xce000000 0x02000000
541 #address-cells = <1>;
543 compatible = "fsl,imx51-nand";
544 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
546 clocks = <&clks IMX5_CLK_NFC_GATE>;
550 pata: pata@83fe0000 {
551 compatible = "fsl,imx51-pata", "fsl,imx27-pata";
552 reg = <0x83fe0000 0x4000>;
554 clocks = <&clks IMX5_CLK_PATA_GATE>;
559 #sound-dai-cells = <0>;
560 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
561 reg = <0x83fe8000 0x4000>;
563 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>;
564 dmas = <&sdma 46 0 0>,
566 dma-names = "rx", "tx";
567 fsl,fifo-depth = <15>;
571 fec: ethernet@83fec000 {
572 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
573 reg = <0x83fec000 0x4000>;
575 clocks = <&clks IMX5_CLK_FEC_GATE>,
576 <&clks IMX5_CLK_FEC_GATE>,
577 <&clks IMX5_CLK_FEC_GATE>;
578 clock-names = "ipg", "ahb", "ptp";