2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include "skeleton.dtsi"
14 #include "imx51-pinfunc.h"
15 #include <dt-bindings/clock/imx5-clock.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/input/input.h>
18 #include <dt-bindings/interrupt-controller/irq.h>
41 tzic: tz-interrupt-controller@e0000000 {
42 compatible = "fsl,imx51-tzic", "fsl,tzic";
44 #interrupt-cells = <1>;
45 reg = <0xe0000000 0x4000>;
53 compatible = "fsl,imx-ckil", "fixed-clock";
55 clock-frequency = <32768>;
59 compatible = "fsl,imx-ckih1", "fixed-clock";
61 clock-frequency = <0>;
65 compatible = "fsl,imx-ckih2", "fixed-clock";
67 clock-frequency = <0>;
71 compatible = "fsl,imx-osc", "fixed-clock";
73 clock-frequency = <24000000>;
82 compatible = "arm,cortex-a8";
84 clock-latency = <62500>;
85 clocks = <&clks IMX5_CLK_CPU_PODF>;
92 voltage-tolerance = <5>;
99 compatible = "simple-bus";
102 compatible = "usb-nop-xceiv";
104 clocks = <&clks IMX5_CLK_USB_PHY_GATE>;
105 clock-names = "main_clk";
110 compatible = "fsl,imx-display-subsystem";
111 ports = <&ipu_di0>, <&ipu_di1>;
115 #address-cells = <1>;
117 compatible = "simple-bus";
118 interrupt-parent = <&tzic>;
121 iram: iram@1ffe0000 {
122 compatible = "mmio-sram";
123 reg = <0x1ffe0000 0x20000>;
127 #address-cells = <1>;
129 compatible = "fsl,imx51-ipu";
130 reg = <0x40000000 0x20000000>;
131 interrupts = <11 10>;
132 clocks = <&clks IMX5_CLK_IPU_GATE>,
133 <&clks IMX5_CLK_IPU_DI0_GATE>,
134 <&clks IMX5_CLK_IPU_DI1_GATE>;
135 clock-names = "bus", "di0", "di1";
141 ipu_di0_disp0: endpoint {
148 ipu_di1_disp1: endpoint {
153 aips@70000000 { /* AIPS1 */
154 compatible = "fsl,aips-bus", "simple-bus";
155 #address-cells = <1>;
157 reg = <0x70000000 0x10000000>;
161 compatible = "fsl,spba-bus", "simple-bus";
162 #address-cells = <1>;
164 reg = <0x70000000 0x40000>;
167 esdhc1: esdhc@70004000 {
168 compatible = "fsl,imx51-esdhc";
169 reg = <0x70004000 0x4000>;
171 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
172 <&clks IMX5_CLK_DUMMY>,
173 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
174 clock-names = "ipg", "ahb", "per";
178 esdhc2: esdhc@70008000 {
179 compatible = "fsl,imx51-esdhc";
180 reg = <0x70008000 0x4000>;
182 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
183 <&clks IMX5_CLK_DUMMY>,
184 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
185 clock-names = "ipg", "ahb", "per";
190 uart3: serial@7000c000 {
191 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
192 reg = <0x7000c000 0x4000>;
194 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
195 <&clks IMX5_CLK_UART3_PER_GATE>;
196 clock-names = "ipg", "per";
200 ecspi1: ecspi@70010000 {
201 #address-cells = <1>;
203 compatible = "fsl,imx51-ecspi";
204 reg = <0x70010000 0x4000>;
206 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
207 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
208 clock-names = "ipg", "per";
213 #sound-dai-cells = <0>;
214 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
215 reg = <0x70014000 0x4000>;
217 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
218 <&clks IMX5_CLK_SSI2_ROOT_GATE>;
219 clock-names = "ipg", "baud";
220 dmas = <&sdma 24 1 0>,
222 dma-names = "rx", "tx";
223 fsl,fifo-depth = <15>;
227 esdhc3: esdhc@70020000 {
228 compatible = "fsl,imx51-esdhc";
229 reg = <0x70020000 0x4000>;
231 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
232 <&clks IMX5_CLK_DUMMY>,
233 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
234 clock-names = "ipg", "ahb", "per";
239 esdhc4: esdhc@70024000 {
240 compatible = "fsl,imx51-esdhc";
241 reg = <0x70024000 0x4000>;
243 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
244 <&clks IMX5_CLK_DUMMY>,
245 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
246 clock-names = "ipg", "ahb", "per";
252 usbotg: usb@73f80000 {
253 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
254 reg = <0x73f80000 0x0200>;
256 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
257 fsl,usbmisc = <&usbmisc 0>;
258 fsl,usbphy = <&usbphy0>;
262 usbh1: usb@73f80200 {
263 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
264 reg = <0x73f80200 0x0200>;
266 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
267 fsl,usbmisc = <&usbmisc 1>;
271 usbh2: usb@73f80400 {
272 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
273 reg = <0x73f80400 0x0200>;
275 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
276 fsl,usbmisc = <&usbmisc 2>;
280 usbh3: usb@73f80600 {
281 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
282 reg = <0x73f80600 0x0200>;
284 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
285 fsl,usbmisc = <&usbmisc 3>;
289 usbmisc: usbmisc@73f80800 {
291 compatible = "fsl,imx51-usbmisc";
292 reg = <0x73f80800 0x200>;
293 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
296 gpio1: gpio@73f84000 {
297 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
298 reg = <0x73f84000 0x4000>;
299 interrupts = <50 51>;
302 interrupt-controller;
303 #interrupt-cells = <2>;
306 gpio2: gpio@73f88000 {
307 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
308 reg = <0x73f88000 0x4000>;
309 interrupts = <52 53>;
312 interrupt-controller;
313 #interrupt-cells = <2>;
316 gpio3: gpio@73f8c000 {
317 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
318 reg = <0x73f8c000 0x4000>;
319 interrupts = <54 55>;
322 interrupt-controller;
323 #interrupt-cells = <2>;
326 gpio4: gpio@73f90000 {
327 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
328 reg = <0x73f90000 0x4000>;
329 interrupts = <56 57>;
332 interrupt-controller;
333 #interrupt-cells = <2>;
337 compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
338 reg = <0x73f94000 0x4000>;
340 clocks = <&clks IMX5_CLK_DUMMY>;
344 wdog1: wdog@73f98000 {
345 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
346 reg = <0x73f98000 0x4000>;
348 clocks = <&clks IMX5_CLK_DUMMY>;
351 wdog2: wdog@73f9c000 {
352 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
353 reg = <0x73f9c000 0x4000>;
355 clocks = <&clks IMX5_CLK_DUMMY>;
359 gpt: timer@73fa0000 {
360 compatible = "fsl,imx51-gpt", "fsl,imx31-gpt";
361 reg = <0x73fa0000 0x4000>;
363 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
364 <&clks IMX5_CLK_GPT_HF_GATE>;
365 clock-names = "ipg", "per";
368 iomuxc: iomuxc@73fa8000 {
369 compatible = "fsl,imx51-iomuxc";
370 reg = <0x73fa8000 0x4000>;
375 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
376 reg = <0x73fb4000 0x4000>;
377 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
378 <&clks IMX5_CLK_PWM1_HF_GATE>;
379 clock-names = "ipg", "per";
385 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
386 reg = <0x73fb8000 0x4000>;
387 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
388 <&clks IMX5_CLK_PWM2_HF_GATE>;
389 clock-names = "ipg", "per";
393 uart1: serial@73fbc000 {
394 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
395 reg = <0x73fbc000 0x4000>;
397 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
398 <&clks IMX5_CLK_UART1_PER_GATE>;
399 clock-names = "ipg", "per";
403 uart2: serial@73fc0000 {
404 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
405 reg = <0x73fc0000 0x4000>;
407 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
408 <&clks IMX5_CLK_UART2_PER_GATE>;
409 clock-names = "ipg", "per";
414 compatible = "fsl,imx51-src";
415 reg = <0x73fd0000 0x4000>;
420 compatible = "fsl,imx51-ccm";
421 reg = <0x73fd4000 0x4000>;
422 interrupts = <0 71 0x04 0 72 0x04>;
427 aips@80000000 { /* AIPS2 */
428 compatible = "fsl,aips-bus", "simple-bus";
429 #address-cells = <1>;
431 reg = <0x80000000 0x10000000>;
435 compatible = "fsl,imx51-iim", "fsl,imx27-iim";
436 reg = <0x83f98000 0x4000>;
438 clocks = <&clks IMX5_CLK_IIM_GATE>;
441 owire: owire@83fa4000 {
442 compatible = "fsl,imx51-owire", "fsl,imx21-owire";
443 reg = <0x83fa4000 0x4000>;
445 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
449 ecspi2: ecspi@83fac000 {
450 #address-cells = <1>;
452 compatible = "fsl,imx51-ecspi";
453 reg = <0x83fac000 0x4000>;
455 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
456 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
457 clock-names = "ipg", "per";
461 sdma: sdma@83fb0000 {
462 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
463 reg = <0x83fb0000 0x4000>;
465 clocks = <&clks IMX5_CLK_SDMA_GATE>,
466 <&clks IMX5_CLK_SDMA_GATE>;
467 clock-names = "ipg", "ahb";
469 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
472 cspi: cspi@83fc0000 {
473 #address-cells = <1>;
475 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
476 reg = <0x83fc0000 0x4000>;
478 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
479 <&clks IMX5_CLK_CSPI_IPG_GATE>;
480 clock-names = "ipg", "per";
485 #address-cells = <1>;
487 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
488 reg = <0x83fc4000 0x4000>;
490 clocks = <&clks IMX5_CLK_I2C2_GATE>;
495 #address-cells = <1>;
497 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
498 reg = <0x83fc8000 0x4000>;
500 clocks = <&clks IMX5_CLK_I2C1_GATE>;
505 #sound-dai-cells = <0>;
506 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
507 reg = <0x83fcc000 0x4000>;
509 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>,
510 <&clks IMX5_CLK_SSI1_ROOT_GATE>;
511 clock-names = "ipg", "baud";
512 dmas = <&sdma 28 0 0>,
514 dma-names = "rx", "tx";
515 fsl,fifo-depth = <15>;
519 audmux: audmux@83fd0000 {
520 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
521 reg = <0x83fd0000 0x4000>;
522 clocks = <&clks IMX5_CLK_DUMMY>;
523 clock-names = "audmux";
527 weim: weim@83fda000 {
528 #address-cells = <2>;
530 compatible = "fsl,imx51-weim";
531 reg = <0x83fda000 0x1000>;
532 clocks = <&clks IMX5_CLK_EMI_SLOW_GATE>;
534 0 0 0xb0000000 0x08000000
535 1 0 0xb8000000 0x08000000
536 2 0 0xc0000000 0x08000000
537 3 0 0xc8000000 0x04000000
538 4 0 0xcc000000 0x02000000
539 5 0 0xce000000 0x02000000
545 #address-cells = <1>;
547 compatible = "fsl,imx51-nand";
548 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
550 clocks = <&clks IMX5_CLK_NFC_GATE>;
554 pata: pata@83fe0000 {
555 compatible = "fsl,imx51-pata", "fsl,imx27-pata";
556 reg = <0x83fe0000 0x4000>;
558 clocks = <&clks IMX5_CLK_PATA_GATE>;
563 #sound-dai-cells = <0>;
564 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
565 reg = <0x83fe8000 0x4000>;
567 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>,
568 <&clks IMX5_CLK_SSI3_ROOT_GATE>;
569 clock-names = "ipg", "baud";
570 dmas = <&sdma 46 0 0>,
572 dma-names = "rx", "tx";
573 fsl,fifo-depth = <15>;
577 fec: ethernet@83fec000 {
578 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
579 reg = <0x83fec000 0x4000>;
581 clocks = <&clks IMX5_CLK_FEC_GATE>,
582 <&clks IMX5_CLK_FEC_GATE>,
583 <&clks IMX5_CLK_FEC_GATE>;
584 clock-names = "ipg", "ahb", "ptp";