2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include "skeleton.dtsi"
14 #include "imx51-pinfunc.h"
15 #include <dt-bindings/clock/imx5-clock.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/input/input.h>
18 #include <dt-bindings/interrupt-controller/irq.h>
40 tzic: tz-interrupt-controller@e0000000 {
41 compatible = "fsl,imx51-tzic", "fsl,tzic";
43 #interrupt-cells = <1>;
44 reg = <0xe0000000 0x4000>;
52 compatible = "fsl,imx-ckil", "fixed-clock";
53 clock-frequency = <32768>;
57 compatible = "fsl,imx-ckih1", "fixed-clock";
58 clock-frequency = <0>;
62 compatible = "fsl,imx-ckih2", "fixed-clock";
63 clock-frequency = <0>;
67 compatible = "fsl,imx-osc", "fixed-clock";
68 clock-frequency = <24000000>;
77 compatible = "arm,cortex-a8";
79 clock-latency = <62500>;
80 clocks = <&clks IMX5_CLK_CPU_PODF>;
87 voltage-tolerance = <5>;
94 compatible = "simple-bus";
97 compatible = "usb-nop-xceiv";
99 clocks = <&clks IMX5_CLK_USB_PHY_GATE>;
100 clock-names = "main_clk";
105 #address-cells = <1>;
107 compatible = "simple-bus";
108 interrupt-parent = <&tzic>;
111 iram: iram@1ffe0000 {
112 compatible = "mmio-sram";
113 reg = <0x1ffe0000 0x20000>;
118 compatible = "fsl,imx51-ipu";
119 reg = <0x40000000 0x20000000>;
120 interrupts = <11 10>;
121 clocks = <&clks IMX5_CLK_IPU_GATE>,
122 <&clks IMX5_CLK_IPU_DI0_GATE>,
123 <&clks IMX5_CLK_IPU_DI1_GATE>;
124 clock-names = "bus", "di0", "di1";
128 aips@70000000 { /* AIPS1 */
129 compatible = "fsl,aips-bus", "simple-bus";
130 #address-cells = <1>;
132 reg = <0x70000000 0x10000000>;
136 compatible = "fsl,spba-bus", "simple-bus";
137 #address-cells = <1>;
139 reg = <0x70000000 0x40000>;
142 esdhc1: esdhc@70004000 {
143 compatible = "fsl,imx51-esdhc";
144 reg = <0x70004000 0x4000>;
146 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
147 <&clks IMX5_CLK_DUMMY>,
148 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
149 clock-names = "ipg", "ahb", "per";
153 esdhc2: esdhc@70008000 {
154 compatible = "fsl,imx51-esdhc";
155 reg = <0x70008000 0x4000>;
157 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
158 <&clks IMX5_CLK_DUMMY>,
159 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
160 clock-names = "ipg", "ahb", "per";
165 uart3: serial@7000c000 {
166 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
167 reg = <0x7000c000 0x4000>;
169 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
170 <&clks IMX5_CLK_UART3_PER_GATE>;
171 clock-names = "ipg", "per";
175 ecspi1: ecspi@70010000 {
176 #address-cells = <1>;
178 compatible = "fsl,imx51-ecspi";
179 reg = <0x70010000 0x4000>;
181 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
182 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
183 clock-names = "ipg", "per";
188 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
189 reg = <0x70014000 0x4000>;
191 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
192 dmas = <&sdma 24 1 0>,
194 dma-names = "rx", "tx";
195 fsl,fifo-depth = <15>;
196 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
200 esdhc3: esdhc@70020000 {
201 compatible = "fsl,imx51-esdhc";
202 reg = <0x70020000 0x4000>;
204 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
205 <&clks IMX5_CLK_DUMMY>,
206 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
207 clock-names = "ipg", "ahb", "per";
212 esdhc4: esdhc@70024000 {
213 compatible = "fsl,imx51-esdhc";
214 reg = <0x70024000 0x4000>;
216 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
217 <&clks IMX5_CLK_DUMMY>,
218 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
219 clock-names = "ipg", "ahb", "per";
225 usbotg: usb@73f80000 {
226 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
227 reg = <0x73f80000 0x0200>;
229 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
230 fsl,usbmisc = <&usbmisc 0>;
231 fsl,usbphy = <&usbphy0>;
235 usbh1: usb@73f80200 {
236 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
237 reg = <0x73f80200 0x0200>;
239 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
240 fsl,usbmisc = <&usbmisc 1>;
244 usbh2: usb@73f80400 {
245 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
246 reg = <0x73f80400 0x0200>;
248 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
249 fsl,usbmisc = <&usbmisc 2>;
253 usbh3: usb@73f80600 {
254 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
255 reg = <0x73f80600 0x0200>;
257 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
258 fsl,usbmisc = <&usbmisc 3>;
262 usbmisc: usbmisc@73f80800 {
264 compatible = "fsl,imx51-usbmisc";
265 reg = <0x73f80800 0x200>;
266 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
269 gpio1: gpio@73f84000 {
270 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
271 reg = <0x73f84000 0x4000>;
272 interrupts = <50 51>;
275 interrupt-controller;
276 #interrupt-cells = <2>;
279 gpio2: gpio@73f88000 {
280 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
281 reg = <0x73f88000 0x4000>;
282 interrupts = <52 53>;
285 interrupt-controller;
286 #interrupt-cells = <2>;
289 gpio3: gpio@73f8c000 {
290 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
291 reg = <0x73f8c000 0x4000>;
292 interrupts = <54 55>;
295 interrupt-controller;
296 #interrupt-cells = <2>;
299 gpio4: gpio@73f90000 {
300 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
301 reg = <0x73f90000 0x4000>;
302 interrupts = <56 57>;
305 interrupt-controller;
306 #interrupt-cells = <2>;
310 compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
311 reg = <0x73f94000 0x4000>;
313 clocks = <&clks IMX5_CLK_DUMMY>;
317 wdog1: wdog@73f98000 {
318 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
319 reg = <0x73f98000 0x4000>;
321 clocks = <&clks IMX5_CLK_DUMMY>;
324 wdog2: wdog@73f9c000 {
325 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
326 reg = <0x73f9c000 0x4000>;
328 clocks = <&clks IMX5_CLK_DUMMY>;
332 gpt: timer@73fa0000 {
333 compatible = "fsl,imx51-gpt", "fsl,imx31-gpt";
334 reg = <0x73fa0000 0x4000>;
336 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
337 <&clks IMX5_CLK_GPT_HF_GATE>;
338 clock-names = "ipg", "per";
341 iomuxc: iomuxc@73fa8000 {
342 compatible = "fsl,imx51-iomuxc";
343 reg = <0x73fa8000 0x4000>;
348 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
349 reg = <0x73fb4000 0x4000>;
350 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
351 <&clks IMX5_CLK_PWM1_HF_GATE>;
352 clock-names = "ipg", "per";
358 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
359 reg = <0x73fb8000 0x4000>;
360 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
361 <&clks IMX5_CLK_PWM2_HF_GATE>;
362 clock-names = "ipg", "per";
366 uart1: serial@73fbc000 {
367 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
368 reg = <0x73fbc000 0x4000>;
370 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
371 <&clks IMX5_CLK_UART1_PER_GATE>;
372 clock-names = "ipg", "per";
376 uart2: serial@73fc0000 {
377 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
378 reg = <0x73fc0000 0x4000>;
380 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
381 <&clks IMX5_CLK_UART2_PER_GATE>;
382 clock-names = "ipg", "per";
387 compatible = "fsl,imx51-src";
388 reg = <0x73fd0000 0x4000>;
393 compatible = "fsl,imx51-ccm";
394 reg = <0x73fd4000 0x4000>;
395 interrupts = <0 71 0x04 0 72 0x04>;
400 aips@80000000 { /* AIPS2 */
401 compatible = "fsl,aips-bus", "simple-bus";
402 #address-cells = <1>;
404 reg = <0x80000000 0x10000000>;
408 compatible = "fsl,imx51-iim", "fsl,imx27-iim";
409 reg = <0x83f98000 0x4000>;
411 clocks = <&clks IMX5_CLK_IIM_GATE>;
414 owire: owire@83fa4000 {
415 compatible = "fsl,imx51-owire", "fsl,imx21-owire";
416 reg = <0x83fa4000 0x4000>;
418 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
422 ecspi2: ecspi@83fac000 {
423 #address-cells = <1>;
425 compatible = "fsl,imx51-ecspi";
426 reg = <0x83fac000 0x4000>;
428 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
429 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
430 clock-names = "ipg", "per";
434 sdma: sdma@83fb0000 {
435 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
436 reg = <0x83fb0000 0x4000>;
438 clocks = <&clks IMX5_CLK_SDMA_GATE>,
439 <&clks IMX5_CLK_SDMA_GATE>;
440 clock-names = "ipg", "ahb";
442 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
445 cspi: cspi@83fc0000 {
446 #address-cells = <1>;
448 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
449 reg = <0x83fc0000 0x4000>;
451 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
452 <&clks IMX5_CLK_CSPI_IPG_GATE>;
453 clock-names = "ipg", "per";
458 #address-cells = <1>;
460 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
461 reg = <0x83fc4000 0x4000>;
463 clocks = <&clks IMX5_CLK_I2C2_GATE>;
468 #address-cells = <1>;
470 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
471 reg = <0x83fc8000 0x4000>;
473 clocks = <&clks IMX5_CLK_I2C1_GATE>;
478 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
479 reg = <0x83fcc000 0x4000>;
481 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
482 dmas = <&sdma 28 0 0>,
484 dma-names = "rx", "tx";
485 fsl,fifo-depth = <15>;
486 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
490 audmux: audmux@83fd0000 {
491 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
492 reg = <0x83fd0000 0x4000>;
493 clocks = <&clks IMX5_CLK_DUMMY>;
494 clock-names = "audmux";
498 weim: weim@83fda000 {
499 #address-cells = <2>;
501 compatible = "fsl,imx51-weim";
502 reg = <0x83fda000 0x1000>;
503 clocks = <&clks IMX5_CLK_EMI_SLOW_GATE>;
505 0 0 0xb0000000 0x08000000
506 1 0 0xb8000000 0x08000000
507 2 0 0xc0000000 0x08000000
508 3 0 0xc8000000 0x04000000
509 4 0 0xcc000000 0x02000000
510 5 0 0xce000000 0x02000000
516 compatible = "fsl,imx51-nand";
517 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
519 clocks = <&clks IMX5_CLK_NFC_GATE>;
523 pata: pata@83fe0000 {
524 compatible = "fsl,imx51-pata", "fsl,imx27-pata";
525 reg = <0x83fe0000 0x4000>;
527 clocks = <&clks IMX5_CLK_PATA_GATE>;
532 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
533 reg = <0x83fe8000 0x4000>;
535 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>;
536 dmas = <&sdma 46 0 0>,
538 dma-names = "rx", "tx";
539 fsl,fifo-depth = <15>;
540 fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
544 fec: ethernet@83fec000 {
545 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
546 reg = <0x83fec000 0x4000>;
548 clocks = <&clks IMX5_CLK_FEC_GATE>,
549 <&clks IMX5_CLK_FEC_GATE>,
550 <&clks IMX5_CLK_FEC_GATE>;
551 clock-names = "ipg", "ahb", "ptp";