arch/arm/boot/dts/imx51.dtsi

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include "skeleton.dtsi"
  14 #include "imx51-pinfunc.h"
  15 #include <dt-bindings/clock/imx5-clock.h>
  16 #include <dt-bindings/gpio/gpio.h>
  17 #include <dt-bindings/input/input.h>
  18 #include <dt-bindings/interrupt-controller/irq.h>
  19
  20 / {
  21         aliases {
  22                 gpio0 = &gpio1;
  23                 gpio1 = &gpio2;
  24                 gpio2 = &gpio3;
  25                 gpio3 = &gpio4;
  26                 i2c0 = &i2c1;
  27                 i2c1 = &i2c2;
  28                 mmc0 = &esdhc1;
  29                 mmc1 = &esdhc2;
  30                 mmc2 = &esdhc3;
  31                 mmc3 = &esdhc4;
  32                 serial0 = &uart1;
  33                 serial1 = &uart2;
  34                 serial2 = &uart3;
  35                 spi0 = &ecspi1;
  36                 spi1 = &ecspi2;
  37                 spi2 = &cspi;
  38         };
  39
  40         tzic: tz-interrupt-controller@e0000000 {
  41                 compatible = "fsl,imx51-tzic", "fsl,tzic";
  42                 interrupt-controller;
  43                 #interrupt-cells = <1>;
  44                 reg = <0xe0000000 0x4000>;
  45         };
  46
  47         clocks {
  48                 #address-cells = <1>;
  49                 #size-cells = <0>;
  50
  51                 ckil {
  52                         compatible = "fsl,imx-ckil", "fixed-clock";
  53                         clock-frequency = <32768>;
  54                 };
  55
  56                 ckih1 {
  57                         compatible = "fsl,imx-ckih1", "fixed-clock";
  58                         clock-frequency = <0>;
  59                 };
  60
  61                 ckih2 {
  62                         compatible = "fsl,imx-ckih2", "fixed-clock";
  63                         clock-frequency = <0>;
  64                 };
  65
  66                 osc {
  67                         compatible = "fsl,imx-osc", "fixed-clock";
  68                         clock-frequency = <24000000>;
  69                 };
  70         };
  71
  72         cpus {
  73                 #address-cells = <1>;
  74                 #size-cells = <0>;
  75                 cpu: cpu@0 {
  76                         device_type = "cpu";
  77                         compatible = "arm,cortex-a8";
  78                         reg = <0>;
  79                         clock-latency = <62500>;
  80                         clocks = <&clks IMX5_CLK_CPU_PODF>;
  81                         clock-names = "cpu";
  82                         operating-points = <
  83                                 166000  1000000
  84                                 600000  1050000
  85                                 800000  1100000
  86                         >;
  87                         voltage-tolerance = <5>;
  88                 };
  89         };
  90
  91         usbphy {
  92                 #address-cells = <1>;
  93                 #size-cells = <0>;
  94                 compatible = "simple-bus";
  95
  96                 usbphy0: usbphy@0 {
  97                         compatible = "usb-nop-xceiv";
  98                         reg = <0>;
  99                         clocks = <&clks IMX5_CLK_USB_PHY_GATE>;
 100                         clock-names = "main_clk";
 101                 };
 102         };
 103
 104         soc {
 105                 #address-cells = <1>;
 106                 #size-cells = <1>;
 107                 compatible = "simple-bus";
 108                 interrupt-parent = <&tzic>;
 109                 ranges;
 110
 111                 iram: iram@1ffe0000 {
 112                         compatible = "mmio-sram";
 113                         reg = <0x1ffe0000 0x20000>;
 114                 };
 115
 116                 ipu: ipu@40000000 {
 117                         #crtc-cells = <1>;
 118                         compatible = "fsl,imx51-ipu";
 119                         reg = <0x40000000 0x20000000>;
 120                         interrupts = <11 10>;
 121                         clocks = <&clks IMX5_CLK_IPU_GATE>,
 122                                  <&clks IMX5_CLK_IPU_DI0_GATE>,
 123                                  <&clks IMX5_CLK_IPU_DI1_GATE>;
 124                         clock-names = "bus", "di0", "di1";
 125                         resets = <&src 2>;
 126                 };
 127
 128                 aips@70000000 { /* AIPS1 */
 129                         compatible = "fsl,aips-bus", "simple-bus";
 130                         #address-cells = <1>;
 131                         #size-cells = <1>;
 132                         reg = <0x70000000 0x10000000>;
 133                         ranges;
 134
 135                         spba@70000000 {
 136                                 compatible = "fsl,spba-bus", "simple-bus";
 137                                 #address-cells = <1>;
 138                                 #size-cells = <1>;
 139                                 reg = <0x70000000 0x40000>;
 140                                 ranges;
 141
 142                                 esdhc1: esdhc@70004000 {
 143                                         compatible = "fsl,imx51-esdhc";
 144                                         reg = <0x70004000 0x4000>;
 145                                         interrupts = <1>;
 146                                         clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
 147                                                  <&clks IMX5_CLK_DUMMY>,
 148                                                  <&clks IMX5_CLK_ESDHC1_PER_GATE>;
 149                                         clock-names = "ipg", "ahb", "per";
 150                                         status = "disabled";
 151                                 };
 152
 153                                 esdhc2: esdhc@70008000 {
 154                                         compatible = "fsl,imx51-esdhc";
 155                                         reg = <0x70008000 0x4000>;
 156                                         interrupts = <2>;
 157                                         clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
 158                                                  <&clks IMX5_CLK_DUMMY>,
 159                                                  <&clks IMX5_CLK_ESDHC2_PER_GATE>;
 160                                         clock-names = "ipg", "ahb", "per";
 161                                         bus-width = <4>;
 162                                         status = "disabled";
 163                                 };
 164
 165                                 uart3: serial@7000c000 {
 166                                         compatible = "fsl,imx51-uart", "fsl,imx21-uart";
 167                                         reg = <0x7000c000 0x4000>;
 168                                         interrupts = <33>;
 169                                         clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
 170                                                  <&clks IMX5_CLK_UART3_PER_GATE>;
 171                                         clock-names = "ipg", "per";
 172                                         status = "disabled";
 173                                 };
 174
 175                                 ecspi1: ecspi@70010000 {
 176                                         #address-cells = <1>;
 177                                         #size-cells = <0>;
 178                                         compatible = "fsl,imx51-ecspi";
 179                                         reg = <0x70010000 0x4000>;
 180                                         interrupts = <36>;
 181                                         clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
 182                                                  <&clks IMX5_CLK_ECSPI1_PER_GATE>;
 183                                         clock-names = "ipg", "per";
 184                                         status = "disabled";
 185                                 };
 186
 187                                 ssi2: ssi@70014000 {
 188                                         compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
 189                                         reg = <0x70014000 0x4000>;
 190                                         interrupts = <30>;
 191                                         clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
 192                                         dmas = <&sdma 24 1 0>,
 193                                                <&sdma 25 1 0>;
 194                                         dma-names = "rx", "tx";
 195                                         fsl,fifo-depth = <15>;
 196                                         fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
 197                                         status = "disabled";
 198                                 };
 199
 200                                 esdhc3: esdhc@70020000 {
 201                                         compatible = "fsl,imx51-esdhc";
 202                                         reg = <0x70020000 0x4000>;
 203                                         interrupts = <3>;
 204                                         clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
 205                                                  <&clks IMX5_CLK_DUMMY>,
 206                                                  <&clks IMX5_CLK_ESDHC3_PER_GATE>;
 207                                         clock-names = "ipg", "ahb", "per";
 208                                         bus-width = <4>;
 209                                         status = "disabled";
 210                                 };
 211
 212                                 esdhc4: esdhc@70024000 {
 213                                         compatible = "fsl,imx51-esdhc";
 214                                         reg = <0x70024000 0x4000>;
 215                                         interrupts = <4>;
 216                                         clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
 217                                                  <&clks IMX5_CLK_DUMMY>,
 218                                                  <&clks IMX5_CLK_ESDHC4_PER_GATE>;
 219                                         clock-names = "ipg", "ahb", "per";
 220                                         bus-width = <4>;
 221                                         status = "disabled";
 222                                 };
 223                         };
 224
 225                         usbotg: usb@73f80000 {
 226                                 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
 227                                 reg = <0x73f80000 0x0200>;
 228                                 interrupts = <18>;
 229                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
 230                                 fsl,usbmisc = <&usbmisc 0>;
 231                                 fsl,usbphy = <&usbphy0>;
 232                                 status = "disabled";
 233                         };
 234
 235                         usbh1: usb@73f80200 {
 236                                 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
 237                                 reg = <0x73f80200 0x0200>;
 238                                 interrupts = <14>;
 239                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
 240                                 fsl,usbmisc = <&usbmisc 1>;
 241                                 status = "disabled";
 242                         };
 243
 244                         usbh2: usb@73f80400 {
 245                                 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
 246                                 reg = <0x73f80400 0x0200>;
 247                                 interrupts = <16>;
 248                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
 249                                 fsl,usbmisc = <&usbmisc 2>;
 250                                 status = "disabled";
 251                         };
 252
 253                         usbh3: usb@73f80600 {
 254                                 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
 255                                 reg = <0x73f80600 0x0200>;
 256                                 interrupts = <17>;
 257                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
 258                                 fsl,usbmisc = <&usbmisc 3>;
 259                                 status = "disabled";
 260                         };
 261
 262                         usbmisc: usbmisc@73f80800 {
 263                                 #index-cells = <1>;
 264                                 compatible = "fsl,imx51-usbmisc";
 265                                 reg = <0x73f80800 0x200>;
 266                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
 267                         };
 268
 269                         gpio1: gpio@73f84000 {
 270                                 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
 271                                 reg = <0x73f84000 0x4000>;
 272                                 interrupts = <50 51>;
 273                                 gpio-controller;
 274                                 #gpio-cells = <2>;
 275                                 interrupt-controller;
 276                                 #interrupt-cells = <2>;
 277                         };
 278
 279                         gpio2: gpio@73f88000 {
 280                                 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
 281                                 reg = <0x73f88000 0x4000>;
 282                                 interrupts = <52 53>;
 283                                 gpio-controller;
 284                                 #gpio-cells = <2>;
 285                                 interrupt-controller;
 286                                 #interrupt-cells = <2>;
 287                         };
 288
 289                         gpio3: gpio@73f8c000 {
 290                                 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
 291                                 reg = <0x73f8c000 0x4000>;
 292                                 interrupts = <54 55>;
 293                                 gpio-controller;
 294                                 #gpio-cells = <2>;
 295                                 interrupt-controller;
 296                                 #interrupt-cells = <2>;
 297                         };
 298
 299                         gpio4: gpio@73f90000 {
 300                                 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
 301                                 reg = <0x73f90000 0x4000>;
 302                                 interrupts = <56 57>;
 303                                 gpio-controller;
 304                                 #gpio-cells = <2>;
 305                                 interrupt-controller;
 306                                 #interrupt-cells = <2>;
 307                         };
 308
 309                         kpp: kpp@73f94000 {
 310                                 compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
 311                                 reg = <0x73f94000 0x4000>;
 312                                 interrupts = <60>;
 313                                 clocks = <&clks IMX5_CLK_DUMMY>;
 314                                 status = "disabled";
 315                         };
 316
 317                         wdog1: wdog@73f98000 {
 318                                 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
 319                                 reg = <0x73f98000 0x4000>;
 320                                 interrupts = <58>;
 321                                 clocks = <&clks IMX5_CLK_DUMMY>;
 322                         };
 323
 324                         wdog2: wdog@73f9c000 {
 325                                 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
 326                                 reg = <0x73f9c000 0x4000>;
 327                                 interrupts = <59>;
 328                                 clocks = <&clks IMX5_CLK_DUMMY>;
 329                                 status = "disabled";
 330                         };
 331
 332                         gpt: timer@73fa0000 {
 333                                 compatible = "fsl,imx51-gpt", "fsl,imx31-gpt";
 334                                 reg = <0x73fa0000 0x4000>;
 335                                 interrupts = <39>;
 336                                 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
 337                                          <&clks IMX5_CLK_GPT_HF_GATE>;
 338                                 clock-names = "ipg", "per";
 339                         };
 340
 341                         iomuxc: iomuxc@73fa8000 {
 342                                 compatible = "fsl,imx51-iomuxc";
 343                                 reg = <0x73fa8000 0x4000>;
 344                         };
 345
 346                         pwm1: pwm@73fb4000 {
 347                                 #pwm-cells = <2>;
 348                                 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
 349                                 reg = <0x73fb4000 0x4000>;
 350                                 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
 351                                          <&clks IMX5_CLK_PWM1_HF_GATE>;
 352                                 clock-names = "ipg", "per";
 353                                 interrupts = <61>;
 354                         };
 355
 356                         pwm2: pwm@73fb8000 {
 357                                 #pwm-cells = <2>;
 358                                 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
 359                                 reg = <0x73fb8000 0x4000>;
 360                                 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
 361                                          <&clks IMX5_CLK_PWM2_HF_GATE>;
 362                                 clock-names = "ipg", "per";
 363                                 interrupts = <94>;
 364                         };
 365
 366                         uart1: serial@73fbc000 {
 367                                 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
 368                                 reg = <0x73fbc000 0x4000>;
 369                                 interrupts = <31>;
 370                                 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
 371                                          <&clks IMX5_CLK_UART1_PER_GATE>;
 372                                 clock-names = "ipg", "per";
 373                                 status = "disabled";
 374                         };
 375
 376                         uart2: serial@73fc0000 {
 377                                 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
 378                                 reg = <0x73fc0000 0x4000>;
 379                                 interrupts = <32>;
 380                                 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
 381                                          <&clks IMX5_CLK_UART2_PER_GATE>;
 382                                 clock-names = "ipg", "per";
 383                                 status = "disabled";
 384                         };
 385
 386                         src: src@73fd0000 {
 387                                 compatible = "fsl,imx51-src";
 388                                 reg = <0x73fd0000 0x4000>;
 389                                 #reset-cells = <1>;
 390                         };
 391
 392                         clks: ccm@73fd4000{
 393                                 compatible = "fsl,imx51-ccm";
 394                                 reg = <0x73fd4000 0x4000>;
 395                                 interrupts = <0 71 0x04 0 72 0x04>;
 396                                 #clock-cells = <1>;
 397                         };
 398                 };
 399
 400                 aips@80000000 { /* AIPS2 */
 401                         compatible = "fsl,aips-bus", "simple-bus";
 402                         #address-cells = <1>;
 403                         #size-cells = <1>;
 404                         reg = <0x80000000 0x10000000>;
 405                         ranges;
 406
 407                         iim: iim@83f98000 {
 408                                 compatible = "fsl,imx51-iim", "fsl,imx27-iim";
 409                                 reg = <0x83f98000 0x4000>;
 410                                 interrupts = <69>;
 411                                 clocks = <&clks IMX5_CLK_IIM_GATE>;
 412                         };
 413
 414                         owire: owire@83fa4000 {
 415                                 compatible = "fsl,imx51-owire", "fsl,imx21-owire";
 416                                 reg = <0x83fa4000 0x4000>;
 417                                 interrupts = <88>;
 418                                 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
 419                                 status = "disabled";
 420                         };
 421
 422                         ecspi2: ecspi@83fac000 {
 423                                 #address-cells = <1>;
 424                                 #size-cells = <0>;
 425                                 compatible = "fsl,imx51-ecspi";
 426                                 reg = <0x83fac000 0x4000>;
 427                                 interrupts = <37>;
 428                                 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
 429                                          <&clks IMX5_CLK_ECSPI2_PER_GATE>;
 430                                 clock-names = "ipg", "per";
 431                                 status = "disabled";
 432                         };
 433
 434                         sdma: sdma@83fb0000 {
 435                                 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
 436                                 reg = <0x83fb0000 0x4000>;
 437                                 interrupts = <6>;
 438                                 clocks = <&clks IMX5_CLK_SDMA_GATE>,
 439                                          <&clks IMX5_CLK_SDMA_GATE>;
 440                                 clock-names = "ipg", "ahb";
 441                                 #dma-cells = <3>;
 442                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
 443                         };
 444
 445                         cspi: cspi@83fc0000 {
 446                                 #address-cells = <1>;
 447                                 #size-cells = <0>;
 448                                 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
 449                                 reg = <0x83fc0000 0x4000>;
 450                                 interrupts = <38>;
 451                                 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
 452                                          <&clks IMX5_CLK_CSPI_IPG_GATE>;
 453                                 clock-names = "ipg", "per";
 454                                 status = "disabled";
 455                         };
 456
 457                         i2c2: i2c@83fc4000 {
 458                                 #address-cells = <1>;
 459                                 #size-cells = <0>;
 460                                 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
 461                                 reg = <0x83fc4000 0x4000>;
 462                                 interrupts = <63>;
 463                                 clocks = <&clks IMX5_CLK_I2C2_GATE>;
 464                                 status = "disabled";
 465                         };
 466
 467                         i2c1: i2c@83fc8000 {
 468                                 #address-cells = <1>;
 469                                 #size-cells = <0>;
 470                                 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
 471                                 reg = <0x83fc8000 0x4000>;
 472                                 interrupts = <62>;
 473                                 clocks = <&clks IMX5_CLK_I2C1_GATE>;
 474                                 status = "disabled";
 475                         };
 476
 477                         ssi1: ssi@83fcc000 {
 478                                 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
 479                                 reg = <0x83fcc000 0x4000>;
 480                                 interrupts = <29>;
 481                                 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
 482                                 dmas = <&sdma 28 0 0>,
 483                                        <&sdma 29 0 0>;
 484                                 dma-names = "rx", "tx";
 485                                 fsl,fifo-depth = <15>;
 486                                 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
 487                                 status = "disabled";
 488                         };
 489
 490                         audmux: audmux@83fd0000 {
 491                                 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
 492                                 reg = <0x83fd0000 0x4000>;
 493                                 clocks = <&clks IMX5_CLK_DUMMY>;
 494                                 clock-names = "audmux";
 495                                 status = "disabled";
 496                         };
 497
 498                         weim: weim@83fda000 {
 499                                 #address-cells = <2>;
 500                                 #size-cells = <1>;
 501                                 compatible = "fsl,imx51-weim";
 502                                 reg = <0x83fda000 0x1000>;
 503                                 clocks = <&clks IMX5_CLK_EMI_SLOW_GATE>;
 504                                 ranges = <
 505                                         0 0 0xb0000000 0x08000000
 506                                         1 0 0xb8000000 0x08000000
 507                                         2 0 0xc0000000 0x08000000
 508                                         3 0 0xc8000000 0x04000000
 509                                         4 0 0xcc000000 0x02000000
 510                                         5 0 0xce000000 0x02000000
 511                                 >;
 512                                 status = "disabled";
 513                         };
 514
 515                         nfc: nand@83fdb000 {
 516                                 compatible = "fsl,imx51-nand";
 517                                 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
 518                                 interrupts = <8>;
 519                                 clocks = <&clks IMX5_CLK_NFC_GATE>;
 520                                 status = "disabled";
 521                         };
 522
 523                         pata: pata@83fe0000 {
 524                                 compatible = "fsl,imx51-pata", "fsl,imx27-pata";
 525                                 reg = <0x83fe0000 0x4000>;
 526                                 interrupts = <70>;
 527                                 clocks = <&clks IMX5_CLK_PATA_GATE>;
 528                                 status = "disabled";
 529                         };
 530
 531                         ssi3: ssi@83fe8000 {
 532                                 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
 533                                 reg = <0x83fe8000 0x4000>;
 534                                 interrupts = <96>;
 535                                 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>;
 536                                 dmas = <&sdma 46 0 0>,
 537                                        <&sdma 47 0 0>;
 538                                 dma-names = "rx", "tx";
 539                                 fsl,fifo-depth = <15>;
 540                                 fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
 541                                 status = "disabled";
 542                         };
 543
 544                         fec: ethernet@83fec000 {
 545                                 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
 546                                 reg = <0x83fec000 0x4000>;
 547                                 interrupts = <87>;
 548                                 clocks = <&clks IMX5_CLK_FEC_GATE>,
 549                                          <&clks IMX5_CLK_FEC_GATE>,
 550                                          <&clks IMX5_CLK_FEC_GATE>;
 551                                 clock-names = "ipg", "ahb", "ptp";
 552                                 status = "disabled";
 553                         };
 554                 };
 555         };
 556 };