2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include "skeleton.dtsi"
14 #include "imx51-pinfunc.h"
15 #include <dt-bindings/clock/imx5-clock.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/input/input.h>
18 #include <dt-bindings/interrupt-controller/irq.h>
40 tzic: tz-interrupt-controller@e0000000 {
41 compatible = "fsl,imx51-tzic", "fsl,tzic";
43 #interrupt-cells = <1>;
44 reg = <0xe0000000 0x4000>;
52 compatible = "fsl,imx-ckil", "fixed-clock";
53 clock-frequency = <32768>;
57 compatible = "fsl,imx-ckih1", "fixed-clock";
58 clock-frequency = <0>;
62 compatible = "fsl,imx-ckih2", "fixed-clock";
63 clock-frequency = <0>;
67 compatible = "fsl,imx-osc", "fixed-clock";
68 clock-frequency = <24000000>;
77 compatible = "arm,cortex-a8";
79 clock-latency = <62500>;
80 clocks = <&clks IMX5_CLK_CPU_PODF>;
87 voltage-tolerance = <5>;
94 compatible = "simple-bus";
97 compatible = "usb-nop-xceiv";
99 clocks = <&clks IMX5_CLK_USB_PHY_GATE>;
100 clock-names = "main_clk";
105 compatible = "fsl,imx-display-subsystem";
106 ports = <&ipu_di0>, <&ipu_di1>;
110 #address-cells = <1>;
112 compatible = "simple-bus";
113 interrupt-parent = <&tzic>;
116 iram: iram@1ffe0000 {
117 compatible = "mmio-sram";
118 reg = <0x1ffe0000 0x20000>;
122 #address-cells = <1>;
124 compatible = "fsl,imx51-ipu";
125 reg = <0x40000000 0x20000000>;
126 interrupts = <11 10>;
127 clocks = <&clks IMX5_CLK_IPU_GATE>,
128 <&clks IMX5_CLK_IPU_DI0_GATE>,
129 <&clks IMX5_CLK_IPU_DI1_GATE>;
130 clock-names = "bus", "di0", "di1";
136 ipu_di0_disp0: endpoint {
143 ipu_di1_disp1: endpoint {
148 aips@70000000 { /* AIPS1 */
149 compatible = "fsl,aips-bus", "simple-bus";
150 #address-cells = <1>;
152 reg = <0x70000000 0x10000000>;
156 compatible = "fsl,spba-bus", "simple-bus";
157 #address-cells = <1>;
159 reg = <0x70000000 0x40000>;
162 esdhc1: esdhc@70004000 {
163 compatible = "fsl,imx51-esdhc";
164 reg = <0x70004000 0x4000>;
166 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
167 <&clks IMX5_CLK_DUMMY>,
168 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
169 clock-names = "ipg", "ahb", "per";
173 esdhc2: esdhc@70008000 {
174 compatible = "fsl,imx51-esdhc";
175 reg = <0x70008000 0x4000>;
177 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
178 <&clks IMX5_CLK_DUMMY>,
179 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
180 clock-names = "ipg", "ahb", "per";
185 uart3: serial@7000c000 {
186 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
187 reg = <0x7000c000 0x4000>;
189 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
190 <&clks IMX5_CLK_UART3_PER_GATE>;
191 clock-names = "ipg", "per";
195 ecspi1: ecspi@70010000 {
196 #address-cells = <1>;
198 compatible = "fsl,imx51-ecspi";
199 reg = <0x70010000 0x4000>;
201 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
202 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
203 clock-names = "ipg", "per";
208 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
209 reg = <0x70014000 0x4000>;
211 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
212 dmas = <&sdma 24 1 0>,
214 dma-names = "rx", "tx";
215 fsl,fifo-depth = <15>;
216 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
220 esdhc3: esdhc@70020000 {
221 compatible = "fsl,imx51-esdhc";
222 reg = <0x70020000 0x4000>;
224 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
225 <&clks IMX5_CLK_DUMMY>,
226 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
227 clock-names = "ipg", "ahb", "per";
232 esdhc4: esdhc@70024000 {
233 compatible = "fsl,imx51-esdhc";
234 reg = <0x70024000 0x4000>;
236 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
237 <&clks IMX5_CLK_DUMMY>,
238 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
239 clock-names = "ipg", "ahb", "per";
245 usbotg: usb@73f80000 {
246 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
247 reg = <0x73f80000 0x0200>;
249 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
250 fsl,usbmisc = <&usbmisc 0>;
251 fsl,usbphy = <&usbphy0>;
255 usbh1: usb@73f80200 {
256 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
257 reg = <0x73f80200 0x0200>;
259 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
260 fsl,usbmisc = <&usbmisc 1>;
264 usbh2: usb@73f80400 {
265 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
266 reg = <0x73f80400 0x0200>;
268 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
269 fsl,usbmisc = <&usbmisc 2>;
273 usbh3: usb@73f80600 {
274 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
275 reg = <0x73f80600 0x0200>;
277 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
278 fsl,usbmisc = <&usbmisc 3>;
282 usbmisc: usbmisc@73f80800 {
284 compatible = "fsl,imx51-usbmisc";
285 reg = <0x73f80800 0x200>;
286 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
289 gpio1: gpio@73f84000 {
290 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
291 reg = <0x73f84000 0x4000>;
292 interrupts = <50 51>;
295 interrupt-controller;
296 #interrupt-cells = <2>;
299 gpio2: gpio@73f88000 {
300 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
301 reg = <0x73f88000 0x4000>;
302 interrupts = <52 53>;
305 interrupt-controller;
306 #interrupt-cells = <2>;
309 gpio3: gpio@73f8c000 {
310 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
311 reg = <0x73f8c000 0x4000>;
312 interrupts = <54 55>;
315 interrupt-controller;
316 #interrupt-cells = <2>;
319 gpio4: gpio@73f90000 {
320 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
321 reg = <0x73f90000 0x4000>;
322 interrupts = <56 57>;
325 interrupt-controller;
326 #interrupt-cells = <2>;
330 compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
331 reg = <0x73f94000 0x4000>;
333 clocks = <&clks IMX5_CLK_DUMMY>;
337 wdog1: wdog@73f98000 {
338 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
339 reg = <0x73f98000 0x4000>;
341 clocks = <&clks IMX5_CLK_DUMMY>;
344 wdog2: wdog@73f9c000 {
345 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
346 reg = <0x73f9c000 0x4000>;
348 clocks = <&clks IMX5_CLK_DUMMY>;
352 gpt: timer@73fa0000 {
353 compatible = "fsl,imx51-gpt", "fsl,imx31-gpt";
354 reg = <0x73fa0000 0x4000>;
356 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
357 <&clks IMX5_CLK_GPT_HF_GATE>;
358 clock-names = "ipg", "per";
361 iomuxc: iomuxc@73fa8000 {
362 compatible = "fsl,imx51-iomuxc";
363 reg = <0x73fa8000 0x4000>;
368 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
369 reg = <0x73fb4000 0x4000>;
370 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
371 <&clks IMX5_CLK_PWM1_HF_GATE>;
372 clock-names = "ipg", "per";
378 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
379 reg = <0x73fb8000 0x4000>;
380 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
381 <&clks IMX5_CLK_PWM2_HF_GATE>;
382 clock-names = "ipg", "per";
386 uart1: serial@73fbc000 {
387 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
388 reg = <0x73fbc000 0x4000>;
390 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
391 <&clks IMX5_CLK_UART1_PER_GATE>;
392 clock-names = "ipg", "per";
396 uart2: serial@73fc0000 {
397 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
398 reg = <0x73fc0000 0x4000>;
400 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
401 <&clks IMX5_CLK_UART2_PER_GATE>;
402 clock-names = "ipg", "per";
407 compatible = "fsl,imx51-src";
408 reg = <0x73fd0000 0x4000>;
413 compatible = "fsl,imx51-ccm";
414 reg = <0x73fd4000 0x4000>;
415 interrupts = <0 71 0x04 0 72 0x04>;
420 aips@80000000 { /* AIPS2 */
421 compatible = "fsl,aips-bus", "simple-bus";
422 #address-cells = <1>;
424 reg = <0x80000000 0x10000000>;
428 compatible = "fsl,imx51-iim", "fsl,imx27-iim";
429 reg = <0x83f98000 0x4000>;
431 clocks = <&clks IMX5_CLK_IIM_GATE>;
434 owire: owire@83fa4000 {
435 compatible = "fsl,imx51-owire", "fsl,imx21-owire";
436 reg = <0x83fa4000 0x4000>;
438 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
442 ecspi2: ecspi@83fac000 {
443 #address-cells = <1>;
445 compatible = "fsl,imx51-ecspi";
446 reg = <0x83fac000 0x4000>;
448 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
449 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
450 clock-names = "ipg", "per";
454 sdma: sdma@83fb0000 {
455 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
456 reg = <0x83fb0000 0x4000>;
458 clocks = <&clks IMX5_CLK_SDMA_GATE>,
459 <&clks IMX5_CLK_SDMA_GATE>;
460 clock-names = "ipg", "ahb";
462 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
465 cspi: cspi@83fc0000 {
466 #address-cells = <1>;
468 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
469 reg = <0x83fc0000 0x4000>;
471 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
472 <&clks IMX5_CLK_CSPI_IPG_GATE>;
473 clock-names = "ipg", "per";
478 #address-cells = <1>;
480 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
481 reg = <0x83fc4000 0x4000>;
483 clocks = <&clks IMX5_CLK_I2C2_GATE>;
488 #address-cells = <1>;
490 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
491 reg = <0x83fc8000 0x4000>;
493 clocks = <&clks IMX5_CLK_I2C1_GATE>;
498 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
499 reg = <0x83fcc000 0x4000>;
501 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
502 dmas = <&sdma 28 0 0>,
504 dma-names = "rx", "tx";
505 fsl,fifo-depth = <15>;
506 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
510 audmux: audmux@83fd0000 {
511 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
512 reg = <0x83fd0000 0x4000>;
513 clocks = <&clks IMX5_CLK_DUMMY>;
514 clock-names = "audmux";
518 weim: weim@83fda000 {
519 #address-cells = <2>;
521 compatible = "fsl,imx51-weim";
522 reg = <0x83fda000 0x1000>;
523 clocks = <&clks IMX5_CLK_EMI_SLOW_GATE>;
525 0 0 0xb0000000 0x08000000
526 1 0 0xb8000000 0x08000000
527 2 0 0xc0000000 0x08000000
528 3 0 0xc8000000 0x04000000
529 4 0 0xcc000000 0x02000000
530 5 0 0xce000000 0x02000000
536 compatible = "fsl,imx51-nand";
537 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
539 clocks = <&clks IMX5_CLK_NFC_GATE>;
543 pata: pata@83fe0000 {
544 compatible = "fsl,imx51-pata", "fsl,imx27-pata";
545 reg = <0x83fe0000 0x4000>;
547 clocks = <&clks IMX5_CLK_PATA_GATE>;
552 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
553 reg = <0x83fe8000 0x4000>;
555 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>;
556 dmas = <&sdma 46 0 0>,
558 dma-names = "rx", "tx";
559 fsl,fifo-depth = <15>;
560 fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
564 fec: ethernet@83fec000 {
565 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
566 reg = <0x83fec000 0x4000>;
568 clocks = <&clks IMX5_CLK_FEC_GATE>,
569 <&clks IMX5_CLK_FEC_GATE>,
570 <&clks IMX5_CLK_FEC_GATE>;
571 clock-names = "ipg", "ahb", "ptp";