arch/arm/boot/dts/imx53.dtsi

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include "skeleton.dtsi"
  14 #include "imx53-pinfunc.h"
  15
  16 / {
  17         aliases {
  18                 serial0 = &uart1;
  19                 serial1 = &uart2;
  20                 serial2 = &uart3;
  21                 serial3 = &uart4;
  22                 serial4 = &uart5;
  23                 gpio0 = &gpio1;
  24                 gpio1 = &gpio2;
  25                 gpio2 = &gpio3;
  26                 gpio3 = &gpio4;
  27                 gpio4 = &gpio5;
  28                 gpio5 = &gpio6;
  29                 gpio6 = &gpio7;
  30         };
  31
  32         tzic: tz-interrupt-controller@0fffc000 {
  33                 compatible = "fsl,imx53-tzic", "fsl,tzic";
  34                 interrupt-controller;
  35                 #interrupt-cells = <1>;
  36                 reg = <0x0fffc000 0x4000>;
  37         };
  38
  39         clocks {
  40                 #address-cells = <1>;
  41                 #size-cells = <0>;
  42
  43                 ckil {
  44                         compatible = "fsl,imx-ckil", "fixed-clock";
  45                         clock-frequency = <32768>;
  46                 };
  47
  48                 ckih1 {
  49                         compatible = "fsl,imx-ckih1", "fixed-clock";
  50                         clock-frequency = <22579200>;
  51                 };
  52
  53                 ckih2 {
  54                         compatible = "fsl,imx-ckih2", "fixed-clock";
  55                         clock-frequency = <0>;
  56                 };
  57
  58                 osc {
  59                         compatible = "fsl,imx-osc", "fixed-clock";
  60                         clock-frequency = <24000000>;
  61                 };
  62         };
  63
  64         soc {
  65                 #address-cells = <1>;
  66                 #size-cells = <1>;
  67                 compatible = "simple-bus";
  68                 interrupt-parent = <&tzic>;
  69                 ranges;
  70
  71                 ipu: ipu@18000000 {
  72                         #crtc-cells = <1>;
  73                         compatible = "fsl,imx53-ipu";
  74                         reg = <0x18000000 0x080000000>;
  75                         interrupts = <11 10>;
  76                         clocks = <&clks 59>, <&clks 110>, <&clks 61>;
  77                         clock-names = "bus", "di0", "di1";
  78                         resets = <&src 2>;
  79                 };
  80
  81                 aips@50000000 { /* AIPS1 */
  82                         compatible = "fsl,aips-bus", "simple-bus";
  83                         #address-cells = <1>;
  84                         #size-cells = <1>;
  85                         reg = <0x50000000 0x10000000>;
  86                         ranges;
  87
  88                         spba@50000000 {
  89                                 compatible = "fsl,spba-bus", "simple-bus";
  90                                 #address-cells = <1>;
  91                                 #size-cells = <1>;
  92                                 reg = <0x50000000 0x40000>;
  93                                 ranges;
  94
  95                                 esdhc1: esdhc@50004000 {
  96                                         compatible = "fsl,imx53-esdhc";
  97                                         reg = <0x50004000 0x4000>;
  98                                         interrupts = <1>;
  99                                         clocks = <&clks 44>, <&clks 0>, <&clks 71>;
 100                                         clock-names = "ipg", "ahb", "per";
 101                                         bus-width = <4>;
 102                                         status = "disabled";
 103                                 };
 104
 105                                 esdhc2: esdhc@50008000 {
 106                                         compatible = "fsl,imx53-esdhc";
 107                                         reg = <0x50008000 0x4000>;
 108                                         interrupts = <2>;
 109                                         clocks = <&clks 45>, <&clks 0>, <&clks 72>;
 110                                         clock-names = "ipg", "ahb", "per";
 111                                         bus-width = <4>;
 112                                         status = "disabled";
 113                                 };
 114
 115                                 uart3: serial@5000c000 {
 116                                         compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 117                                         reg = <0x5000c000 0x4000>;
 118                                         interrupts = <33>;
 119                                         clocks = <&clks 32>, <&clks 33>;
 120                                         clock-names = "ipg", "per";
 121                                         status = "disabled";
 122                                 };
 123
 124                                 ecspi1: ecspi@50010000 {
 125                                         #address-cells = <1>;
 126                                         #size-cells = <0>;
 127                                         compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
 128                                         reg = <0x50010000 0x4000>;
 129                                         interrupts = <36>;
 130                                         clocks = <&clks 51>, <&clks 52>;
 131                                         clock-names = "ipg", "per";
 132                                         status = "disabled";
 133                                 };
 134
 135                                 ssi2: ssi@50014000 {
 136                                         compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
 137                                         reg = <0x50014000 0x4000>;
 138                                         interrupts = <30>;
 139                                         clocks = <&clks 49>;
 140                                         fsl,fifo-depth = <15>;
 141                                         fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
 142                                         status = "disabled";
 143                                 };
 144
 145                                 esdhc3: esdhc@50020000 {
 146                                         compatible = "fsl,imx53-esdhc";
 147                                         reg = <0x50020000 0x4000>;
 148                                         interrupts = <3>;
 149                                         clocks = <&clks 46>, <&clks 0>, <&clks 73>;
 150                                         clock-names = "ipg", "ahb", "per";
 151                                         bus-width = <4>;
 152                                         status = "disabled";
 153                                 };
 154
 155                                 esdhc4: esdhc@50024000 {
 156                                         compatible = "fsl,imx53-esdhc";
 157                                         reg = <0x50024000 0x4000>;
 158                                         interrupts = <4>;
 159                                         clocks = <&clks 47>, <&clks 0>, <&clks 74>;
 160                                         clock-names = "ipg", "ahb", "per";
 161                                         bus-width = <4>;
 162                                         status = "disabled";
 163                                 };
 164                         };
 165
 166                         usbotg: usb@53f80000 {
 167                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 168                                 reg = <0x53f80000 0x0200>;
 169                                 interrupts = <18>;
 170                                 clocks = <&clks 108>;
 171                                 fsl,usbmisc = <&usbmisc 0>;
 172                                 status = "disabled";
 173                         };
 174
 175                         usbh1: usb@53f80200 {
 176                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 177                                 reg = <0x53f80200 0x0200>;
 178                                 interrupts = <14>;
 179                                 clocks = <&clks 108>;
 180                                 fsl,usbmisc = <&usbmisc 1>;
 181                                 status = "disabled";
 182                         };
 183
 184                         usbh2: usb@53f80400 {
 185                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 186                                 reg = <0x53f80400 0x0200>;
 187                                 interrupts = <16>;
 188                                 clocks = <&clks 108>;
 189                                 fsl,usbmisc = <&usbmisc 2>;
 190                                 status = "disabled";
 191                         };
 192
 193                         usbh3: usb@53f80600 {
 194                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 195                                 reg = <0x53f80600 0x0200>;
 196                                 interrupts = <17>;
 197                                 clocks = <&clks 108>;
 198                                 fsl,usbmisc = <&usbmisc 3>;
 199                                 status = "disabled";
 200                         };
 201
 202                         usbmisc: usbmisc@53f80800 {
 203                                 #index-cells = <1>;
 204                                 compatible = "fsl,imx53-usbmisc";
 205                                 reg = <0x53f80800 0x200>;
 206                                 clocks = <&clks 108>;
 207                         };
 208
 209                         gpio1: gpio@53f84000 {
 210                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 211                                 reg = <0x53f84000 0x4000>;
 212                                 interrupts = <50 51>;
 213                                 gpio-controller;
 214                                 #gpio-cells = <2>;
 215                                 interrupt-controller;
 216                                 #interrupt-cells = <2>;
 217                         };
 218
 219                         gpio2: gpio@53f88000 {
 220                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 221                                 reg = <0x53f88000 0x4000>;
 222                                 interrupts = <52 53>;
 223                                 gpio-controller;
 224                                 #gpio-cells = <2>;
 225                                 interrupt-controller;
 226                                 #interrupt-cells = <2>;
 227                         };
 228
 229                         gpio3: gpio@53f8c000 {
 230                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 231                                 reg = <0x53f8c000 0x4000>;
 232                                 interrupts = <54 55>;
 233                                 gpio-controller;
 234                                 #gpio-cells = <2>;
 235                                 interrupt-controller;
 236                                 #interrupt-cells = <2>;
 237                         };
 238
 239                         gpio4: gpio@53f90000 {
 240                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 241                                 reg = <0x53f90000 0x4000>;
 242                                 interrupts = <56 57>;
 243                                 gpio-controller;
 244                                 #gpio-cells = <2>;
 245                                 interrupt-controller;
 246                                 #interrupt-cells = <2>;
 247                         };
 248
 249                         wdog1: wdog@53f98000 {
 250                                 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
 251                                 reg = <0x53f98000 0x4000>;
 252                                 interrupts = <58>;
 253                                 clocks = <&clks 0>;
 254                         };
 255
 256                         wdog2: wdog@53f9c000 {
 257                                 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
 258                                 reg = <0x53f9c000 0x4000>;
 259                                 interrupts = <59>;
 260                                 clocks = <&clks 0>;
 261                                 status = "disabled";
 262                         };
 263
 264                         gpt: timer@53fa0000 {
 265                                 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
 266                                 reg = <0x53fa0000 0x4000>;
 267                                 interrupts = <39>;
 268                                 clocks = <&clks 36>, <&clks 41>;
 269                                 clock-names = "ipg", "per";
 270                         };
 271
 272                         iomuxc: iomuxc@53fa8000 {
 273                                 compatible = "fsl,imx53-iomuxc";
 274                                 reg = <0x53fa8000 0x4000>;
 275
 276                                 audmux {
 277                                         pinctrl_audmux_1: audmuxgrp-1 {
 278                                                 fsl,pins = <
 279                                                         MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC  0x80000000
 280                                                         MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD  0x80000000
 281                                                         MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
 282                                                         MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD  0x80000000
 283                                                 >;
 284                                         };
 285                                 };
 286
 287                                 fec {
 288                                         pinctrl_fec_1: fecgrp-1 {
 289                                                 fsl,pins = <
 290                                                         MX53_PAD_FEC_MDC__FEC_MDC        0x80000000
 291                                                         MX53_PAD_FEC_MDIO__FEC_MDIO      0x80000000
 292                                                         MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
 293                                                         MX53_PAD_FEC_RX_ER__FEC_RX_ER    0x80000000
 294                                                         MX53_PAD_FEC_CRS_DV__FEC_RX_DV   0x80000000
 295                                                         MX53_PAD_FEC_RXD1__FEC_RDATA_1   0x80000000
 296                                                         MX53_PAD_FEC_RXD0__FEC_RDATA_0   0x80000000
 297                                                         MX53_PAD_FEC_TX_EN__FEC_TX_EN    0x80000000
 298                                                         MX53_PAD_FEC_TXD1__FEC_TDATA_1   0x80000000
 299                                                         MX53_PAD_FEC_TXD0__FEC_TDATA_0   0x80000000
 300                                                 >;
 301                                         };
 302                                 };
 303
 304                                 csi {
 305                                         pinctrl_csi_1: csigrp-1 {
 306                                                 fsl,pins = <
 307                                                         MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x1d5
 308                                                         MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC     0x1d5
 309                                                         MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC      0x1d5
 310                                                         MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK   0x1d5
 311                                                         MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19      0x1d5
 312                                                         MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18      0x1d5
 313                                                         MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17      0x1d5
 314                                                         MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16      0x1d5
 315                                                         MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15      0x1d5
 316                                                         MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14      0x1d5
 317                                                         MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13      0x1d5
 318                                                         MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12      0x1d5
 319                                                         MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11      0x1d5
 320                                                         MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10      0x1d5
 321                                                         MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9        0x1d5
 322                                                         MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8        0x1d5
 323                                                         MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7        0x1d5
 324                                                         MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6        0x1d5
 325                                                         MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5        0x1d5
 326                                                         MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4        0x1d5
 327                                                         MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK   0x1d5
 328                                                 >;
 329                                         };
 330                                 };
 331
 332                                 cspi {
 333                                         pinctrl_cspi_1: cspigrp-1 {
 334                                                 fsl,pins = <
 335                                                         MX53_PAD_SD1_DATA0__CSPI_MISO 0x1d5
 336                                                         MX53_PAD_SD1_CMD__CSPI_MOSI   0x1d5
 337                                                         MX53_PAD_SD1_CLK__CSPI_SCLK   0x1d5
 338                                                 >;
 339                                         };
 340                                 };
 341
 342                                 ecspi1 {
 343                                         pinctrl_ecspi1_1: ecspi1grp-1 {
 344                                                 fsl,pins = <
 345                                                         MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
 346                                                         MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
 347                                                         MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
 348                                                 >;
 349                                         };
 350                                 };
 351
 352                                 esdhc1 {
 353                                         pinctrl_esdhc1_1: esdhc1grp-1 {
 354                                                 fsl,pins = <
 355                                                         MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
 356                                                         MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
 357                                                         MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
 358                                                         MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
 359                                                         MX53_PAD_SD1_CMD__ESDHC1_CMD    0x1d5
 360                                                         MX53_PAD_SD1_CLK__ESDHC1_CLK    0x1d5
 361                                                 >;
 362                                         };
 363
 364                                         pinctrl_esdhc1_2: esdhc1grp-2 {
 365                                                 fsl,pins = <
 366                                                         MX53_PAD_SD1_DATA0__ESDHC1_DAT0   0x1d5
 367                                                         MX53_PAD_SD1_DATA1__ESDHC1_DAT1   0x1d5
 368                                                         MX53_PAD_SD1_DATA2__ESDHC1_DAT2   0x1d5
 369                                                         MX53_PAD_SD1_DATA3__ESDHC1_DAT3   0x1d5
 370                                                         MX53_PAD_PATA_DATA8__ESDHC1_DAT4  0x1d5
 371                                                         MX53_PAD_PATA_DATA9__ESDHC1_DAT5  0x1d5
 372                                                         MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x1d5
 373                                                         MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x1d5
 374                                                         MX53_PAD_SD1_CMD__ESDHC1_CMD      0x1d5
 375                                                         MX53_PAD_SD1_CLK__ESDHC1_CLK      0x1d5
 376                                                 >;
 377                                         };
 378                                 };
 379
 380                                 esdhc2 {
 381                                         pinctrl_esdhc2_1: esdhc2grp-1 {
 382                                                 fsl,pins = <
 383                                                         MX53_PAD_SD2_CMD__ESDHC2_CMD    0x1d5
 384                                                         MX53_PAD_SD2_CLK__ESDHC2_CLK    0x1d5
 385                                                         MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
 386                                                         MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
 387                                                         MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
 388                                                         MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
 389                                                 >;
 390                                         };
 391                                 };
 392
 393                                 esdhc3 {
 394                                         pinctrl_esdhc3_1: esdhc3grp-1 {
 395                                                 fsl,pins = <
 396                                                         MX53_PAD_PATA_DATA8__ESDHC3_DAT0  0x1d5
 397                                                         MX53_PAD_PATA_DATA9__ESDHC3_DAT1  0x1d5
 398                                                         MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
 399                                                         MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
 400                                                         MX53_PAD_PATA_DATA0__ESDHC3_DAT4  0x1d5
 401                                                         MX53_PAD_PATA_DATA1__ESDHC3_DAT5  0x1d5
 402                                                         MX53_PAD_PATA_DATA2__ESDHC3_DAT6  0x1d5
 403                                                         MX53_PAD_PATA_DATA3__ESDHC3_DAT7  0x1d5
 404                                                         MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
 405                                                         MX53_PAD_PATA_IORDY__ESDHC3_CLK   0x1d5
 406                                                 >;
 407                                         };
 408                                 };
 409
 410                                 can1 {
 411                                         pinctrl_can1_1: can1grp-1 {
 412                                                 fsl,pins = <
 413                                                         MX53_PAD_PATA_INTRQ__CAN1_TXCAN 0x80000000
 414                                                         MX53_PAD_PATA_DIOR__CAN1_RXCAN  0x80000000
 415                                                 >;
 416                                         };
 417
 418                                         pinctrl_can1_2: can1grp-2 {
 419                                                 fsl,pins = <
 420                                                         MX53_PAD_KEY_COL2__CAN1_TXCAN 0x80000000
 421                                                         MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000
 422                                                 >;
 423                                         };
 424                                 };
 425
 426                                 can2 {
 427                                         pinctrl_can2_1: can2grp-1 {
 428                                                 fsl,pins = <
 429                                                         MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000
 430                                                         MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000
 431                                                 >;
 432                                         };
 433                                 };
 434
 435                                 i2c1 {
 436                                         pinctrl_i2c1_1: i2c1grp-1 {
 437                                                 fsl,pins = <
 438                                                         MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000
 439                                                         MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000
 440                                                 >;
 441                                         };
 442                                 };
 443
 444                                 i2c2 {
 445                                         pinctrl_i2c2_1: i2c2grp-1 {
 446                                                 fsl,pins = <
 447                                                         MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
 448                                                         MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
 449                                                 >;
 450                                         };
 451                                 };
 452
 453                                 i2c3 {
 454                                         pinctrl_i2c3_1: i2c3grp-1 {
 455                                                 fsl,pins = <
 456                                                         MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
 457                                                         MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000
 458                                                 >;
 459                                         };
 460                                 };
 461
 462                                 owire {
 463                                         pinctrl_owire_1: owiregrp-1 {
 464                                                 fsl,pins = <
 465                                                         MX53_PAD_GPIO_18__OWIRE_LINE 0x80000000
 466                                                 >;
 467                                         };
 468                                 };
 469
 470                                 uart1 {
 471                                         pinctrl_uart1_1: uart1grp-1 {
 472                                                 fsl,pins = <
 473                                                         MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1c5
 474                                                         MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1c5
 475                                                 >;
 476                                         };
 477
 478                                         pinctrl_uart1_2: uart1grp-2 {
 479                                                 fsl,pins = <
 480                                                         MX53_PAD_PATA_DIOW__UART1_TXD_MUX  0x1c5
 481                                                         MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1c5
 482                                                 >;
 483                                         };
 484                                 };
 485
 486                                 uart2 {
 487                                         pinctrl_uart2_1: uart2grp-1 {
 488                                                 fsl,pins = <
 489                                                         MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1c5
 490                                                         MX53_PAD_PATA_DMARQ__UART2_TXD_MUX     0x1c5
 491                                                 >;
 492                                         };
 493                                 };
 494
 495                                 uart3 {
 496                                         pinctrl_uart3_1: uart3grp-1 {
 497                                                 fsl,pins = <
 498                                                         MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1c5
 499                                                         MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1c5
 500                                                         MX53_PAD_PATA_DA_1__UART3_CTS     0x1c5
 501                                                         MX53_PAD_PATA_DA_2__UART3_RTS     0x1c5
 502                                                 >;
 503                                         };
 504
 505                                         pinctrl_uart3_2: uart3grp-2 {
 506                                                 fsl,pins = <
 507                                                         MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1c5
 508                                                         MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1c5
 509                                                 >;
 510                                         };
 511
 512                                 };
 513
 514                                 uart4 {
 515                                         pinctrl_uart4_1: uart4grp-1 {
 516                                                 fsl,pins = <
 517                                                         MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1c5
 518                                                         MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1c5
 519                                                 >;
 520                                         };
 521                                 };
 522
 523                                 uart5 {
 524                                         pinctrl_uart5_1: uart5grp-1 {
 525                                                 fsl,pins = <
 526                                                         MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x1c5
 527                                                         MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x1c5
 528                                                 >;
 529                                         };
 530                                 };
 531
 532                         };
 533
 534                         gpr: iomuxc-gpr@53fa8000 {
 535                                 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
 536                                 reg = <0x53fa8000 0xc>;
 537                         };
 538
 539                         ldb: ldb@53fa8008 {
 540                                 #address-cells = <1>;
 541                                 #size-cells = <0>;
 542                                 compatible = "fsl,imx53-ldb";
 543                                 reg = <0x53fa8008 0x4>;
 544                                 gpr = <&gpr>;
 545                                 clocks = <&clks 122>, <&clks 120>,
 546                                          <&clks 115>, <&clks 116>,
 547                                          <&clks 123>, <&clks 85>;
 548                                 clock-names = "di0_pll", "di1_pll",
 549                                               "di0_sel", "di1_sel",
 550                                               "di0", "di1";
 551                                 status = "disabled";
 552
 553                                 lvds-channel@0 {
 554                                         reg = <0>;
 555                                         crtcs = <&ipu 0>;
 556                                         status = "disabled";
 557                                 };
 558
 559                                 lvds-channel@1 {
 560                                         reg = <1>;
 561                                         crtcs = <&ipu 1>;
 562                                         status = "disabled";
 563                                 };
 564                         };
 565
 566                         pwm1: pwm@53fb4000 {
 567                                 #pwm-cells = <2>;
 568                                 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
 569                                 reg = <0x53fb4000 0x4000>;
 570                                 clocks = <&clks 37>, <&clks 38>;
 571                                 clock-names = "ipg", "per";
 572                                 interrupts = <61>;
 573                         };
 574
 575                         pwm2: pwm@53fb8000 {
 576                                 #pwm-cells = <2>;
 577                                 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
 578                                 reg = <0x53fb8000 0x4000>;
 579                                 clocks = <&clks 39>, <&clks 40>;
 580                                 clock-names = "ipg", "per";
 581                                 interrupts = <94>;
 582                         };
 583
 584                         uart1: serial@53fbc000 {
 585                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 586                                 reg = <0x53fbc000 0x4000>;
 587                                 interrupts = <31>;
 588                                 clocks = <&clks 28>, <&clks 29>;
 589                                 clock-names = "ipg", "per";
 590                                 status = "disabled";
 591                         };
 592
 593                         uart2: serial@53fc0000 {
 594                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 595                                 reg = <0x53fc0000 0x4000>;
 596                                 interrupts = <32>;
 597                                 clocks = <&clks 30>, <&clks 31>;
 598                                 clock-names = "ipg", "per";
 599                                 status = "disabled";
 600                         };
 601
 602                         can1: can@53fc8000 {
 603                                 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
 604                                 reg = <0x53fc8000 0x4000>;
 605                                 interrupts = <82>;
 606                                 clocks = <&clks 158>, <&clks 157>;
 607                                 clock-names = "ipg", "per";
 608                                 status = "disabled";
 609                         };
 610
 611                         can2: can@53fcc000 {
 612                                 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
 613                                 reg = <0x53fcc000 0x4000>;
 614                                 interrupts = <83>;
 615                                 clocks = <&clks 87>, <&clks 86>;
 616                                 clock-names = "ipg", "per";
 617                                 status = "disabled";
 618                         };
 619
 620                         src: src@53fd0000 {
 621                                 compatible = "fsl,imx53-src", "fsl,imx51-src";
 622                                 reg = <0x53fd0000 0x4000>;
 623                                 #reset-cells = <1>;
 624                         };
 625
 626                         clks: ccm@53fd4000{
 627                                 compatible = "fsl,imx53-ccm";
 628                                 reg = <0x53fd4000 0x4000>;
 629                                 interrupts = <0 71 0x04 0 72 0x04>;
 630                                 #clock-cells = <1>;
 631                         };
 632
 633                         gpio5: gpio@53fdc000 {
 634                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 635                                 reg = <0x53fdc000 0x4000>;
 636                                 interrupts = <103 104>;
 637                                 gpio-controller;
 638                                 #gpio-cells = <2>;
 639                                 interrupt-controller;
 640                                 #interrupt-cells = <2>;
 641                         };
 642
 643                         gpio6: gpio@53fe0000 {
 644                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 645                                 reg = <0x53fe0000 0x4000>;
 646                                 interrupts = <105 106>;
 647                                 gpio-controller;
 648                                 #gpio-cells = <2>;
 649                                 interrupt-controller;
 650                                 #interrupt-cells = <2>;
 651                         };
 652
 653                         gpio7: gpio@53fe4000 {
 654                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 655                                 reg = <0x53fe4000 0x4000>;
 656                                 interrupts = <107 108>;
 657                                 gpio-controller;
 658                                 #gpio-cells = <2>;
 659                                 interrupt-controller;
 660                                 #interrupt-cells = <2>;
 661                         };
 662
 663                         i2c3: i2c@53fec000 {
 664                                 #address-cells = <1>;
 665                                 #size-cells = <0>;
 666                                 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
 667                                 reg = <0x53fec000 0x4000>;
 668                                 interrupts = <64>;
 669                                 clocks = <&clks 88>;
 670                                 status = "disabled";
 671                         };
 672
 673                         uart4: serial@53ff0000 {
 674                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 675                                 reg = <0x53ff0000 0x4000>;
 676                                 interrupts = <13>;
 677                                 clocks = <&clks 65>, <&clks 66>;
 678                                 clock-names = "ipg", "per";
 679                                 status = "disabled";
 680                         };
 681                 };
 682
 683                 aips@60000000 { /* AIPS2 */
 684                         compatible = "fsl,aips-bus", "simple-bus";
 685                         #address-cells = <1>;
 686                         #size-cells = <1>;
 687                         reg = <0x60000000 0x10000000>;
 688                         ranges;
 689
 690                         uart5: serial@63f90000 {
 691                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 692                                 reg = <0x63f90000 0x4000>;
 693                                 interrupts = <86>;
 694                                 clocks = <&clks 67>, <&clks 68>;
 695                                 clock-names = "ipg", "per";
 696                                 status = "disabled";
 697                         };
 698
 699                         owire: owire@63fa4000 {
 700                                 compatible = "fsl,imx53-owire", "fsl,imx21-owire";
 701                                 reg = <0x63fa4000 0x4000>;
 702                                 clocks = <&clks 159>;
 703                                 status = "disabled";
 704                         };
 705
 706                         ecspi2: ecspi@63fac000 {
 707                                 #address-cells = <1>;
 708                                 #size-cells = <0>;
 709                                 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
 710                                 reg = <0x63fac000 0x4000>;
 711                                 interrupts = <37>;
 712                                 clocks = <&clks 53>, <&clks 54>;
 713                                 clock-names = "ipg", "per";
 714                                 status = "disabled";
 715                         };
 716
 717                         sdma: sdma@63fb0000 {
 718                                 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
 719                                 reg = <0x63fb0000 0x4000>;
 720                                 interrupts = <6>;
 721                                 clocks = <&clks 56>, <&clks 56>;
 722                                 clock-names = "ipg", "ahb";
 723                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
 724                         };
 725
 726                         cspi: cspi@63fc0000 {
 727                                 #address-cells = <1>;
 728                                 #size-cells = <0>;
 729                                 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
 730                                 reg = <0x63fc0000 0x4000>;
 731                                 interrupts = <38>;
 732                                 clocks = <&clks 55>, <&clks 55>;
 733                                 clock-names = "ipg", "per";
 734                                 status = "disabled";
 735                         };
 736
 737                         i2c2: i2c@63fc4000 {
 738                                 #address-cells = <1>;
 739                                 #size-cells = <0>;
 740                                 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
 741                                 reg = <0x63fc4000 0x4000>;
 742                                 interrupts = <63>;
 743                                 clocks = <&clks 35>;
 744                                 status = "disabled";
 745                         };
 746
 747                         i2c1: i2c@63fc8000 {
 748                                 #address-cells = <1>;
 749                                 #size-cells = <0>;
 750                                 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
 751                                 reg = <0x63fc8000 0x4000>;
 752                                 interrupts = <62>;
 753                                 clocks = <&clks 34>;
 754                                 status = "disabled";
 755                         };
 756
 757                         ssi1: ssi@63fcc000 {
 758                                 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
 759                                 reg = <0x63fcc000 0x4000>;
 760                                 interrupts = <29>;
 761                                 clocks = <&clks 48>;
 762                                 fsl,fifo-depth = <15>;
 763                                 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
 764                                 status = "disabled";
 765                         };
 766
 767                         audmux: audmux@63fd0000 {
 768                                 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
 769                                 reg = <0x63fd0000 0x4000>;
 770                                 status = "disabled";
 771                         };
 772
 773                         nfc: nand@63fdb000 {
 774                                 compatible = "fsl,imx53-nand";
 775                                 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
 776                                 interrupts = <8>;
 777                                 clocks = <&clks 60>;
 778                                 status = "disabled";
 779                         };
 780
 781                         ssi3: ssi@63fe8000 {
 782                                 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
 783                                 reg = <0x63fe8000 0x4000>;
 784                                 interrupts = <96>;
 785                                 clocks = <&clks 50>;
 786                                 fsl,fifo-depth = <15>;
 787                                 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
 788                                 status = "disabled";
 789                         };
 790
 791                         fec: ethernet@63fec000 {
 792                                 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
 793                                 reg = <0x63fec000 0x4000>;
 794                                 interrupts = <87>;
 795                                 clocks = <&clks 42>, <&clks 42>, <&clks 42>;
 796                                 clock-names = "ipg", "ahb", "ptp";
 797                                 status = "disabled";
 798                         };
 799                 };
 800         };
 801 };