2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include "skeleton.dtsi"
14 #include "imx53-pinfunc.h"
15 #include <dt-bindings/clock/imx5-clock.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/input/input.h>
51 compatible = "arm,cortex-a8";
57 compatible = "fsl,imx-display-subsystem";
58 ports = <&ipu_di0>, <&ipu_di1>;
61 tzic: tz-interrupt-controller@0fffc000 {
62 compatible = "fsl,imx53-tzic", "fsl,tzic";
64 #interrupt-cells = <1>;
65 reg = <0x0fffc000 0x4000>;
73 compatible = "fsl,imx-ckil", "fixed-clock";
75 clock-frequency = <32768>;
79 compatible = "fsl,imx-ckih1", "fixed-clock";
81 clock-frequency = <22579200>;
85 compatible = "fsl,imx-ckih2", "fixed-clock";
87 clock-frequency = <0>;
91 compatible = "fsl,imx-osc", "fixed-clock";
93 clock-frequency = <24000000>;
100 compatible = "simple-bus";
101 interrupt-parent = <&tzic>;
104 sata: sata@10000000 {
105 compatible = "fsl,imx53-ahci";
106 reg = <0x10000000 0x1000>;
108 clocks = <&clks IMX5_CLK_SATA_GATE>,
109 <&clks IMX5_CLK_SATA_REF>,
110 <&clks IMX5_CLK_AHB>;
111 clock-names = "sata_gate", "sata_ref", "ahb";
116 #address-cells = <1>;
118 compatible = "fsl,imx53-ipu";
119 reg = <0x18000000 0x08000000>;
120 interrupts = <11 10>;
121 clocks = <&clks IMX5_CLK_IPU_GATE>,
122 <&clks IMX5_CLK_IPU_DI0_GATE>,
123 <&clks IMX5_CLK_IPU_DI1_GATE>;
124 clock-names = "bus", "di0", "di1";
128 #address-cells = <1>;
132 ipu_di0_disp0: endpoint@0 {
136 ipu_di0_lvds0: endpoint@1 {
138 remote-endpoint = <&lvds0_in>;
143 #address-cells = <1>;
147 ipu_di1_disp1: endpoint@0 {
151 ipu_di1_lvds1: endpoint@1 {
153 remote-endpoint = <&lvds1_in>;
156 ipu_di1_tve: endpoint@2 {
158 remote-endpoint = <&tve_in>;
163 aips@50000000 { /* AIPS1 */
164 compatible = "fsl,aips-bus", "simple-bus";
165 #address-cells = <1>;
167 reg = <0x50000000 0x10000000>;
171 compatible = "fsl,spba-bus", "simple-bus";
172 #address-cells = <1>;
174 reg = <0x50000000 0x40000>;
177 esdhc1: esdhc@50004000 {
178 compatible = "fsl,imx53-esdhc";
179 reg = <0x50004000 0x4000>;
181 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
182 <&clks IMX5_CLK_DUMMY>,
183 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
184 clock-names = "ipg", "ahb", "per";
189 esdhc2: esdhc@50008000 {
190 compatible = "fsl,imx53-esdhc";
191 reg = <0x50008000 0x4000>;
193 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
194 <&clks IMX5_CLK_DUMMY>,
195 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
196 clock-names = "ipg", "ahb", "per";
201 uart3: serial@5000c000 {
202 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
203 reg = <0x5000c000 0x4000>;
205 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
206 <&clks IMX5_CLK_UART3_PER_GATE>;
207 clock-names = "ipg", "per";
211 ecspi1: ecspi@50010000 {
212 #address-cells = <1>;
214 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
215 reg = <0x50010000 0x4000>;
217 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
218 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
219 clock-names = "ipg", "per";
224 compatible = "fsl,imx53-ssi",
227 reg = <0x50014000 0x4000>;
229 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
230 dmas = <&sdma 24 1 0>,
232 dma-names = "rx", "tx";
233 fsl,fifo-depth = <15>;
234 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
238 esdhc3: esdhc@50020000 {
239 compatible = "fsl,imx53-esdhc";
240 reg = <0x50020000 0x4000>;
242 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
243 <&clks IMX5_CLK_DUMMY>,
244 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
245 clock-names = "ipg", "ahb", "per";
250 esdhc4: esdhc@50024000 {
251 compatible = "fsl,imx53-esdhc";
252 reg = <0x50024000 0x4000>;
254 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
255 <&clks IMX5_CLK_DUMMY>,
256 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
257 clock-names = "ipg", "ahb", "per";
264 compatible = "usb-nop-xceiv";
265 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
266 clock-names = "main_clk";
271 compatible = "usb-nop-xceiv";
272 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
273 clock-names = "main_clk";
277 usbotg: usb@53f80000 {
278 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
279 reg = <0x53f80000 0x0200>;
281 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
282 fsl,usbmisc = <&usbmisc 0>;
283 fsl,usbphy = <&usbphy0>;
287 usbh1: usb@53f80200 {
288 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
289 reg = <0x53f80200 0x0200>;
291 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
292 fsl,usbmisc = <&usbmisc 1>;
293 fsl,usbphy = <&usbphy1>;
297 usbh2: usb@53f80400 {
298 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
299 reg = <0x53f80400 0x0200>;
301 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
302 fsl,usbmisc = <&usbmisc 2>;
306 usbh3: usb@53f80600 {
307 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
308 reg = <0x53f80600 0x0200>;
310 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
311 fsl,usbmisc = <&usbmisc 3>;
315 usbmisc: usbmisc@53f80800 {
317 compatible = "fsl,imx53-usbmisc";
318 reg = <0x53f80800 0x200>;
319 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
322 gpio1: gpio@53f84000 {
323 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
324 reg = <0x53f84000 0x4000>;
325 interrupts = <50 51>;
328 interrupt-controller;
329 #interrupt-cells = <2>;
332 gpio2: gpio@53f88000 {
333 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
334 reg = <0x53f88000 0x4000>;
335 interrupts = <52 53>;
338 interrupt-controller;
339 #interrupt-cells = <2>;
342 gpio3: gpio@53f8c000 {
343 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
344 reg = <0x53f8c000 0x4000>;
345 interrupts = <54 55>;
348 interrupt-controller;
349 #interrupt-cells = <2>;
352 gpio4: gpio@53f90000 {
353 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
354 reg = <0x53f90000 0x4000>;
355 interrupts = <56 57>;
358 interrupt-controller;
359 #interrupt-cells = <2>;
363 compatible = "fsl,imx53-kpp", "fsl,imx21-kpp";
364 reg = <0x53f94000 0x4000>;
366 clocks = <&clks IMX5_CLK_DUMMY>;
370 wdog1: wdog@53f98000 {
371 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
372 reg = <0x53f98000 0x4000>;
374 clocks = <&clks IMX5_CLK_DUMMY>;
377 wdog2: wdog@53f9c000 {
378 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
379 reg = <0x53f9c000 0x4000>;
381 clocks = <&clks IMX5_CLK_DUMMY>;
385 gpt: timer@53fa0000 {
386 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
387 reg = <0x53fa0000 0x4000>;
389 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
390 <&clks IMX5_CLK_GPT_HF_GATE>;
391 clock-names = "ipg", "per";
394 iomuxc: iomuxc@53fa8000 {
395 compatible = "fsl,imx53-iomuxc";
396 reg = <0x53fa8000 0x4000>;
399 gpr: iomuxc-gpr@53fa8000 {
400 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
401 reg = <0x53fa8000 0xc>;
405 #address-cells = <1>;
407 compatible = "fsl,imx53-ldb";
408 reg = <0x53fa8008 0x4>;
410 clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
411 <&clks IMX5_CLK_LDB_DI1_SEL>,
412 <&clks IMX5_CLK_IPU_DI0_SEL>,
413 <&clks IMX5_CLK_IPU_DI1_SEL>,
414 <&clks IMX5_CLK_LDB_DI0_GATE>,
415 <&clks IMX5_CLK_LDB_DI1_GATE>;
416 clock-names = "di0_pll", "di1_pll",
417 "di0_sel", "di1_sel",
427 remote-endpoint = <&ipu_di0_lvds0>;
438 remote-endpoint = <&ipu_di1_lvds1>;
446 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
447 reg = <0x53fb4000 0x4000>;
448 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
449 <&clks IMX5_CLK_PWM1_HF_GATE>;
450 clock-names = "ipg", "per";
456 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
457 reg = <0x53fb8000 0x4000>;
458 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
459 <&clks IMX5_CLK_PWM2_HF_GATE>;
460 clock-names = "ipg", "per";
464 uart1: serial@53fbc000 {
465 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
466 reg = <0x53fbc000 0x4000>;
468 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
469 <&clks IMX5_CLK_UART1_PER_GATE>;
470 clock-names = "ipg", "per";
474 uart2: serial@53fc0000 {
475 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
476 reg = <0x53fc0000 0x4000>;
478 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
479 <&clks IMX5_CLK_UART2_PER_GATE>;
480 clock-names = "ipg", "per";
485 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
486 reg = <0x53fc8000 0x4000>;
488 clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>,
489 <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
490 clock-names = "ipg", "per";
495 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
496 reg = <0x53fcc000 0x4000>;
498 clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>,
499 <&clks IMX5_CLK_CAN2_SERIAL_GATE>;
500 clock-names = "ipg", "per";
505 compatible = "fsl,imx53-src", "fsl,imx51-src";
506 reg = <0x53fd0000 0x4000>;
511 compatible = "fsl,imx53-ccm";
512 reg = <0x53fd4000 0x4000>;
513 interrupts = <0 71 0x04 0 72 0x04>;
517 gpio5: gpio@53fdc000 {
518 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
519 reg = <0x53fdc000 0x4000>;
520 interrupts = <103 104>;
523 interrupt-controller;
524 #interrupt-cells = <2>;
527 gpio6: gpio@53fe0000 {
528 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
529 reg = <0x53fe0000 0x4000>;
530 interrupts = <105 106>;
533 interrupt-controller;
534 #interrupt-cells = <2>;
537 gpio7: gpio@53fe4000 {
538 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
539 reg = <0x53fe4000 0x4000>;
540 interrupts = <107 108>;
543 interrupt-controller;
544 #interrupt-cells = <2>;
548 #address-cells = <1>;
550 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
551 reg = <0x53fec000 0x4000>;
553 clocks = <&clks IMX5_CLK_I2C3_GATE>;
557 uart4: serial@53ff0000 {
558 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
559 reg = <0x53ff0000 0x4000>;
561 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
562 <&clks IMX5_CLK_UART4_PER_GATE>;
563 clock-names = "ipg", "per";
568 aips@60000000 { /* AIPS2 */
569 compatible = "fsl,aips-bus", "simple-bus";
570 #address-cells = <1>;
572 reg = <0x60000000 0x10000000>;
576 compatible = "fsl,imx53-iim", "fsl,imx27-iim";
577 reg = <0x63f98000 0x4000>;
579 clocks = <&clks IMX5_CLK_IIM_GATE>;
582 uart5: serial@63f90000 {
583 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
584 reg = <0x63f90000 0x4000>;
586 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
587 <&clks IMX5_CLK_UART5_PER_GATE>;
588 clock-names = "ipg", "per";
592 owire: owire@63fa4000 {
593 compatible = "fsl,imx53-owire", "fsl,imx21-owire";
594 reg = <0x63fa4000 0x4000>;
595 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
599 ecspi2: ecspi@63fac000 {
600 #address-cells = <1>;
602 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
603 reg = <0x63fac000 0x4000>;
605 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
606 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
607 clock-names = "ipg", "per";
611 sdma: sdma@63fb0000 {
612 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
613 reg = <0x63fb0000 0x4000>;
615 clocks = <&clks IMX5_CLK_SDMA_GATE>,
616 <&clks IMX5_CLK_SDMA_GATE>;
617 clock-names = "ipg", "ahb";
619 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
622 cspi: cspi@63fc0000 {
623 #address-cells = <1>;
625 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
626 reg = <0x63fc0000 0x4000>;
628 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
629 <&clks IMX5_CLK_CSPI_IPG_GATE>;
630 clock-names = "ipg", "per";
635 #address-cells = <1>;
637 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
638 reg = <0x63fc4000 0x4000>;
640 clocks = <&clks IMX5_CLK_I2C2_GATE>;
645 #address-cells = <1>;
647 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
648 reg = <0x63fc8000 0x4000>;
650 clocks = <&clks IMX5_CLK_I2C1_GATE>;
655 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
657 reg = <0x63fcc000 0x4000>;
659 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
660 dmas = <&sdma 28 0 0>,
662 dma-names = "rx", "tx";
663 fsl,fifo-depth = <15>;
664 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
668 audmux: audmux@63fd0000 {
669 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
670 reg = <0x63fd0000 0x4000>;
675 compatible = "fsl,imx53-nand";
676 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
678 clocks = <&clks IMX5_CLK_NFC_GATE>;
683 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
685 reg = <0x63fe8000 0x4000>;
687 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>;
688 dmas = <&sdma 46 0 0>,
690 dma-names = "rx", "tx";
691 fsl,fifo-depth = <15>;
692 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
696 fec: ethernet@63fec000 {
697 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
698 reg = <0x63fec000 0x4000>;
700 clocks = <&clks IMX5_CLK_FEC_GATE>,
701 <&clks IMX5_CLK_FEC_GATE>,
702 <&clks IMX5_CLK_FEC_GATE>;
703 clock-names = "ipg", "ahb", "ptp";
708 compatible = "fsl,imx53-tve";
709 reg = <0x63ff0000 0x1000>;
711 clocks = <&clks IMX5_CLK_TVE_GATE>,
712 <&clks IMX5_CLK_IPU_DI1_SEL>;
713 clock-names = "tve", "di_sel";
718 remote-endpoint = <&ipu_di1_tve>;
724 compatible = "fsl,imx53-vpu";
725 reg = <0x63ff4000 0x1000>;
727 clocks = <&clks IMX5_CLK_VPU_GATE>,
728 <&clks IMX5_CLK_VPU_GATE>;
729 clock-names = "per", "ahb";
735 ocram: sram@f8000000 {
736 compatible = "mmio-sram";
737 reg = <0xf8000000 0x20000>;
738 clocks = <&clks IMX5_CLK_OCRAM>;