2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include "skeleton.dtsi"
14 #include "imx53-pinfunc.h"
15 #include <dt-bindings/clock/imx5-clock.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/input/input.h>
51 compatible = "arm,cortex-a8";
57 compatible = "fsl,imx-display-subsystem";
58 ports = <&ipu_di0>, <&ipu_di1>;
61 tzic: tz-interrupt-controller@0fffc000 {
62 compatible = "fsl,imx53-tzic", "fsl,tzic";
64 #interrupt-cells = <1>;
65 reg = <0x0fffc000 0x4000>;
73 compatible = "fsl,imx-ckil", "fixed-clock";
75 clock-frequency = <32768>;
79 compatible = "fsl,imx-ckih1", "fixed-clock";
81 clock-frequency = <22579200>;
85 compatible = "fsl,imx-ckih2", "fixed-clock";
87 clock-frequency = <0>;
91 compatible = "fsl,imx-osc", "fixed-clock";
93 clock-frequency = <24000000>;
100 compatible = "simple-bus";
101 interrupt-parent = <&tzic>;
104 sata: sata@10000000 {
105 compatible = "fsl,imx53-ahci";
106 reg = <0x10000000 0x1000>;
108 clocks = <&clks IMX5_CLK_SATA_GATE>,
109 <&clks IMX5_CLK_SATA_REF>,
110 <&clks IMX5_CLK_AHB>;
111 clock-names = "sata", "sata_ref", "ahb";
116 #address-cells = <1>;
118 compatible = "fsl,imx53-ipu";
119 reg = <0x18000000 0x08000000>;
120 interrupts = <11 10>;
121 clocks = <&clks IMX5_CLK_IPU_GATE>,
122 <&clks IMX5_CLK_IPU_DI0_GATE>,
123 <&clks IMX5_CLK_IPU_DI1_GATE>;
124 clock-names = "bus", "di0", "di1";
128 #address-cells = <1>;
132 ipu_di0_disp0: endpoint@0 {
136 ipu_di0_lvds0: endpoint@1 {
138 remote-endpoint = <&lvds0_in>;
143 #address-cells = <1>;
147 ipu_di1_disp1: endpoint@0 {
151 ipu_di1_lvds1: endpoint@1 {
153 remote-endpoint = <&lvds1_in>;
156 ipu_di1_tve: endpoint@2 {
158 remote-endpoint = <&tve_in>;
163 aips@50000000 { /* AIPS1 */
164 compatible = "fsl,aips-bus", "simple-bus";
165 #address-cells = <1>;
167 reg = <0x50000000 0x10000000>;
171 compatible = "fsl,spba-bus", "simple-bus";
172 #address-cells = <1>;
174 reg = <0x50000000 0x40000>;
177 esdhc1: esdhc@50004000 {
178 compatible = "fsl,imx53-esdhc";
179 reg = <0x50004000 0x4000>;
181 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
182 <&clks IMX5_CLK_DUMMY>,
183 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
184 clock-names = "ipg", "ahb", "per";
189 esdhc2: esdhc@50008000 {
190 compatible = "fsl,imx53-esdhc";
191 reg = <0x50008000 0x4000>;
193 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
194 <&clks IMX5_CLK_DUMMY>,
195 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
196 clock-names = "ipg", "ahb", "per";
201 uart3: serial@5000c000 {
202 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
203 reg = <0x5000c000 0x4000>;
205 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
206 <&clks IMX5_CLK_UART3_PER_GATE>;
207 clock-names = "ipg", "per";
211 ecspi1: ecspi@50010000 {
212 #address-cells = <1>;
214 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
215 reg = <0x50010000 0x4000>;
217 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
218 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
219 clock-names = "ipg", "per";
224 #sound-dai-cells = <0>;
225 compatible = "fsl,imx53-ssi",
228 reg = <0x50014000 0x4000>;
230 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
231 dmas = <&sdma 24 1 0>,
233 dma-names = "rx", "tx";
234 fsl,fifo-depth = <15>;
238 esdhc3: esdhc@50020000 {
239 compatible = "fsl,imx53-esdhc";
240 reg = <0x50020000 0x4000>;
242 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
243 <&clks IMX5_CLK_DUMMY>,
244 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
245 clock-names = "ipg", "ahb", "per";
250 esdhc4: esdhc@50024000 {
251 compatible = "fsl,imx53-esdhc";
252 reg = <0x50024000 0x4000>;
254 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
255 <&clks IMX5_CLK_DUMMY>,
256 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
257 clock-names = "ipg", "ahb", "per";
263 aipstz1: bridge@53f00000 {
264 compatible = "fsl,imx53-aipstz";
265 reg = <0x53f00000 0x60>;
269 compatible = "usb-nop-xceiv";
270 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
271 clock-names = "main_clk";
276 compatible = "usb-nop-xceiv";
277 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
278 clock-names = "main_clk";
282 usbotg: usb@53f80000 {
283 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
284 reg = <0x53f80000 0x0200>;
286 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
287 fsl,usbmisc = <&usbmisc 0>;
288 fsl,usbphy = <&usbphy0>;
292 usbh1: usb@53f80200 {
293 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
294 reg = <0x53f80200 0x0200>;
296 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
297 fsl,usbmisc = <&usbmisc 1>;
298 fsl,usbphy = <&usbphy1>;
302 usbh2: usb@53f80400 {
303 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
304 reg = <0x53f80400 0x0200>;
306 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
307 fsl,usbmisc = <&usbmisc 2>;
311 usbh3: usb@53f80600 {
312 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
313 reg = <0x53f80600 0x0200>;
315 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
316 fsl,usbmisc = <&usbmisc 3>;
320 usbmisc: usbmisc@53f80800 {
322 compatible = "fsl,imx53-usbmisc";
323 reg = <0x53f80800 0x200>;
324 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
327 gpio1: gpio@53f84000 {
328 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
329 reg = <0x53f84000 0x4000>;
330 interrupts = <50 51>;
333 interrupt-controller;
334 #interrupt-cells = <2>;
337 gpio2: gpio@53f88000 {
338 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
339 reg = <0x53f88000 0x4000>;
340 interrupts = <52 53>;
343 interrupt-controller;
344 #interrupt-cells = <2>;
347 gpio3: gpio@53f8c000 {
348 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
349 reg = <0x53f8c000 0x4000>;
350 interrupts = <54 55>;
353 interrupt-controller;
354 #interrupt-cells = <2>;
357 gpio4: gpio@53f90000 {
358 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
359 reg = <0x53f90000 0x4000>;
360 interrupts = <56 57>;
363 interrupt-controller;
364 #interrupt-cells = <2>;
368 compatible = "fsl,imx53-kpp", "fsl,imx21-kpp";
369 reg = <0x53f94000 0x4000>;
371 clocks = <&clks IMX5_CLK_DUMMY>;
375 wdog1: wdog@53f98000 {
376 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
377 reg = <0x53f98000 0x4000>;
379 clocks = <&clks IMX5_CLK_DUMMY>;
382 wdog2: wdog@53f9c000 {
383 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
384 reg = <0x53f9c000 0x4000>;
386 clocks = <&clks IMX5_CLK_DUMMY>;
390 gpt: timer@53fa0000 {
391 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
392 reg = <0x53fa0000 0x4000>;
394 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
395 <&clks IMX5_CLK_GPT_HF_GATE>;
396 clock-names = "ipg", "per";
399 iomuxc: iomuxc@53fa8000 {
400 compatible = "fsl,imx53-iomuxc";
401 reg = <0x53fa8000 0x4000>;
404 gpr: iomuxc-gpr@53fa8000 {
405 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
406 reg = <0x53fa8000 0xc>;
410 #address-cells = <1>;
412 compatible = "fsl,imx53-ldb";
413 reg = <0x53fa8008 0x4>;
415 clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
416 <&clks IMX5_CLK_LDB_DI1_SEL>,
417 <&clks IMX5_CLK_IPU_DI0_SEL>,
418 <&clks IMX5_CLK_IPU_DI1_SEL>,
419 <&clks IMX5_CLK_LDB_DI0_GATE>,
420 <&clks IMX5_CLK_LDB_DI1_GATE>;
421 clock-names = "di0_pll", "di1_pll",
422 "di0_sel", "di1_sel",
427 #address-cells = <1>;
436 remote-endpoint = <&ipu_di0_lvds0>;
442 #address-cells = <1>;
451 remote-endpoint = <&ipu_di1_lvds1>;
459 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
460 reg = <0x53fb4000 0x4000>;
461 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
462 <&clks IMX5_CLK_PWM1_HF_GATE>;
463 clock-names = "ipg", "per";
469 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
470 reg = <0x53fb8000 0x4000>;
471 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
472 <&clks IMX5_CLK_PWM2_HF_GATE>;
473 clock-names = "ipg", "per";
477 uart1: serial@53fbc000 {
478 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
479 reg = <0x53fbc000 0x4000>;
481 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
482 <&clks IMX5_CLK_UART1_PER_GATE>;
483 clock-names = "ipg", "per";
487 uart2: serial@53fc0000 {
488 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
489 reg = <0x53fc0000 0x4000>;
491 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
492 <&clks IMX5_CLK_UART2_PER_GATE>;
493 clock-names = "ipg", "per";
498 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
499 reg = <0x53fc8000 0x4000>;
501 clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>,
502 <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
503 clock-names = "ipg", "per";
508 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
509 reg = <0x53fcc000 0x4000>;
511 clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>,
512 <&clks IMX5_CLK_CAN2_SERIAL_GATE>;
513 clock-names = "ipg", "per";
518 compatible = "fsl,imx53-src", "fsl,imx51-src";
519 reg = <0x53fd0000 0x4000>;
524 compatible = "fsl,imx53-ccm";
525 reg = <0x53fd4000 0x4000>;
526 interrupts = <0 71 0x04 0 72 0x04>;
530 gpio5: gpio@53fdc000 {
531 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
532 reg = <0x53fdc000 0x4000>;
533 interrupts = <103 104>;
536 interrupt-controller;
537 #interrupt-cells = <2>;
540 gpio6: gpio@53fe0000 {
541 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
542 reg = <0x53fe0000 0x4000>;
543 interrupts = <105 106>;
546 interrupt-controller;
547 #interrupt-cells = <2>;
550 gpio7: gpio@53fe4000 {
551 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
552 reg = <0x53fe4000 0x4000>;
553 interrupts = <107 108>;
556 interrupt-controller;
557 #interrupt-cells = <2>;
561 #address-cells = <1>;
563 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
564 reg = <0x53fec000 0x4000>;
566 clocks = <&clks IMX5_CLK_I2C3_GATE>;
570 uart4: serial@53ff0000 {
571 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
572 reg = <0x53ff0000 0x4000>;
574 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
575 <&clks IMX5_CLK_UART4_PER_GATE>;
576 clock-names = "ipg", "per";
581 aips@60000000 { /* AIPS2 */
582 compatible = "fsl,aips-bus", "simple-bus";
583 #address-cells = <1>;
585 reg = <0x60000000 0x10000000>;
588 aipstz2: bridge@63f00000 {
589 compatible = "fsl,imx53-aipstz";
590 reg = <0x63f00000 0x60>;
594 compatible = "fsl,imx53-iim", "fsl,imx27-iim";
595 reg = <0x63f98000 0x4000>;
597 clocks = <&clks IMX5_CLK_IIM_GATE>;
600 uart5: serial@63f90000 {
601 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
602 reg = <0x63f90000 0x4000>;
604 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
605 <&clks IMX5_CLK_UART5_PER_GATE>;
606 clock-names = "ipg", "per";
610 owire: owire@63fa4000 {
611 compatible = "fsl,imx53-owire", "fsl,imx21-owire";
612 reg = <0x63fa4000 0x4000>;
613 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
617 ecspi2: ecspi@63fac000 {
618 #address-cells = <1>;
620 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
621 reg = <0x63fac000 0x4000>;
623 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
624 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
625 clock-names = "ipg", "per";
629 sdma: sdma@63fb0000 {
630 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
631 reg = <0x63fb0000 0x4000>;
633 clocks = <&clks IMX5_CLK_SDMA_GATE>,
634 <&clks IMX5_CLK_SDMA_GATE>;
635 clock-names = "ipg", "ahb";
637 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
640 cspi: cspi@63fc0000 {
641 #address-cells = <1>;
643 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
644 reg = <0x63fc0000 0x4000>;
646 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
647 <&clks IMX5_CLK_CSPI_IPG_GATE>;
648 clock-names = "ipg", "per";
653 #address-cells = <1>;
655 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
656 reg = <0x63fc4000 0x4000>;
658 clocks = <&clks IMX5_CLK_I2C2_GATE>;
663 #address-cells = <1>;
665 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
666 reg = <0x63fc8000 0x4000>;
668 clocks = <&clks IMX5_CLK_I2C1_GATE>;
673 #sound-dai-cells = <0>;
674 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
676 reg = <0x63fcc000 0x4000>;
678 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
679 dmas = <&sdma 28 0 0>,
681 dma-names = "rx", "tx";
682 fsl,fifo-depth = <15>;
686 audmux: audmux@63fd0000 {
687 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
688 reg = <0x63fd0000 0x4000>;
693 compatible = "fsl,imx53-nand";
694 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
696 clocks = <&clks IMX5_CLK_NFC_GATE>;
701 #sound-dai-cells = <0>;
702 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
704 reg = <0x63fe8000 0x4000>;
706 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>;
707 dmas = <&sdma 46 0 0>,
709 dma-names = "rx", "tx";
710 fsl,fifo-depth = <15>;
714 fec: ethernet@63fec000 {
715 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
716 reg = <0x63fec000 0x4000>;
718 clocks = <&clks IMX5_CLK_FEC_GATE>,
719 <&clks IMX5_CLK_FEC_GATE>,
720 <&clks IMX5_CLK_FEC_GATE>;
721 clock-names = "ipg", "ahb", "ptp";
726 compatible = "fsl,imx53-tve";
727 reg = <0x63ff0000 0x1000>;
729 clocks = <&clks IMX5_CLK_TVE_GATE>,
730 <&clks IMX5_CLK_IPU_DI1_SEL>;
731 clock-names = "tve", "di_sel";
736 remote-endpoint = <&ipu_di1_tve>;
742 compatible = "fsl,imx53-vpu";
743 reg = <0x63ff4000 0x1000>;
745 clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
746 <&clks IMX5_CLK_VPU_GATE>;
747 clock-names = "per", "ahb";
753 ocram: sram@f8000000 {
754 compatible = "mmio-sram";
755 reg = <0xf8000000 0x20000>;
756 clocks = <&clks IMX5_CLK_OCRAM>;
760 compatible = "arm,cortex-a8-pmu";