2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 /include/ "skeleton.dtsi"
24 tzic: tz-interrupt-controller@0fffc000 {
25 compatible = "fsl,imx53-tzic", "fsl,tzic";
27 #interrupt-cells = <1>;
28 reg = <0x0fffc000 0x4000>;
36 compatible = "fsl,imx-ckil", "fixed-clock";
37 clock-frequency = <32768>;
41 compatible = "fsl,imx-ckih1", "fixed-clock";
42 clock-frequency = <22579200>;
46 compatible = "fsl,imx-ckih2", "fixed-clock";
47 clock-frequency = <0>;
51 compatible = "fsl,imx-osc", "fixed-clock";
52 clock-frequency = <24000000>;
59 compatible = "simple-bus";
60 interrupt-parent = <&tzic>;
63 aips@50000000 { /* AIPS1 */
64 compatible = "fsl,aips-bus", "simple-bus";
67 reg = <0x50000000 0x10000000>;
71 compatible = "fsl,spba-bus", "simple-bus";
74 reg = <0x50000000 0x40000>;
77 esdhc@50004000 { /* ESDHC1 */
78 compatible = "fsl,imx53-esdhc";
79 reg = <0x50004000 0x4000>;
84 esdhc@50008000 { /* ESDHC2 */
85 compatible = "fsl,imx53-esdhc";
86 reg = <0x50008000 0x4000>;
91 uart3: serial@5000c000 {
92 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
93 reg = <0x5000c000 0x4000>;
98 ecspi@50010000 { /* ECSPI1 */
101 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
102 reg = <0x50010000 0x4000>;
108 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
109 reg = <0x50014000 0x4000>;
111 fsl,fifo-depth = <15>;
112 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
116 esdhc@50020000 { /* ESDHC3 */
117 compatible = "fsl,imx53-esdhc";
118 reg = <0x50020000 0x4000>;
123 esdhc@50024000 { /* ESDHC4 */
124 compatible = "fsl,imx53-esdhc";
125 reg = <0x50024000 0x4000>;
131 gpio1: gpio@53f84000 {
132 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
133 reg = <0x53f84000 0x4000>;
134 interrupts = <50 51>;
137 interrupt-controller;
138 #interrupt-cells = <2>;
141 gpio2: gpio@53f88000 {
142 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
143 reg = <0x53f88000 0x4000>;
144 interrupts = <52 53>;
147 interrupt-controller;
148 #interrupt-cells = <2>;
151 gpio3: gpio@53f8c000 {
152 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
153 reg = <0x53f8c000 0x4000>;
154 interrupts = <54 55>;
157 interrupt-controller;
158 #interrupt-cells = <2>;
161 gpio4: gpio@53f90000 {
162 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
163 reg = <0x53f90000 0x4000>;
164 interrupts = <56 57>;
167 interrupt-controller;
168 #interrupt-cells = <2>;
171 wdog@53f98000 { /* WDOG1 */
172 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
173 reg = <0x53f98000 0x4000>;
178 wdog@53f9c000 { /* WDOG2 */
179 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
180 reg = <0x53f9c000 0x4000>;
185 uart1: serial@53fbc000 {
186 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
187 reg = <0x53fbc000 0x4000>;
192 uart2: serial@53fc0000 {
193 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
194 reg = <0x53fc0000 0x4000>;
199 gpio5: gpio@53fdc000 {
200 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
201 reg = <0x53fdc000 0x4000>;
202 interrupts = <103 104>;
205 interrupt-controller;
206 #interrupt-cells = <2>;
209 gpio6: gpio@53fe0000 {
210 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
211 reg = <0x53fe0000 0x4000>;
212 interrupts = <105 106>;
215 interrupt-controller;
216 #interrupt-cells = <2>;
219 gpio7: gpio@53fe4000 {
220 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
221 reg = <0x53fe4000 0x4000>;
222 interrupts = <107 108>;
225 interrupt-controller;
226 #interrupt-cells = <2>;
229 i2c@53fec000 { /* I2C3 */
230 #address-cells = <1>;
232 compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
233 reg = <0x53fec000 0x4000>;
238 uart4: serial@53ff0000 {
239 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
240 reg = <0x53ff0000 0x4000>;
246 aips@60000000 { /* AIPS2 */
247 compatible = "fsl,aips-bus", "simple-bus";
248 #address-cells = <1>;
250 reg = <0x60000000 0x10000000>;
253 uart5: serial@63f90000 {
254 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
255 reg = <0x63f90000 0x4000>;
260 ecspi@63fac000 { /* ECSPI2 */
261 #address-cells = <1>;
263 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
264 reg = <0x63fac000 0x4000>;
270 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
271 reg = <0x63fb0000 0x4000>;
276 #address-cells = <1>;
278 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
279 reg = <0x63fc0000 0x4000>;
284 i2c@63fc4000 { /* I2C2 */
285 #address-cells = <1>;
287 compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
288 reg = <0x63fc4000 0x4000>;
293 i2c@63fc8000 { /* I2C1 */
294 #address-cells = <1>;
296 compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
297 reg = <0x63fc8000 0x4000>;
303 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
304 reg = <0x63fcc000 0x4000>;
306 fsl,fifo-depth = <15>;
307 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
312 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
313 reg = <0x63fd0000 0x4000>;
318 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
319 reg = <0x63fe8000 0x4000>;
321 fsl,fifo-depth = <15>;
322 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
327 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
328 reg = <0x63fec000 0x4000>;