arch/arm/boot/dts/imx53.dtsi

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include "skeleton.dtsi"
  14 #include "imx53-pinfunc.h"
  15
  16 / {
  17         aliases {
  18                 serial0 = &uart1;
  19                 serial1 = &uart2;
  20                 serial2 = &uart3;
  21                 serial3 = &uart4;
  22                 serial4 = &uart5;
  23                 gpio0 = &gpio1;
  24                 gpio1 = &gpio2;
  25                 gpio2 = &gpio3;
  26                 gpio3 = &gpio4;
  27                 gpio4 = &gpio5;
  28                 gpio5 = &gpio6;
  29                 gpio6 = &gpio7;
  30                 i2c0 = &i2c1;
  31                 i2c1 = &i2c2;
  32                 i2c2 = &i2c3;
  33         };
  34
  35         tzic: tz-interrupt-controller@0fffc000 {
  36                 compatible = "fsl,imx53-tzic", "fsl,tzic";
  37                 interrupt-controller;
  38                 #interrupt-cells = <1>;
  39                 reg = <0x0fffc000 0x4000>;
  40         };
  41
  42         clocks {
  43                 #address-cells = <1>;
  44                 #size-cells = <0>;
  45
  46                 ckil {
  47                         compatible = "fsl,imx-ckil", "fixed-clock";
  48                         clock-frequency = <32768>;
  49                 };
  50
  51                 ckih1 {
  52                         compatible = "fsl,imx-ckih1", "fixed-clock";
  53                         clock-frequency = <22579200>;
  54                 };
  55
  56                 ckih2 {
  57                         compatible = "fsl,imx-ckih2", "fixed-clock";
  58                         clock-frequency = <0>;
  59                 };
  60
  61                 osc {
  62                         compatible = "fsl,imx-osc", "fixed-clock";
  63                         clock-frequency = <24000000>;
  64                 };
  65         };
  66
  67         soc {
  68                 #address-cells = <1>;
  69                 #size-cells = <1>;
  70                 compatible = "simple-bus";
  71                 interrupt-parent = <&tzic>;
  72                 ranges;
  73
  74                 ipu: ipu@18000000 {
  75                         #crtc-cells = <1>;
  76                         compatible = "fsl,imx53-ipu";
  77                         reg = <0x18000000 0x080000000>;
  78                         interrupts = <11 10>;
  79                         clocks = <&clks 59>, <&clks 110>, <&clks 61>;
  80                         clock-names = "bus", "di0", "di1";
  81                         resets = <&src 2>;
  82                 };
  83
  84                 aips@50000000 { /* AIPS1 */
  85                         compatible = "fsl,aips-bus", "simple-bus";
  86                         #address-cells = <1>;
  87                         #size-cells = <1>;
  88                         reg = <0x50000000 0x10000000>;
  89                         ranges;
  90
  91                         spba@50000000 {
  92                                 compatible = "fsl,spba-bus", "simple-bus";
  93                                 #address-cells = <1>;
  94                                 #size-cells = <1>;
  95                                 reg = <0x50000000 0x40000>;
  96                                 ranges;
  97
  98                                 esdhc1: esdhc@50004000 {
  99                                         compatible = "fsl,imx53-esdhc";
 100                                         reg = <0x50004000 0x4000>;
 101                                         interrupts = <1>;
 102                                         clocks = <&clks 44>, <&clks 0>, <&clks 71>;
 103                                         clock-names = "ipg", "ahb", "per";
 104                                         bus-width = <4>;
 105                                         status = "disabled";
 106                                 };
 107
 108                                 esdhc2: esdhc@50008000 {
 109                                         compatible = "fsl,imx53-esdhc";
 110                                         reg = <0x50008000 0x4000>;
 111                                         interrupts = <2>;
 112                                         clocks = <&clks 45>, <&clks 0>, <&clks 72>;
 113                                         clock-names = "ipg", "ahb", "per";
 114                                         bus-width = <4>;
 115                                         status = "disabled";
 116                                 };
 117
 118                                 uart3: serial@5000c000 {
 119                                         compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 120                                         reg = <0x5000c000 0x4000>;
 121                                         interrupts = <33>;
 122                                         clocks = <&clks 32>, <&clks 33>;
 123                                         clock-names = "ipg", "per";
 124                                         status = "disabled";
 125                                 };
 126
 127                                 ecspi1: ecspi@50010000 {
 128                                         #address-cells = <1>;
 129                                         #size-cells = <0>;
 130                                         compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
 131                                         reg = <0x50010000 0x4000>;
 132                                         interrupts = <36>;
 133                                         clocks = <&clks 51>, <&clks 52>;
 134                                         clock-names = "ipg", "per";
 135                                         status = "disabled";
 136                                 };
 137
 138                                 ssi2: ssi@50014000 {
 139                                         compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
 140                                         reg = <0x50014000 0x4000>;
 141                                         interrupts = <30>;
 142                                         clocks = <&clks 49>;
 143                                         fsl,fifo-depth = <15>;
 144                                         fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
 145                                         status = "disabled";
 146                                 };
 147
 148                                 esdhc3: esdhc@50020000 {
 149                                         compatible = "fsl,imx53-esdhc";
 150                                         reg = <0x50020000 0x4000>;
 151                                         interrupts = <3>;
 152                                         clocks = <&clks 46>, <&clks 0>, <&clks 73>;
 153                                         clock-names = "ipg", "ahb", "per";
 154                                         bus-width = <4>;
 155                                         status = "disabled";
 156                                 };
 157
 158                                 esdhc4: esdhc@50024000 {
 159                                         compatible = "fsl,imx53-esdhc";
 160                                         reg = <0x50024000 0x4000>;
 161                                         interrupts = <4>;
 162                                         clocks = <&clks 47>, <&clks 0>, <&clks 74>;
 163                                         clock-names = "ipg", "ahb", "per";
 164                                         bus-width = <4>;
 165                                         status = "disabled";
 166                                 };
 167                         };
 168
 169                         usbphy0: usbphy@0 {
 170                                 compatible = "usb-nop-xceiv";
 171                                 clocks = <&clks 124>;
 172                                 clock-names = "main_clk";
 173                                 status = "okay";
 174                         };
 175
 176                         usbphy1: usbphy@1 {
 177                                 compatible = "usb-nop-xceiv";
 178                                 clocks = <&clks 125>;
 179                                 clock-names = "main_clk";
 180                                 status = "okay";
 181                         };
 182
 183                         usbotg: usb@53f80000 {
 184                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 185                                 reg = <0x53f80000 0x0200>;
 186                                 interrupts = <18>;
 187                                 clocks = <&clks 108>;
 188                                 fsl,usbmisc = <&usbmisc 0>;
 189                                 fsl,usbphy = <&usbphy0>;
 190                                 status = "disabled";
 191                         };
 192
 193                         usbh1: usb@53f80200 {
 194                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 195                                 reg = <0x53f80200 0x0200>;
 196                                 interrupts = <14>;
 197                                 clocks = <&clks 108>;
 198                                 fsl,usbmisc = <&usbmisc 1>;
 199                                 fsl,usbphy = <&usbphy1>;
 200                                 status = "disabled";
 201                         };
 202
 203                         usbh2: usb@53f80400 {
 204                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 205                                 reg = <0x53f80400 0x0200>;
 206                                 interrupts = <16>;
 207                                 clocks = <&clks 108>;
 208                                 fsl,usbmisc = <&usbmisc 2>;
 209                                 status = "disabled";
 210                         };
 211
 212                         usbh3: usb@53f80600 {
 213                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 214                                 reg = <0x53f80600 0x0200>;
 215                                 interrupts = <17>;
 216                                 clocks = <&clks 108>;
 217                                 fsl,usbmisc = <&usbmisc 3>;
 218                                 status = "disabled";
 219                         };
 220
 221                         usbmisc: usbmisc@53f80800 {
 222                                 #index-cells = <1>;
 223                                 compatible = "fsl,imx53-usbmisc";
 224                                 reg = <0x53f80800 0x200>;
 225                                 clocks = <&clks 108>;
 226                         };
 227
 228                         gpio1: gpio@53f84000 {
 229                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 230                                 reg = <0x53f84000 0x4000>;
 231                                 interrupts = <50 51>;
 232                                 gpio-controller;
 233                                 #gpio-cells = <2>;
 234                                 interrupt-controller;
 235                                 #interrupt-cells = <2>;
 236                         };
 237
 238                         gpio2: gpio@53f88000 {
 239                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 240                                 reg = <0x53f88000 0x4000>;
 241                                 interrupts = <52 53>;
 242                                 gpio-controller;
 243                                 #gpio-cells = <2>;
 244                                 interrupt-controller;
 245                                 #interrupt-cells = <2>;
 246                         };
 247
 248                         gpio3: gpio@53f8c000 {
 249                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 250                                 reg = <0x53f8c000 0x4000>;
 251                                 interrupts = <54 55>;
 252                                 gpio-controller;
 253                                 #gpio-cells = <2>;
 254                                 interrupt-controller;
 255                                 #interrupt-cells = <2>;
 256                         };
 257
 258                         gpio4: gpio@53f90000 {
 259                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 260                                 reg = <0x53f90000 0x4000>;
 261                                 interrupts = <56 57>;
 262                                 gpio-controller;
 263                                 #gpio-cells = <2>;
 264                                 interrupt-controller;
 265                                 #interrupt-cells = <2>;
 266                         };
 267
 268                         wdog1: wdog@53f98000 {
 269                                 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
 270                                 reg = <0x53f98000 0x4000>;
 271                                 interrupts = <58>;
 272                                 clocks = <&clks 0>;
 273                         };
 274
 275                         wdog2: wdog@53f9c000 {
 276                                 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
 277                                 reg = <0x53f9c000 0x4000>;
 278                                 interrupts = <59>;
 279                                 clocks = <&clks 0>;
 280                                 status = "disabled";
 281                         };
 282
 283                         gpt: timer@53fa0000 {
 284                                 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
 285                                 reg = <0x53fa0000 0x4000>;
 286                                 interrupts = <39>;
 287                                 clocks = <&clks 36>, <&clks 41>;
 288                                 clock-names = "ipg", "per";
 289                         };
 290
 291                         iomuxc: iomuxc@53fa8000 {
 292                                 compatible = "fsl,imx53-iomuxc";
 293                                 reg = <0x53fa8000 0x4000>;
 294
 295                                 audmux {
 296                                         pinctrl_audmux_1: audmuxgrp-1 {
 297                                                 fsl,pins = <
 298                                                         MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC  0x80000000
 299                                                         MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD  0x80000000
 300                                                         MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
 301                                                         MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD  0x80000000
 302                                                 >;
 303                                         };
 304
 305                                         pinctrl_audmux_2: audmuxgrp-2 {
 306                                                 fsl,pins = <
 307                                                         MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC     0x80000000
 308                                                         MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD     0x80000000
 309                                                         MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS    0x80000000
 310                                                         MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD     0x80000000
 311                                                 >;
 312                                         };
 313                                 };
 314
 315                                 fec {
 316                                         pinctrl_fec_1: fecgrp-1 {
 317                                                 fsl,pins = <
 318                                                         MX53_PAD_FEC_MDC__FEC_MDC        0x80000000
 319                                                         MX53_PAD_FEC_MDIO__FEC_MDIO      0x80000000
 320                                                         MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
 321                                                         MX53_PAD_FEC_RX_ER__FEC_RX_ER    0x80000000
 322                                                         MX53_PAD_FEC_CRS_DV__FEC_RX_DV   0x80000000
 323                                                         MX53_PAD_FEC_RXD1__FEC_RDATA_1   0x80000000
 324                                                         MX53_PAD_FEC_RXD0__FEC_RDATA_0   0x80000000
 325                                                         MX53_PAD_FEC_TX_EN__FEC_TX_EN    0x80000000
 326                                                         MX53_PAD_FEC_TXD1__FEC_TDATA_1   0x80000000
 327                                                         MX53_PAD_FEC_TXD0__FEC_TDATA_0   0x80000000
 328                                                 >;
 329                                         };
 330                                 };
 331
 332                                 csi {
 333                                         pinctrl_csi_1: csigrp-1 {
 334                                                 fsl,pins = <
 335                                                         MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x1d5
 336                                                         MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC     0x1d5
 337                                                         MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC      0x1d5
 338                                                         MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK   0x1d5
 339                                                         MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19      0x1d5
 340                                                         MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18      0x1d5
 341                                                         MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17      0x1d5
 342                                                         MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16      0x1d5
 343                                                         MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15      0x1d5
 344                                                         MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14      0x1d5
 345                                                         MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13      0x1d5
 346                                                         MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12      0x1d5
 347                                                         MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11      0x1d5
 348                                                         MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10      0x1d5
 349                                                         MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9        0x1d5
 350                                                         MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8        0x1d5
 351                                                         MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7        0x1d5
 352                                                         MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6        0x1d5
 353                                                         MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5        0x1d5
 354                                                         MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4        0x1d5
 355                                                         MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK   0x1d5
 356                                                 >;
 357                                         };
 358                                 };
 359
 360                                 cspi {
 361                                         pinctrl_cspi_1: cspigrp-1 {
 362                                                 fsl,pins = <
 363                                                         MX53_PAD_SD1_DATA0__CSPI_MISO 0x1d5
 364                                                         MX53_PAD_SD1_CMD__CSPI_MOSI   0x1d5
 365                                                         MX53_PAD_SD1_CLK__CSPI_SCLK   0x1d5
 366                                                 >;
 367                                         };
 368                                 };
 369
 370                                 ecspi1 {
 371                                         pinctrl_ecspi1_1: ecspi1grp-1 {
 372                                                 fsl,pins = <
 373                                                         MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
 374                                                         MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
 375                                                         MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
 376                                                 >;
 377                                         };
 378                                 };
 379
 380                                 esdhc1 {
 381                                         pinctrl_esdhc1_1: esdhc1grp-1 {
 382                                                 fsl,pins = <
 383                                                         MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
 384                                                         MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
 385                                                         MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
 386                                                         MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
 387                                                         MX53_PAD_SD1_CMD__ESDHC1_CMD    0x1d5
 388                                                         MX53_PAD_SD1_CLK__ESDHC1_CLK    0x1d5
 389                                                 >;
 390                                         };
 391
 392                                         pinctrl_esdhc1_2: esdhc1grp-2 {
 393                                                 fsl,pins = <
 394                                                         MX53_PAD_SD1_DATA0__ESDHC1_DAT0   0x1d5
 395                                                         MX53_PAD_SD1_DATA1__ESDHC1_DAT1   0x1d5
 396                                                         MX53_PAD_SD1_DATA2__ESDHC1_DAT2   0x1d5
 397                                                         MX53_PAD_SD1_DATA3__ESDHC1_DAT3   0x1d5
 398                                                         MX53_PAD_PATA_DATA8__ESDHC1_DAT4  0x1d5
 399                                                         MX53_PAD_PATA_DATA9__ESDHC1_DAT5  0x1d5
 400                                                         MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x1d5
 401                                                         MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x1d5
 402                                                         MX53_PAD_SD1_CMD__ESDHC1_CMD      0x1d5
 403                                                         MX53_PAD_SD1_CLK__ESDHC1_CLK      0x1d5
 404                                                 >;
 405                                         };
 406                                 };
 407
 408                                 esdhc2 {
 409                                         pinctrl_esdhc2_1: esdhc2grp-1 {
 410                                                 fsl,pins = <
 411                                                         MX53_PAD_SD2_CMD__ESDHC2_CMD    0x1d5
 412                                                         MX53_PAD_SD2_CLK__ESDHC2_CLK    0x1d5
 413                                                         MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
 414                                                         MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
 415                                                         MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
 416                                                         MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
 417                                                 >;
 418                                         };
 419                                 };
 420
 421                                 esdhc3 {
 422                                         pinctrl_esdhc3_1: esdhc3grp-1 {
 423                                                 fsl,pins = <
 424                                                         MX53_PAD_PATA_DATA8__ESDHC3_DAT0  0x1d5
 425                                                         MX53_PAD_PATA_DATA9__ESDHC3_DAT1  0x1d5
 426                                                         MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
 427                                                         MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
 428                                                         MX53_PAD_PATA_DATA0__ESDHC3_DAT4  0x1d5
 429                                                         MX53_PAD_PATA_DATA1__ESDHC3_DAT5  0x1d5
 430                                                         MX53_PAD_PATA_DATA2__ESDHC3_DAT6  0x1d5
 431                                                         MX53_PAD_PATA_DATA3__ESDHC3_DAT7  0x1d5
 432                                                         MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
 433                                                         MX53_PAD_PATA_IORDY__ESDHC3_CLK   0x1d5
 434                                                 >;
 435                                         };
 436                                 };
 437
 438                                 can1 {
 439                                         pinctrl_can1_1: can1grp-1 {
 440                                                 fsl,pins = <
 441                                                         MX53_PAD_PATA_INTRQ__CAN1_TXCAN 0x80000000
 442                                                         MX53_PAD_PATA_DIOR__CAN1_RXCAN  0x80000000
 443                                                 >;
 444                                         };
 445
 446                                         pinctrl_can1_2: can1grp-2 {
 447                                                 fsl,pins = <
 448                                                         MX53_PAD_KEY_COL2__CAN1_TXCAN 0x80000000
 449                                                         MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000
 450                                                 >;
 451                                         };
 452
 453                                         pinctrl_can1_3: can1grp-3 {
 454                                                 fsl,pins = <
 455                                                         MX53_PAD_GPIO_7__CAN1_TXCAN     0x80000000
 456                                                         MX53_PAD_GPIO_8__CAN1_RXCAN     0x80000000
 457                                                 >;
 458                                         };
 459                                 };
 460
 461                                 can2 {
 462                                         pinctrl_can2_1: can2grp-1 {
 463                                                 fsl,pins = <
 464                                                         MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000
 465                                                         MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000
 466                                                 >;
 467                                         };
 468                                 };
 469
 470                                 i2c1 {
 471                                         pinctrl_i2c1_1: i2c1grp-1 {
 472                                                 fsl,pins = <
 473                                                         MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000
 474                                                         MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000
 475                                                 >;
 476                                         };
 477                                 };
 478
 479                                 i2c2 {
 480                                         pinctrl_i2c2_1: i2c2grp-1 {
 481                                                 fsl,pins = <
 482                                                         MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
 483                                                         MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
 484                                                 >;
 485                                         };
 486                                 };
 487
 488                                 i2c3 {
 489                                         pinctrl_i2c3_1: i2c3grp-1 {
 490                                                 fsl,pins = <
 491                                                         MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
 492                                                         MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000
 493                                                 >;
 494                                         };
 495                                 };
 496
 497                                 owire {
 498                                         pinctrl_owire_1: owiregrp-1 {
 499                                                 fsl,pins = <
 500                                                         MX53_PAD_GPIO_18__OWIRE_LINE 0x80000000
 501                                                 >;
 502                                         };
 503                                 };
 504
 505                                 uart1 {
 506                                         pinctrl_uart1_1: uart1grp-1 {
 507                                                 fsl,pins = <
 508                                                         MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1c5
 509                                                         MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1c5
 510                                                 >;
 511                                         };
 512
 513                                         pinctrl_uart1_2: uart1grp-2 {
 514                                                 fsl,pins = <
 515                                                         MX53_PAD_PATA_DIOW__UART1_TXD_MUX  0x1c5
 516                                                         MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1c5
 517                                                 >;
 518                                         };
 519                                 };
 520
 521                                 uart2 {
 522                                         pinctrl_uart2_1: uart2grp-1 {
 523                                                 fsl,pins = <
 524                                                         MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1c5
 525                                                         MX53_PAD_PATA_DMARQ__UART2_TXD_MUX     0x1c5
 526                                                 >;
 527                                         };
 528                                 };
 529
 530                                 uart3 {
 531                                         pinctrl_uart3_1: uart3grp-1 {
 532                                                 fsl,pins = <
 533                                                         MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1c5
 534                                                         MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1c5
 535                                                         MX53_PAD_PATA_DA_1__UART3_CTS     0x1c5
 536                                                         MX53_PAD_PATA_DA_2__UART3_RTS     0x1c5
 537                                                 >;
 538                                         };
 539
 540                                         pinctrl_uart3_2: uart3grp-2 {
 541                                                 fsl,pins = <
 542                                                         MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1c5
 543                                                         MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1c5
 544                                                 >;
 545                                         };
 546
 547                                 };
 548
 549                                 uart4 {
 550                                         pinctrl_uart4_1: uart4grp-1 {
 551                                                 fsl,pins = <
 552                                                         MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1c5
 553                                                         MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1c5
 554                                                 >;
 555                                         };
 556                                 };
 557
 558                                 uart5 {
 559                                         pinctrl_uart5_1: uart5grp-1 {
 560                                                 fsl,pins = <
 561                                                         MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x1c5
 562                                                         MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x1c5
 563                                                 >;
 564                                         };
 565                                 };
 566
 567                         };
 568
 569                         gpr: iomuxc-gpr@53fa8000 {
 570                                 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
 571                                 reg = <0x53fa8000 0xc>;
 572                         };
 573
 574                         ldb: ldb@53fa8008 {
 575                                 #address-cells = <1>;
 576                                 #size-cells = <0>;
 577                                 compatible = "fsl,imx53-ldb";
 578                                 reg = <0x53fa8008 0x4>;
 579                                 gpr = <&gpr>;
 580                                 clocks = <&clks 122>, <&clks 120>,
 581                                          <&clks 115>, <&clks 116>,
 582                                          <&clks 123>, <&clks 85>;
 583                                 clock-names = "di0_pll", "di1_pll",
 584                                               "di0_sel", "di1_sel",
 585                                               "di0", "di1";
 586                                 status = "disabled";
 587
 588                                 lvds-channel@0 {
 589                                         reg = <0>;
 590                                         crtcs = <&ipu 0>;
 591                                         status = "disabled";
 592                                 };
 593
 594                                 lvds-channel@1 {
 595                                         reg = <1>;
 596                                         crtcs = <&ipu 1>;
 597                                         status = "disabled";
 598                                 };
 599                         };
 600
 601                         pwm1: pwm@53fb4000 {
 602                                 #pwm-cells = <2>;
 603                                 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
 604                                 reg = <0x53fb4000 0x4000>;
 605                                 clocks = <&clks 37>, <&clks 38>;
 606                                 clock-names = "ipg", "per";
 607                                 interrupts = <61>;
 608                         };
 609
 610                         pwm2: pwm@53fb8000 {
 611                                 #pwm-cells = <2>;
 612                                 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
 613                                 reg = <0x53fb8000 0x4000>;
 614                                 clocks = <&clks 39>, <&clks 40>;
 615                                 clock-names = "ipg", "per";
 616                                 interrupts = <94>;
 617                         };
 618
 619                         uart1: serial@53fbc000 {
 620                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 621                                 reg = <0x53fbc000 0x4000>;
 622                                 interrupts = <31>;
 623                                 clocks = <&clks 28>, <&clks 29>;
 624                                 clock-names = "ipg", "per";
 625                                 status = "disabled";
 626                         };
 627
 628                         uart2: serial@53fc0000 {
 629                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 630                                 reg = <0x53fc0000 0x4000>;
 631                                 interrupts = <32>;
 632                                 clocks = <&clks 30>, <&clks 31>;
 633                                 clock-names = "ipg", "per";
 634                                 status = "disabled";
 635                         };
 636
 637                         can1: can@53fc8000 {
 638                                 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
 639                                 reg = <0x53fc8000 0x4000>;
 640                                 interrupts = <82>;
 641                                 clocks = <&clks 158>, <&clks 157>;
 642                                 clock-names = "ipg", "per";
 643                                 status = "disabled";
 644                         };
 645
 646                         can2: can@53fcc000 {
 647                                 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
 648                                 reg = <0x53fcc000 0x4000>;
 649                                 interrupts = <83>;
 650                                 clocks = <&clks 87>, <&clks 86>;
 651                                 clock-names = "ipg", "per";
 652                                 status = "disabled";
 653                         };
 654
 655                         src: src@53fd0000 {
 656                                 compatible = "fsl,imx53-src", "fsl,imx51-src";
 657                                 reg = <0x53fd0000 0x4000>;
 658                                 #reset-cells = <1>;
 659                         };
 660
 661                         clks: ccm@53fd4000{
 662                                 compatible = "fsl,imx53-ccm";
 663                                 reg = <0x53fd4000 0x4000>;
 664                                 interrupts = <0 71 0x04 0 72 0x04>;
 665                                 #clock-cells = <1>;
 666                         };
 667
 668                         gpio5: gpio@53fdc000 {
 669                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 670                                 reg = <0x53fdc000 0x4000>;
 671                                 interrupts = <103 104>;
 672                                 gpio-controller;
 673                                 #gpio-cells = <2>;
 674                                 interrupt-controller;
 675                                 #interrupt-cells = <2>;
 676                         };
 677
 678                         gpio6: gpio@53fe0000 {
 679                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 680                                 reg = <0x53fe0000 0x4000>;
 681                                 interrupts = <105 106>;
 682                                 gpio-controller;
 683                                 #gpio-cells = <2>;
 684                                 interrupt-controller;
 685                                 #interrupt-cells = <2>;
 686                         };
 687
 688                         gpio7: gpio@53fe4000 {
 689                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 690                                 reg = <0x53fe4000 0x4000>;
 691                                 interrupts = <107 108>;
 692                                 gpio-controller;
 693                                 #gpio-cells = <2>;
 694                                 interrupt-controller;
 695                                 #interrupt-cells = <2>;
 696                         };
 697
 698                         i2c3: i2c@53fec000 {
 699                                 #address-cells = <1>;
 700                                 #size-cells = <0>;
 701                                 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
 702                                 reg = <0x53fec000 0x4000>;
 703                                 interrupts = <64>;
 704                                 clocks = <&clks 88>;
 705                                 status = "disabled";
 706                         };
 707
 708                         uart4: serial@53ff0000 {
 709                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 710                                 reg = <0x53ff0000 0x4000>;
 711                                 interrupts = <13>;
 712                                 clocks = <&clks 65>, <&clks 66>;
 713                                 clock-names = "ipg", "per";
 714                                 status = "disabled";
 715                         };
 716                 };
 717
 718                 aips@60000000 { /* AIPS2 */
 719                         compatible = "fsl,aips-bus", "simple-bus";
 720                         #address-cells = <1>;
 721                         #size-cells = <1>;
 722                         reg = <0x60000000 0x10000000>;
 723                         ranges;
 724
 725                         uart5: serial@63f90000 {
 726                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 727                                 reg = <0x63f90000 0x4000>;
 728                                 interrupts = <86>;
 729                                 clocks = <&clks 67>, <&clks 68>;
 730                                 clock-names = "ipg", "per";
 731                                 status = "disabled";
 732                         };
 733
 734                         owire: owire@63fa4000 {
 735                                 compatible = "fsl,imx53-owire", "fsl,imx21-owire";
 736                                 reg = <0x63fa4000 0x4000>;
 737                                 clocks = <&clks 159>;
 738                                 status = "disabled";
 739                         };
 740
 741                         ecspi2: ecspi@63fac000 {
 742                                 #address-cells = <1>;
 743                                 #size-cells = <0>;
 744                                 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
 745                                 reg = <0x63fac000 0x4000>;
 746                                 interrupts = <37>;
 747                                 clocks = <&clks 53>, <&clks 54>;
 748                                 clock-names = "ipg", "per";
 749                                 status = "disabled";
 750                         };
 751
 752                         sdma: sdma@63fb0000 {
 753                                 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
 754                                 reg = <0x63fb0000 0x4000>;
 755                                 interrupts = <6>;
 756                                 clocks = <&clks 56>, <&clks 56>;
 757                                 clock-names = "ipg", "ahb";
 758                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
 759                         };
 760
 761                         cspi: cspi@63fc0000 {
 762                                 #address-cells = <1>;
 763                                 #size-cells = <0>;
 764                                 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
 765                                 reg = <0x63fc0000 0x4000>;
 766                                 interrupts = <38>;
 767                                 clocks = <&clks 55>, <&clks 55>;
 768                                 clock-names = "ipg", "per";
 769                                 status = "disabled";
 770                         };
 771
 772                         i2c2: i2c@63fc4000 {
 773                                 #address-cells = <1>;
 774                                 #size-cells = <0>;
 775                                 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
 776                                 reg = <0x63fc4000 0x4000>;
 777                                 interrupts = <63>;
 778                                 clocks = <&clks 35>;
 779                                 status = "disabled";
 780                         };
 781
 782                         i2c1: i2c@63fc8000 {
 783                                 #address-cells = <1>;
 784                                 #size-cells = <0>;
 785                                 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
 786                                 reg = <0x63fc8000 0x4000>;
 787                                 interrupts = <62>;
 788                                 clocks = <&clks 34>;
 789                                 status = "disabled";
 790                         };
 791
 792                         ssi1: ssi@63fcc000 {
 793                                 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
 794                                 reg = <0x63fcc000 0x4000>;
 795                                 interrupts = <29>;
 796                                 clocks = <&clks 48>;
 797                                 fsl,fifo-depth = <15>;
 798                                 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
 799                                 status = "disabled";
 800                         };
 801
 802                         audmux: audmux@63fd0000 {
 803                                 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
 804                                 reg = <0x63fd0000 0x4000>;
 805                                 status = "disabled";
 806                         };
 807
 808                         nfc: nand@63fdb000 {
 809                                 compatible = "fsl,imx53-nand";
 810                                 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
 811                                 interrupts = <8>;
 812                                 clocks = <&clks 60>;
 813                                 status = "disabled";
 814                         };
 815
 816                         ssi3: ssi@63fe8000 {
 817                                 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
 818                                 reg = <0x63fe8000 0x4000>;
 819                                 interrupts = <96>;
 820                                 clocks = <&clks 50>;
 821                                 fsl,fifo-depth = <15>;
 822                                 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
 823                                 status = "disabled";
 824                         };
 825
 826                         fec: ethernet@63fec000 {
 827                                 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
 828                                 reg = <0x63fec000 0x4000>;
 829                                 interrupts = <87>;
 830                                 clocks = <&clks 42>, <&clks 42>, <&clks 42>;
 831                                 clock-names = "ipg", "ahb", "ptp";
 832                                 status = "disabled";
 833                         };
 834                 };
 835         };
 836 };