2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 /include/ "skeleton.dtsi"
31 tzic: tz-interrupt-controller@0fffc000 {
32 compatible = "fsl,imx53-tzic", "fsl,tzic";
34 #interrupt-cells = <1>;
35 reg = <0x0fffc000 0x4000>;
43 compatible = "fsl,imx-ckil", "fixed-clock";
44 clock-frequency = <32768>;
48 compatible = "fsl,imx-ckih1", "fixed-clock";
49 clock-frequency = <22579200>;
53 compatible = "fsl,imx-ckih2", "fixed-clock";
54 clock-frequency = <0>;
58 compatible = "fsl,imx-osc", "fixed-clock";
59 clock-frequency = <24000000>;
66 compatible = "simple-bus";
67 interrupt-parent = <&tzic>;
72 compatible = "fsl,imx53-ipu";
73 reg = <0x18000000 0x080000000>;
77 aips@50000000 { /* AIPS1 */
78 compatible = "fsl,aips-bus", "simple-bus";
81 reg = <0x50000000 0x10000000>;
85 compatible = "fsl,spba-bus", "simple-bus";
88 reg = <0x50000000 0x40000>;
91 esdhc1: esdhc@50004000 {
92 compatible = "fsl,imx53-esdhc";
93 reg = <0x50004000 0x4000>;
95 clocks = <&clks 44>, <&clks 0>, <&clks 71>;
96 clock-names = "ipg", "ahb", "per";
101 esdhc2: esdhc@50008000 {
102 compatible = "fsl,imx53-esdhc";
103 reg = <0x50008000 0x4000>;
105 clocks = <&clks 45>, <&clks 0>, <&clks 72>;
106 clock-names = "ipg", "ahb", "per";
111 uart3: serial@5000c000 {
112 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
113 reg = <0x5000c000 0x4000>;
115 clocks = <&clks 32>, <&clks 33>;
116 clock-names = "ipg", "per";
120 ecspi1: ecspi@50010000 {
121 #address-cells = <1>;
123 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
124 reg = <0x50010000 0x4000>;
126 clocks = <&clks 51>, <&clks 52>;
127 clock-names = "ipg", "per";
132 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
133 reg = <0x50014000 0x4000>;
136 fsl,fifo-depth = <15>;
137 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
141 esdhc3: esdhc@50020000 {
142 compatible = "fsl,imx53-esdhc";
143 reg = <0x50020000 0x4000>;
145 clocks = <&clks 46>, <&clks 0>, <&clks 73>;
146 clock-names = "ipg", "ahb", "per";
151 esdhc4: esdhc@50024000 {
152 compatible = "fsl,imx53-esdhc";
153 reg = <0x50024000 0x4000>;
155 clocks = <&clks 47>, <&clks 0>, <&clks 74>;
156 clock-names = "ipg", "ahb", "per";
162 usbotg: usb@53f80000 {
163 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
164 reg = <0x53f80000 0x0200>;
169 usbh1: usb@53f80200 {
170 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
171 reg = <0x53f80200 0x0200>;
176 usbh2: usb@53f80400 {
177 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
178 reg = <0x53f80400 0x0200>;
183 usbh3: usb@53f80600 {
184 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
185 reg = <0x53f80600 0x0200>;
190 gpio1: gpio@53f84000 {
191 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
192 reg = <0x53f84000 0x4000>;
193 interrupts = <50 51>;
196 interrupt-controller;
197 #interrupt-cells = <2>;
200 gpio2: gpio@53f88000 {
201 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
202 reg = <0x53f88000 0x4000>;
203 interrupts = <52 53>;
206 interrupt-controller;
207 #interrupt-cells = <2>;
210 gpio3: gpio@53f8c000 {
211 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
212 reg = <0x53f8c000 0x4000>;
213 interrupts = <54 55>;
216 interrupt-controller;
217 #interrupt-cells = <2>;
220 gpio4: gpio@53f90000 {
221 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
222 reg = <0x53f90000 0x4000>;
223 interrupts = <56 57>;
226 interrupt-controller;
227 #interrupt-cells = <2>;
230 wdog1: wdog@53f98000 {
231 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
232 reg = <0x53f98000 0x4000>;
237 wdog2: wdog@53f9c000 {
238 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
239 reg = <0x53f9c000 0x4000>;
245 iomuxc: iomuxc@53fa8000 {
246 compatible = "fsl,imx53-iomuxc";
247 reg = <0x53fa8000 0x4000>;
250 pinctrl_audmux_1: audmuxgrp-1 {
252 10 0x80000000 /* MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC */
253 17 0x80000000 /* MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */
254 23 0x80000000 /* MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */
255 30 0x80000000 /* MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */
261 pinctrl_fec_1: fecgrp-1 {
263 820 0x80000000 /* MX53_PAD_FEC_MDC__FEC_MDC */
264 779 0x80000000 /* MX53_PAD_FEC_MDIO__FEC_MDIO */
265 786 0x80000000 /* MX53_PAD_FEC_REF_CLK__FEC_TX_CLK */
266 791 0x80000000 /* MX53_PAD_FEC_RX_ER__FEC_RX_ER */
267 796 0x80000000 /* MX53_PAD_FEC_CRS_DV__FEC_RX_DV */
268 799 0x80000000 /* MX53_PAD_FEC_RXD1__FEC_RDATA_1 */
269 804 0x80000000 /* MX53_PAD_FEC_RXD0__FEC_RDATA_0 */
270 808 0x80000000 /* MX53_PAD_FEC_TX_EN__FEC_TX_EN */
271 811 0x80000000 /* MX53_PAD_FEC_TXD1__FEC_TDATA_1 */
272 816 0x80000000 /* MX53_PAD_FEC_TXD0__FEC_TDATA_0 */
278 pinctrl_ecspi1_1: ecspi1grp-1 {
280 433 0x80000000 /* MX53_PAD_EIM_D16__ECSPI1_SCLK */
281 439 0x80000000 /* MX53_PAD_EIM_D17__ECSPI1_MISO */
282 445 0x80000000 /* MX53_PAD_EIM_D18__ECSPI1_MOSI */
288 pinctrl_esdhc1_1: esdhc1grp-1 {
290 995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
291 1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
292 1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
293 1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
294 1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
295 1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
299 pinctrl_esdhc1_2: esdhc1grp-2 {
301 995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
302 1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
303 1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
304 1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
305 941 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC1_DAT4 */
306 948 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC1_DAT5 */
307 955 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC1_DAT6 */
308 962 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC1_DAT7 */
309 1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
310 1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
316 pinctrl_esdhc2_1: esdhc2grp-1 {
318 1038 0x1d5 /* MX53_PAD_SD2_CMD__ESDHC2_CMD */
319 1032 0x1d5 /* MX53_PAD_SD2_CLK__ESDHC2_CLK */
320 1062 0x1d5 /* MX53_PAD_SD2_DATA0__ESDHC2_DAT0 */
321 1056 0x1d5 /* MX53_PAD_SD2_DATA1__ESDHC2_DAT1 */
322 1050 0x1d5 /* MX53_PAD_SD2_DATA2__ESDHC2_DAT2 */
323 1044 0x1d5 /* MX53_PAD_SD2_DATA3__ESDHC2_DAT3 */
329 pinctrl_esdhc3_1: esdhc3grp-1 {
331 943 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC3_DAT0 */
332 950 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC3_DAT1 */
333 957 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC3_DAT2 */
334 964 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC3_DAT3 */
335 893 0x1d5 /* MX53_PAD_PATA_DATA0__ESDHC3_DAT4 */
336 900 0x1d5 /* MX53_PAD_PATA_DATA1__ESDHC3_DAT5 */
337 906 0x1d5 /* MX53_PAD_PATA_DATA2__ESDHC3_DAT6 */
338 912 0x1d5 /* MX53_PAD_PATA_DATA3__ESDHC3_DAT7 */
339 857 0x1d5 /* MX53_PAD_PATA_RESET_B__ESDHC3_CMD */
340 863 0x1d5 /* MX53_PAD_PATA_IORDY__ESDHC3_CLK */
346 pinctrl_can1_1: can1grp-1 {
348 847 0x80000000 /* MX53_PAD_PATA_INTRQ__CAN1_TXCAN */
349 853 0x80000000 /* MX53_PAD_PATA_DIOR__CAN1_RXCAN */
355 pinctrl_can2_1: can2grp-1 {
357 67 0x80000000 /* MX53_PAD_KEY_COL4__CAN2_TXCAN */
358 74 0x80000000 /* MX53_PAD_KEY_ROW4__CAN2_RXCAN */
364 pinctrl_i2c1_1: i2c1grp-1 {
366 333 0xc0000000 /* MX53_PAD_CSI0_DAT8__I2C1_SDA */
367 341 0xc0000000 /* MX53_PAD_CSI0_DAT9__I2C1_SCL */
373 pinctrl_i2c2_1: i2c2grp-1 {
375 61 0xc0000000 /* MX53_PAD_KEY_ROW3__I2C2_SDA */
376 53 0xc0000000 /* MX53_PAD_KEY_COL3__I2C2_SCL */
382 pinctrl_i2c3_1: i2c3grp-1 {
384 1102 0xc0000000 /* MX53_PAD_GPIO_6__I2C3_SDA */
385 1130 0xc0000000 /* MX53_PAD_GPIO_5__I2C3_SCL */
391 pinctrl_uart1_1: uart1grp-1 {
393 346 0x1c5 /* MX53_PAD_CSI0_DAT10__UART1_TXD_MUX */
394 354 0x1c5 /* MX53_PAD_CSI0_DAT11__UART1_RXD_MUX */
398 pinctrl_uart1_2: uart1grp-2 {
400 828 0x1c5 /* MX53_PAD_PATA_DIOW__UART1_TXD_MUX */
401 832 0x1c5 /* MX53_PAD_PATA_DMACK__UART1_RXD_MUX */
407 pinctrl_uart2_1: uart2grp-1 {
409 841 0x1c5 /* MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX */
410 836 0x1c5 /* MX53_PAD_PATA_DMARQ__UART2_TXD_MUX */
416 pinctrl_uart3_1: uart3grp-1 {
418 884 0x1c5 /* MX53_PAD_PATA_CS_0__UART3_TXD_MUX */
419 888 0x1c5 /* MX53_PAD_PATA_CS_1__UART3_RXD_MUX */
420 875 0x1c5 /* MX53_PAD_PATA_DA_1__UART3_CTS */
421 880 0x1c5 /* MX53_PAD_PATA_DA_2__UART3_RTS */
427 pinctrl_uart4_1: uart4grp-1 {
429 11 0x1c5 /* MX53_PAD_KEY_COL0__UART4_TXD_MUX */
430 18 0x1c5 /* MX53_PAD_KEY_ROW0__UART4_RXD_MUX */
436 pinctrl_uart5_1: uart5grp-1 {
438 24 0x1c5 /* MX53_PAD_KEY_COL1__UART5_TXD_MUX */
439 31 0x1c5 /* MX53_PAD_KEY_ROW1__UART5_RXD_MUX */
448 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
449 reg = <0x53fb4000 0x4000>;
450 clocks = <&clks 37>, <&clks 38>;
451 clock-names = "ipg", "per";
457 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
458 reg = <0x53fb8000 0x4000>;
459 clocks = <&clks 39>, <&clks 40>;
460 clock-names = "ipg", "per";
464 uart1: serial@53fbc000 {
465 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
466 reg = <0x53fbc000 0x4000>;
468 clocks = <&clks 28>, <&clks 29>;
469 clock-names = "ipg", "per";
473 uart2: serial@53fc0000 {
474 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
475 reg = <0x53fc0000 0x4000>;
477 clocks = <&clks 30>, <&clks 31>;
478 clock-names = "ipg", "per";
483 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
484 reg = <0x53fc8000 0x4000>;
486 clocks = <&clks 158>, <&clks 157>;
487 clock-names = "ipg", "per";
492 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
493 reg = <0x53fcc000 0x4000>;
495 clocks = <&clks 87>, <&clks 86>;
496 clock-names = "ipg", "per";
501 compatible = "fsl,imx53-ccm";
502 reg = <0x53fd4000 0x4000>;
503 interrupts = <0 71 0x04 0 72 0x04>;
507 gpio5: gpio@53fdc000 {
508 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
509 reg = <0x53fdc000 0x4000>;
510 interrupts = <103 104>;
513 interrupt-controller;
514 #interrupt-cells = <2>;
517 gpio6: gpio@53fe0000 {
518 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
519 reg = <0x53fe0000 0x4000>;
520 interrupts = <105 106>;
523 interrupt-controller;
524 #interrupt-cells = <2>;
527 gpio7: gpio@53fe4000 {
528 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
529 reg = <0x53fe4000 0x4000>;
530 interrupts = <107 108>;
533 interrupt-controller;
534 #interrupt-cells = <2>;
538 #address-cells = <1>;
540 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
541 reg = <0x53fec000 0x4000>;
547 uart4: serial@53ff0000 {
548 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
549 reg = <0x53ff0000 0x4000>;
551 clocks = <&clks 65>, <&clks 66>;
552 clock-names = "ipg", "per";
557 aips@60000000 { /* AIPS2 */
558 compatible = "fsl,aips-bus", "simple-bus";
559 #address-cells = <1>;
561 reg = <0x60000000 0x10000000>;
564 uart5: serial@63f90000 {
565 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
566 reg = <0x63f90000 0x4000>;
568 clocks = <&clks 67>, <&clks 68>;
569 clock-names = "ipg", "per";
573 ecspi2: ecspi@63fac000 {
574 #address-cells = <1>;
576 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
577 reg = <0x63fac000 0x4000>;
579 clocks = <&clks 53>, <&clks 54>;
580 clock-names = "ipg", "per";
584 sdma: sdma@63fb0000 {
585 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
586 reg = <0x63fb0000 0x4000>;
588 clocks = <&clks 56>, <&clks 56>;
589 clock-names = "ipg", "ahb";
590 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
593 cspi: cspi@63fc0000 {
594 #address-cells = <1>;
596 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
597 reg = <0x63fc0000 0x4000>;
599 clocks = <&clks 55>, <&clks 0>;
600 clock-names = "ipg", "per";
605 #address-cells = <1>;
607 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
608 reg = <0x63fc4000 0x4000>;
615 #address-cells = <1>;
617 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
618 reg = <0x63fc8000 0x4000>;
625 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
626 reg = <0x63fcc000 0x4000>;
629 fsl,fifo-depth = <15>;
630 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
634 audmux: audmux@63fd0000 {
635 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
636 reg = <0x63fd0000 0x4000>;
641 compatible = "fsl,imx53-nand";
642 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
649 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
650 reg = <0x63fe8000 0x4000>;
653 fsl,fifo-depth = <15>;
654 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
658 fec: ethernet@63fec000 {
659 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
660 reg = <0x63fec000 0x4000>;
662 clocks = <&clks 42>, <&clks 42>, <&clks 42>;
663 clock-names = "ipg", "ahb", "ptp";