arch/arm/boot/dts/imx6q-sabrelite.dts

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 /dts-v1/;
  14 /include/ "imx6q.dtsi"
  15
  16 / {
  17         model = "Freescale i.MX6 Quad SABRE Lite Board";
  18         compatible = "fsl,imx6q-sabrelite", "fsl,imx6q";
  19
  20         memory {
  21                 reg = <0x10000000 0x40000000>;
  22         };
  23
  24         soc {
  25                 aips-bus@02100000 { /* AIPS2 */
  26                         ethernet@02188000 {
  27                                 phy-mode = "rgmii";
  28                                 phy-reset-gpios = <&gpio3 23 0>;
  29                                 status = "okay";
  30                         };
  31
  32                         usdhc@02198000 { /* uSDHC3 */
  33                                 cd-gpios = <&gpio7 0 0>;
  34                                 wp-gpios = <&gpio7 1 0>;
  35                                 vmmc-supply = <&reg_3p3v>;
  36                                 status = "okay";
  37                         };
  38
  39                         usdhc@0219c000 { /* uSDHC4 */
  40                                 cd-gpios = <&gpio2 6 0>;
  41                                 wp-gpios = <&gpio2 7 0>;
  42                                 vmmc-supply = <&reg_3p3v>;
  43                                 status = "okay";
  44                         };
  45
  46                         uart2: serial@021e8000 {
  47                                 status = "okay";
  48                         };
  49
  50                         i2c@021a0000 { /* I2C1 */
  51                                 status = "okay";
  52                                 clock-frequency = <100000>;
  53
  54                                 codec: sgtl5000@0a {
  55                                         compatible = "fsl,sgtl5000";
  56                                         reg = <0x0a>;
  57                                         VDDA-supply = <&reg_2p5v>;
  58                                         VDDIO-supply = <&reg_3p3v>;
  59                                 };
  60                         };
  61                 };
  62         };
  63
  64         regulators {
  65                 compatible = "simple-bus";
  66
  67                 reg_2p5v: 2p5v {
  68                         compatible = "regulator-fixed";
  69                         regulator-name = "2P5V";
  70                         regulator-min-microvolt = <2500000>;
  71                         regulator-max-microvolt = <2500000>;
  72                         regulator-always-on;
  73                 };
  74
  75                 reg_3p3v: 3p3v {
  76                         compatible = "regulator-fixed";
  77                         regulator-name = "3P3V";
  78                         regulator-min-microvolt = <3300000>;
  79                         regulator-max-microvolt = <3300000>;
  80                         regulator-always-on;
  81                 };
  82         };
  83 };