3 * Copyright 2013 Freescale Semiconductor, Inc.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include "imx6q-pinfunc.h"
13 #include "imx6qdl.dtsi"
25 compatible = "arm,cortex-a9";
28 next-level-cache = <&L2>;
37 fsl,soc-operating-points = <
38 /* ARM kHz SOC-PU uV */
45 clock-latency = <61036>; /* two CLK32 periods */
46 clocks = <&clks 104>, <&clks 6>, <&clks 16>,
47 <&clks 17>, <&clks 170>;
48 clock-names = "arm", "pll2_pfd2_396m", "step",
49 "pll1_sw", "pll1_sys";
50 arm-supply = <®_arm>;
51 pu-supply = <®_pu>;
52 soc-supply = <®_soc>;
56 compatible = "arm,cortex-a9";
59 next-level-cache = <&L2>;
63 compatible = "arm,cortex-a9";
66 next-level-cache = <&L2>;
70 compatible = "arm,cortex-a9";
73 next-level-cache = <&L2>;
78 ocram: sram@00900000 {
79 compatible = "mmio-sram";
80 reg = <0x00900000 0x40000>;
84 aips-bus@02000000 { /* AIPS1 */
86 ecspi5: ecspi@02018000 {
89 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
90 reg = <0x02018000 0x4000>;
91 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
92 clocks = <&clks 116>, <&clks 116>;
93 clock-names = "ipg", "per";
98 iomuxc: iomuxc@020e0000 {
99 compatible = "fsl,imx6q-iomuxc";
102 pinctrl_ipu2_1: ipu2grp-1 {
104 MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x10
105 MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0x10
106 MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0x10
107 MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0x10
108 MX6QDL_PAD_DI0_PIN4__IPU2_DI0_PIN04 0x80000000
109 MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0x10
110 MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0x10
111 MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0x10
112 MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0x10
113 MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0x10
114 MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0x10
115 MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0x10
116 MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0x10
117 MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0x10
118 MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0x10
119 MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0x10
120 MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0x10
121 MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0x10
122 MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0x10
123 MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0x10
124 MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0x10
125 MX6QDL_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 0x10
126 MX6QDL_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 0x10
127 MX6QDL_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 0x10
128 MX6QDL_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 0x10
129 MX6QDL_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 0x10
130 MX6QDL_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 0x10
131 MX6QDL_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 0x10
132 MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 0x10
139 sata: sata@02200000 {
140 compatible = "fsl,imx6q-ahci";
141 reg = <0x02200000 0x4000>;
142 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
143 clocks = <&clks 154>, <&clks 187>, <&clks 105>;
144 clock-names = "sata", "sata_ref", "ahb";
149 #address-cells = <1>;
151 compatible = "fsl,imx6q-ipu";
152 reg = <0x02800000 0x400000>;
153 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
154 <0 7 IRQ_TYPE_LEVEL_HIGH>;
155 clocks = <&clks 133>, <&clks 134>, <&clks 137>;
156 clock-names = "bus", "di0", "di1";
160 #address-cells = <1>;
164 ipu2_di0_disp0: endpoint@0 {
167 ipu2_di0_hdmi: endpoint@1 {
168 remote-endpoint = <&hdmi_mux_2>;
171 ipu2_di0_mipi: endpoint@2 {
174 ipu2_di0_lvds0: endpoint@3 {
175 remote-endpoint = <&lvds0_mux_2>;
178 ipu2_di0_lvds1: endpoint@4 {
179 remote-endpoint = <&lvds1_mux_2>;
184 #address-cells = <1>;
188 ipu2_di1_hdmi: endpoint@1 {
189 remote-endpoint = <&hdmi_mux_3>;
192 ipu2_di1_mipi: endpoint@2 {
195 ipu2_di1_lvds0: endpoint@3 {
196 remote-endpoint = <&lvds0_mux_3>;
199 ipu2_di1_lvds1: endpoint@4 {
200 remote-endpoint = <&lvds1_mux_3>;
207 compatible = "fsl,imx-display-subsystem";
208 ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;
213 compatible = "fsl,imx6q-hdmi";
218 hdmi_mux_2: endpoint {
219 remote-endpoint = <&ipu2_di0_hdmi>;
226 hdmi_mux_3: endpoint {
227 remote-endpoint = <&ipu2_di1_hdmi>;
233 clocks = <&clks 33>, <&clks 34>,
234 <&clks 39>, <&clks 40>, <&clks 41>, <&clks 42>,
235 <&clks 135>, <&clks 136>;
236 clock-names = "di0_pll", "di1_pll",
237 "di0_sel", "di1_sel", "di2_sel", "di3_sel",
244 lvds0_mux_2: endpoint {
245 remote-endpoint = <&ipu2_di0_lvds0>;
252 lvds0_mux_3: endpoint {
253 remote-endpoint = <&ipu2_di1_lvds0>;
262 lvds1_mux_2: endpoint {
263 remote-endpoint = <&ipu2_di0_lvds1>;
270 lvds1_mux_3: endpoint {
271 remote-endpoint = <&ipu2_di1_lvds1>;
281 mipi_mux_2: endpoint {
282 remote-endpoint = <&ipu2_di0_mipi>;
289 mipi_mux_3: endpoint {
290 remote-endpoint = <&ipu2_di1_mipi>;