2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include <dt-bindings/clock/imx6qdl-clock.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include "skeleton.dtsi"
50 intc: interrupt-controller@00a01000 {
51 compatible = "arm,cortex-a9-gic";
52 #interrupt-cells = <3>;
54 reg = <0x00a01000 0x1000>,
63 compatible = "fsl,imx-ckil", "fixed-clock";
65 clock-frequency = <32768>;
69 compatible = "fsl,imx-ckih1", "fixed-clock";
71 clock-frequency = <0>;
75 compatible = "fsl,imx-osc", "fixed-clock";
77 clock-frequency = <24000000>;
84 compatible = "simple-bus";
85 interrupt-parent = <&intc>;
88 dma_apbh: dma-apbh@00110000 {
89 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
90 reg = <0x00110000 0x2000>;
91 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
92 <0 13 IRQ_TYPE_LEVEL_HIGH>,
93 <0 13 IRQ_TYPE_LEVEL_HIGH>,
94 <0 13 IRQ_TYPE_LEVEL_HIGH>;
95 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
98 clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
101 gpmi: gpmi-nand@00112000 {
102 compatible = "fsl,imx6q-gpmi-nand";
103 #address-cells = <1>;
105 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
106 reg-names = "gpmi-nand", "bch";
107 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
108 interrupt-names = "bch";
109 clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
110 <&clks IMX6QDL_CLK_GPMI_APB>,
111 <&clks IMX6QDL_CLK_GPMI_BCH>,
112 <&clks IMX6QDL_CLK_GPMI_BCH_APB>,
113 <&clks IMX6QDL_CLK_PER1_BCH>;
114 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
115 "gpmi_bch_apb", "per1_bch";
116 dmas = <&dma_apbh 0>;
122 compatible = "arm,cortex-a9-twd-timer";
123 reg = <0x00a00600 0x20>;
124 interrupts = <1 13 0xf01>;
125 clocks = <&clks IMX6QDL_CLK_TWD>;
128 L2: l2-cache@00a02000 {
129 compatible = "arm,pl310-cache";
130 reg = <0x00a02000 0x1000>;
131 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
134 arm,tag-latency = <4 2 3>;
135 arm,data-latency = <4 2 3>;
138 pcie: pcie@0x01000000 {
139 compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
140 reg = <0x01ffc000 0x04000>,
141 <0x01f00000 0x80000>;
142 reg-names = "dbi", "config";
143 #address-cells = <3>;
146 ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */
147 0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */
148 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
150 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
151 interrupt-names = "msi";
152 #interrupt-cells = <1>;
153 interrupt-map-mask = <0 0 0 0x7>;
154 interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
155 <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
156 <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
157 <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
158 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
159 <&clks IMX6QDL_CLK_LVDS1_GATE>,
160 <&clks IMX6QDL_CLK_PCIE_REF_125M>;
161 clock-names = "pcie", "pcie_bus", "pcie_phy";
166 compatible = "arm,cortex-a9-pmu";
167 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
170 aips-bus@02000000 { /* AIPS1 */
171 compatible = "fsl,aips-bus", "simple-bus";
172 #address-cells = <1>;
174 reg = <0x02000000 0x100000>;
178 compatible = "fsl,spba-bus", "simple-bus";
179 #address-cells = <1>;
181 reg = <0x02000000 0x40000>;
184 spdif: spdif@02004000 {
185 compatible = "fsl,imx35-spdif";
186 reg = <0x02004000 0x4000>;
187 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
188 dmas = <&sdma 14 18 0>,
190 dma-names = "rx", "tx";
191 clocks = <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_OSC>,
192 <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_DUMMY>,
193 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_DUMMY>,
194 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_DUMMY>,
195 <&clks IMX6QDL_CLK_DUMMY>;
196 clock-names = "core", "rxtx0",
204 ecspi1: ecspi@02008000 {
205 #address-cells = <1>;
207 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
208 reg = <0x02008000 0x4000>;
209 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
210 clocks = <&clks IMX6QDL_CLK_ECSPI1>,
211 <&clks IMX6QDL_CLK_ECSPI1>;
212 clock-names = "ipg", "per";
213 dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
214 dma-names = "rx", "tx";
218 ecspi2: ecspi@0200c000 {
219 #address-cells = <1>;
221 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
222 reg = <0x0200c000 0x4000>;
223 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
224 clocks = <&clks IMX6QDL_CLK_ECSPI2>,
225 <&clks IMX6QDL_CLK_ECSPI2>;
226 clock-names = "ipg", "per";
227 dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
228 dma-names = "rx", "tx";
232 ecspi3: ecspi@02010000 {
233 #address-cells = <1>;
235 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
236 reg = <0x02010000 0x4000>;
237 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
238 clocks = <&clks IMX6QDL_CLK_ECSPI3>,
239 <&clks IMX6QDL_CLK_ECSPI3>;
240 clock-names = "ipg", "per";
241 dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
242 dma-names = "rx", "tx";
246 ecspi4: ecspi@02014000 {
247 #address-cells = <1>;
249 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
250 reg = <0x02014000 0x4000>;
251 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
252 clocks = <&clks IMX6QDL_CLK_ECSPI4>,
253 <&clks IMX6QDL_CLK_ECSPI4>;
254 clock-names = "ipg", "per";
255 dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
256 dma-names = "rx", "tx";
260 uart1: serial@02020000 {
261 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
262 reg = <0x02020000 0x4000>;
263 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
264 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
265 <&clks IMX6QDL_CLK_UART_SERIAL>;
266 clock-names = "ipg", "per";
267 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
268 dma-names = "rx", "tx";
272 esai: esai@02024000 {
273 reg = <0x02024000 0x4000>;
274 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
278 #sound-dai-cells = <0>;
279 compatible = "fsl,imx6q-ssi",
281 reg = <0x02028000 0x4000>;
282 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
283 clocks = <&clks IMX6QDL_CLK_SSI1_IPG>,
284 <&clks IMX6QDL_CLK_SSI1>;
285 clock-names = "ipg", "baud";
286 dmas = <&sdma 37 1 0>,
288 dma-names = "rx", "tx";
289 fsl,fifo-depth = <15>;
294 #sound-dai-cells = <0>;
295 compatible = "fsl,imx6q-ssi",
297 reg = <0x0202c000 0x4000>;
298 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
299 clocks = <&clks IMX6QDL_CLK_SSI2_IPG>,
300 <&clks IMX6QDL_CLK_SSI2>;
301 clock-names = "ipg", "baud";
302 dmas = <&sdma 41 1 0>,
304 dma-names = "rx", "tx";
305 fsl,fifo-depth = <15>;
310 #sound-dai-cells = <0>;
311 compatible = "fsl,imx6q-ssi",
313 reg = <0x02030000 0x4000>;
314 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
315 clocks = <&clks IMX6QDL_CLK_SSI3_IPG>,
316 <&clks IMX6QDL_CLK_SSI3>;
317 clock-names = "ipg", "baud";
318 dmas = <&sdma 45 1 0>,
320 dma-names = "rx", "tx";
321 fsl,fifo-depth = <15>;
325 asrc: asrc@02034000 {
326 reg = <0x02034000 0x4000>;
327 interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
331 reg = <0x0203c000 0x4000>;
336 reg = <0x02040000 0x3c000>;
337 interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>,
338 <0 12 IRQ_TYPE_LEVEL_HIGH>;
341 aipstz@0207c000 { /* AIPSTZ1 */
342 reg = <0x0207c000 0x4000>;
347 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
348 reg = <0x02080000 0x4000>;
349 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
350 clocks = <&clks IMX6QDL_CLK_IPG>,
351 <&clks IMX6QDL_CLK_PWM1>;
352 clock-names = "ipg", "per";
357 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
358 reg = <0x02084000 0x4000>;
359 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
360 clocks = <&clks IMX6QDL_CLK_IPG>,
361 <&clks IMX6QDL_CLK_PWM2>;
362 clock-names = "ipg", "per";
367 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
368 reg = <0x02088000 0x4000>;
369 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
370 clocks = <&clks IMX6QDL_CLK_IPG>,
371 <&clks IMX6QDL_CLK_PWM3>;
372 clock-names = "ipg", "per";
377 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
378 reg = <0x0208c000 0x4000>;
379 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
380 clocks = <&clks IMX6QDL_CLK_IPG>,
381 <&clks IMX6QDL_CLK_PWM4>;
382 clock-names = "ipg", "per";
385 can1: flexcan@02090000 {
386 compatible = "fsl,imx6q-flexcan";
387 reg = <0x02090000 0x4000>;
388 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
389 clocks = <&clks IMX6QDL_CLK_CAN1_IPG>,
390 <&clks IMX6QDL_CLK_CAN1_SERIAL>;
391 clock-names = "ipg", "per";
395 can2: flexcan@02094000 {
396 compatible = "fsl,imx6q-flexcan";
397 reg = <0x02094000 0x4000>;
398 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
399 clocks = <&clks IMX6QDL_CLK_CAN2_IPG>,
400 <&clks IMX6QDL_CLK_CAN2_SERIAL>;
401 clock-names = "ipg", "per";
406 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
407 reg = <0x02098000 0x4000>;
408 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
409 clocks = <&clks IMX6QDL_CLK_GPT_IPG>,
410 <&clks IMX6QDL_CLK_GPT_IPG_PER>,
411 <&clks IMX6QDL_CLK_GPT_3M>;
412 clock-names = "ipg", "per", "osc_per";
415 gpio1: gpio@0209c000 {
416 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
417 reg = <0x0209c000 0x4000>;
418 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
419 <0 67 IRQ_TYPE_LEVEL_HIGH>;
422 interrupt-controller;
423 #interrupt-cells = <2>;
426 gpio2: gpio@020a0000 {
427 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
428 reg = <0x020a0000 0x4000>;
429 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
430 <0 69 IRQ_TYPE_LEVEL_HIGH>;
433 interrupt-controller;
434 #interrupt-cells = <2>;
437 gpio3: gpio@020a4000 {
438 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
439 reg = <0x020a4000 0x4000>;
440 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
441 <0 71 IRQ_TYPE_LEVEL_HIGH>;
444 interrupt-controller;
445 #interrupt-cells = <2>;
448 gpio4: gpio@020a8000 {
449 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
450 reg = <0x020a8000 0x4000>;
451 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
452 <0 73 IRQ_TYPE_LEVEL_HIGH>;
455 interrupt-controller;
456 #interrupt-cells = <2>;
459 gpio5: gpio@020ac000 {
460 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
461 reg = <0x020ac000 0x4000>;
462 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
463 <0 75 IRQ_TYPE_LEVEL_HIGH>;
466 interrupt-controller;
467 #interrupt-cells = <2>;
470 gpio6: gpio@020b0000 {
471 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
472 reg = <0x020b0000 0x4000>;
473 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
474 <0 77 IRQ_TYPE_LEVEL_HIGH>;
477 interrupt-controller;
478 #interrupt-cells = <2>;
481 gpio7: gpio@020b4000 {
482 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
483 reg = <0x020b4000 0x4000>;
484 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
485 <0 79 IRQ_TYPE_LEVEL_HIGH>;
488 interrupt-controller;
489 #interrupt-cells = <2>;
493 compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
494 reg = <0x020b8000 0x4000>;
495 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
496 clocks = <&clks IMX6QDL_CLK_IPG>;
500 wdog1: wdog@020bc000 {
501 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
502 reg = <0x020bc000 0x4000>;
503 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
504 clocks = <&clks IMX6QDL_CLK_DUMMY>;
507 wdog2: wdog@020c0000 {
508 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
509 reg = <0x020c0000 0x4000>;
510 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
511 clocks = <&clks IMX6QDL_CLK_DUMMY>;
516 compatible = "fsl,imx6q-ccm";
517 reg = <0x020c4000 0x4000>;
518 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
519 <0 88 IRQ_TYPE_LEVEL_HIGH>;
523 anatop: anatop@020c8000 {
524 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
525 reg = <0x020c8000 0x1000>;
526 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
527 <0 54 IRQ_TYPE_LEVEL_HIGH>,
528 <0 127 IRQ_TYPE_LEVEL_HIGH>;
531 compatible = "fsl,anatop-regulator";
532 regulator-name = "vdd1p1";
533 regulator-min-microvolt = <800000>;
534 regulator-max-microvolt = <1375000>;
536 anatop-reg-offset = <0x110>;
537 anatop-vol-bit-shift = <8>;
538 anatop-vol-bit-width = <5>;
539 anatop-min-bit-val = <4>;
540 anatop-min-voltage = <800000>;
541 anatop-max-voltage = <1375000>;
545 compatible = "fsl,anatop-regulator";
546 regulator-name = "vdd3p0";
547 regulator-min-microvolt = <2800000>;
548 regulator-max-microvolt = <3150000>;
550 anatop-reg-offset = <0x120>;
551 anatop-vol-bit-shift = <8>;
552 anatop-vol-bit-width = <5>;
553 anatop-min-bit-val = <0>;
554 anatop-min-voltage = <2625000>;
555 anatop-max-voltage = <3400000>;
559 compatible = "fsl,anatop-regulator";
560 regulator-name = "vdd2p5";
561 regulator-min-microvolt = <2000000>;
562 regulator-max-microvolt = <2750000>;
564 anatop-reg-offset = <0x130>;
565 anatop-vol-bit-shift = <8>;
566 anatop-vol-bit-width = <5>;
567 anatop-min-bit-val = <0>;
568 anatop-min-voltage = <2000000>;
569 anatop-max-voltage = <2750000>;
572 reg_arm: regulator-vddcore@140 {
573 compatible = "fsl,anatop-regulator";
574 regulator-name = "vddarm";
575 regulator-min-microvolt = <725000>;
576 regulator-max-microvolt = <1450000>;
578 anatop-reg-offset = <0x140>;
579 anatop-vol-bit-shift = <0>;
580 anatop-vol-bit-width = <5>;
581 anatop-delay-reg-offset = <0x170>;
582 anatop-delay-bit-shift = <24>;
583 anatop-delay-bit-width = <2>;
584 anatop-min-bit-val = <1>;
585 anatop-min-voltage = <725000>;
586 anatop-max-voltage = <1450000>;
589 reg_pu: regulator-vddpu@140 {
590 compatible = "fsl,anatop-regulator";
591 regulator-name = "vddpu";
592 regulator-min-microvolt = <725000>;
593 regulator-max-microvolt = <1450000>;
595 anatop-reg-offset = <0x140>;
596 anatop-vol-bit-shift = <9>;
597 anatop-vol-bit-width = <5>;
598 anatop-delay-reg-offset = <0x170>;
599 anatop-delay-bit-shift = <26>;
600 anatop-delay-bit-width = <2>;
601 anatop-min-bit-val = <1>;
602 anatop-min-voltage = <725000>;
603 anatop-max-voltage = <1450000>;
606 reg_soc: regulator-vddsoc@140 {
607 compatible = "fsl,anatop-regulator";
608 regulator-name = "vddsoc";
609 regulator-min-microvolt = <725000>;
610 regulator-max-microvolt = <1450000>;
612 anatop-reg-offset = <0x140>;
613 anatop-vol-bit-shift = <18>;
614 anatop-vol-bit-width = <5>;
615 anatop-delay-reg-offset = <0x170>;
616 anatop-delay-bit-shift = <28>;
617 anatop-delay-bit-width = <2>;
618 anatop-min-bit-val = <1>;
619 anatop-min-voltage = <725000>;
620 anatop-max-voltage = <1450000>;
625 compatible = "fsl,imx6q-tempmon";
626 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
627 fsl,tempmon = <&anatop>;
628 fsl,tempmon-data = <&ocotp>;
629 clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
632 usbphy1: usbphy@020c9000 {
633 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
634 reg = <0x020c9000 0x1000>;
635 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
636 clocks = <&clks IMX6QDL_CLK_USBPHY1>;
637 fsl,anatop = <&anatop>;
640 usbphy2: usbphy@020ca000 {
641 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
642 reg = <0x020ca000 0x1000>;
643 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
644 clocks = <&clks IMX6QDL_CLK_USBPHY2>;
645 fsl,anatop = <&anatop>;
649 compatible = "fsl,sec-v4.0-mon", "simple-bus";
650 #address-cells = <1>;
652 ranges = <0 0x020cc000 0x4000>;
655 compatible = "fsl,sec-v4.0-mon-rtc-lp";
657 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
658 <0 20 IRQ_TYPE_LEVEL_HIGH>;
662 epit1: epit@020d0000 { /* EPIT1 */
663 reg = <0x020d0000 0x4000>;
664 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
667 epit2: epit@020d4000 { /* EPIT2 */
668 reg = <0x020d4000 0x4000>;
669 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
673 compatible = "fsl,imx6q-src", "fsl,imx51-src";
674 reg = <0x020d8000 0x4000>;
675 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
676 <0 96 IRQ_TYPE_LEVEL_HIGH>;
681 compatible = "fsl,imx6q-gpc";
682 reg = <0x020dc000 0x4000>;
683 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
684 <0 90 IRQ_TYPE_LEVEL_HIGH>;
687 gpr: iomuxc-gpr@020e0000 {
688 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
689 reg = <0x020e0000 0x38>;
692 iomuxc: iomuxc@020e0000 {
693 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
694 reg = <0x020e0000 0x4000>;
698 #address-cells = <1>;
700 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
705 #address-cells = <1>;
713 lvds0_mux_0: endpoint {
714 remote-endpoint = <&ipu1_di0_lvds0>;
721 lvds0_mux_1: endpoint {
722 remote-endpoint = <&ipu1_di1_lvds0>;
728 #address-cells = <1>;
736 lvds1_mux_0: endpoint {
737 remote-endpoint = <&ipu1_di0_lvds1>;
744 lvds1_mux_1: endpoint {
745 remote-endpoint = <&ipu1_di1_lvds1>;
752 #address-cells = <1>;
754 reg = <0x00120000 0x9000>;
755 interrupts = <0 115 0x04>;
757 clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
758 <&clks IMX6QDL_CLK_HDMI_ISFR>;
759 clock-names = "iahb", "isfr";
765 hdmi_mux_0: endpoint {
766 remote-endpoint = <&ipu1_di0_hdmi>;
773 hdmi_mux_1: endpoint {
774 remote-endpoint = <&ipu1_di1_hdmi>;
779 dcic1: dcic@020e4000 {
780 reg = <0x020e4000 0x4000>;
781 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
784 dcic2: dcic@020e8000 {
785 reg = <0x020e8000 0x4000>;
786 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
789 sdma: sdma@020ec000 {
790 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
791 reg = <0x020ec000 0x4000>;
792 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
793 clocks = <&clks IMX6QDL_CLK_SDMA>,
794 <&clks IMX6QDL_CLK_SDMA>;
795 clock-names = "ipg", "ahb";
797 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
801 aips-bus@02100000 { /* AIPS2 */
802 compatible = "fsl,aips-bus", "simple-bus";
803 #address-cells = <1>;
805 reg = <0x02100000 0x100000>;
809 reg = <0x02100000 0x40000>;
810 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>,
811 <0 106 IRQ_TYPE_LEVEL_HIGH>;
814 aipstz@0217c000 { /* AIPSTZ2 */
815 reg = <0x0217c000 0x4000>;
818 usbotg: usb@02184000 {
819 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
820 reg = <0x02184000 0x200>;
821 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
822 clocks = <&clks IMX6QDL_CLK_USBOH3>;
823 fsl,usbphy = <&usbphy1>;
824 fsl,usbmisc = <&usbmisc 0>;
828 usbh1: usb@02184200 {
829 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
830 reg = <0x02184200 0x200>;
831 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
832 clocks = <&clks IMX6QDL_CLK_USBOH3>;
833 fsl,usbphy = <&usbphy2>;
834 fsl,usbmisc = <&usbmisc 1>;
838 usbh2: usb@02184400 {
839 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
840 reg = <0x02184400 0x200>;
841 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
842 clocks = <&clks IMX6QDL_CLK_USBOH3>;
843 fsl,usbmisc = <&usbmisc 2>;
847 usbh3: usb@02184600 {
848 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
849 reg = <0x02184600 0x200>;
850 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
851 clocks = <&clks IMX6QDL_CLK_USBOH3>;
852 fsl,usbmisc = <&usbmisc 3>;
856 usbmisc: usbmisc@02184800 {
858 compatible = "fsl,imx6q-usbmisc";
859 reg = <0x02184800 0x200>;
860 clocks = <&clks IMX6QDL_CLK_USBOH3>;
863 fec: ethernet@02188000 {
864 compatible = "fsl,imx6q-fec";
865 reg = <0x02188000 0x4000>;
866 interrupts-extended =
867 <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
868 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
869 clocks = <&clks IMX6QDL_CLK_ENET>,
870 <&clks IMX6QDL_CLK_ENET>,
871 <&clks IMX6QDL_CLK_ENET_REF>;
872 clock-names = "ipg", "ahb", "ptp";
877 reg = <0x0218c000 0x4000>;
878 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
879 <0 117 IRQ_TYPE_LEVEL_HIGH>,
880 <0 126 IRQ_TYPE_LEVEL_HIGH>;
883 usdhc1: usdhc@02190000 {
884 compatible = "fsl,imx6q-usdhc";
885 reg = <0x02190000 0x4000>;
886 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
887 clocks = <&clks IMX6QDL_CLK_USDHC1>,
888 <&clks IMX6QDL_CLK_USDHC1>,
889 <&clks IMX6QDL_CLK_USDHC1>;
890 clock-names = "ipg", "ahb", "per";
895 usdhc2: usdhc@02194000 {
896 compatible = "fsl,imx6q-usdhc";
897 reg = <0x02194000 0x4000>;
898 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
899 clocks = <&clks IMX6QDL_CLK_USDHC2>,
900 <&clks IMX6QDL_CLK_USDHC2>,
901 <&clks IMX6QDL_CLK_USDHC2>;
902 clock-names = "ipg", "ahb", "per";
907 usdhc3: usdhc@02198000 {
908 compatible = "fsl,imx6q-usdhc";
909 reg = <0x02198000 0x4000>;
910 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
911 clocks = <&clks IMX6QDL_CLK_USDHC3>,
912 <&clks IMX6QDL_CLK_USDHC3>,
913 <&clks IMX6QDL_CLK_USDHC3>;
914 clock-names = "ipg", "ahb", "per";
919 usdhc4: usdhc@0219c000 {
920 compatible = "fsl,imx6q-usdhc";
921 reg = <0x0219c000 0x4000>;
922 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
923 clocks = <&clks IMX6QDL_CLK_USDHC4>,
924 <&clks IMX6QDL_CLK_USDHC4>,
925 <&clks IMX6QDL_CLK_USDHC4>;
926 clock-names = "ipg", "ahb", "per";
932 #address-cells = <1>;
934 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
935 reg = <0x021a0000 0x4000>;
936 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
937 clocks = <&clks IMX6QDL_CLK_I2C1>;
942 #address-cells = <1>;
944 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
945 reg = <0x021a4000 0x4000>;
946 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
947 clocks = <&clks IMX6QDL_CLK_I2C2>;
952 #address-cells = <1>;
954 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
955 reg = <0x021a8000 0x4000>;
956 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
957 clocks = <&clks IMX6QDL_CLK_I2C3>;
962 reg = <0x021ac000 0x4000>;
965 mmdc0: mmdc@021b0000 { /* MMDC0 */
966 compatible = "fsl,imx6q-mmdc";
967 reg = <0x021b0000 0x4000>;
970 mmdc1: mmdc@021b4000 { /* MMDC1 */
971 reg = <0x021b4000 0x4000>;
974 weim: weim@021b8000 {
975 compatible = "fsl,imx6q-weim";
976 reg = <0x021b8000 0x4000>;
977 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
978 clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
981 ocotp: ocotp@021bc000 {
982 compatible = "fsl,imx6q-ocotp", "syscon";
983 reg = <0x021bc000 0x4000>;
986 tzasc@021d0000 { /* TZASC1 */
987 reg = <0x021d0000 0x4000>;
988 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
991 tzasc@021d4000 { /* TZASC2 */
992 reg = <0x021d4000 0x4000>;
993 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
996 audmux: audmux@021d8000 {
997 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
998 reg = <0x021d8000 0x4000>;
1002 mipi_csi: mipi@021dc000 {
1003 reg = <0x021dc000 0x4000>;
1006 mipi_dsi: mipi@021e0000 {
1007 #address-cells = <1>;
1009 reg = <0x021e0000 0x4000>;
1010 status = "disabled";
1015 mipi_mux_0: endpoint {
1016 remote-endpoint = <&ipu1_di0_mipi>;
1023 mipi_mux_1: endpoint {
1024 remote-endpoint = <&ipu1_di1_mipi>;
1030 reg = <0x021e4000 0x4000>;
1031 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
1034 uart2: serial@021e8000 {
1035 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1036 reg = <0x021e8000 0x4000>;
1037 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
1038 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1039 <&clks IMX6QDL_CLK_UART_SERIAL>;
1040 clock-names = "ipg", "per";
1041 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1042 dma-names = "rx", "tx";
1043 status = "disabled";
1046 uart3: serial@021ec000 {
1047 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1048 reg = <0x021ec000 0x4000>;
1049 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
1050 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1051 <&clks IMX6QDL_CLK_UART_SERIAL>;
1052 clock-names = "ipg", "per";
1053 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1054 dma-names = "rx", "tx";
1055 status = "disabled";
1058 uart4: serial@021f0000 {
1059 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1060 reg = <0x021f0000 0x4000>;
1061 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
1062 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1063 <&clks IMX6QDL_CLK_UART_SERIAL>;
1064 clock-names = "ipg", "per";
1065 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1066 dma-names = "rx", "tx";
1067 status = "disabled";
1070 uart5: serial@021f4000 {
1071 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1072 reg = <0x021f4000 0x4000>;
1073 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
1074 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1075 <&clks IMX6QDL_CLK_UART_SERIAL>;
1076 clock-names = "ipg", "per";
1077 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1078 dma-names = "rx", "tx";
1079 status = "disabled";
1083 ipu1: ipu@02400000 {
1084 #address-cells = <1>;
1086 compatible = "fsl,imx6q-ipu";
1087 reg = <0x02400000 0x400000>;
1088 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
1089 <0 5 IRQ_TYPE_LEVEL_HIGH>;
1090 clocks = <&clks IMX6QDL_CLK_IPU1>,
1091 <&clks IMX6QDL_CLK_IPU1_DI0>,
1092 <&clks IMX6QDL_CLK_IPU1_DI1>;
1093 clock-names = "bus", "di0", "di1";
1105 #address-cells = <1>;
1109 ipu1_di0_disp0: endpoint@0 {
1112 ipu1_di0_hdmi: endpoint@1 {
1113 remote-endpoint = <&hdmi_mux_0>;
1116 ipu1_di0_mipi: endpoint@2 {
1117 remote-endpoint = <&mipi_mux_0>;
1120 ipu1_di0_lvds0: endpoint@3 {
1121 remote-endpoint = <&lvds0_mux_0>;
1124 ipu1_di0_lvds1: endpoint@4 {
1125 remote-endpoint = <&lvds1_mux_0>;
1130 #address-cells = <1>;
1134 ipu1_di0_disp1: endpoint@0 {
1137 ipu1_di1_hdmi: endpoint@1 {
1138 remote-endpoint = <&hdmi_mux_1>;
1141 ipu1_di1_mipi: endpoint@2 {
1142 remote-endpoint = <&mipi_mux_1>;
1145 ipu1_di1_lvds0: endpoint@3 {
1146 remote-endpoint = <&lvds0_mux_1>;
1149 ipu1_di1_lvds1: endpoint@4 {
1150 remote-endpoint = <&lvds1_mux_1>;