arch/arm/boot/dts/imx6qdl.dtsi

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include "skeleton.dtsi"
  14
  15 / {
  16         aliases {
  17                 gpio0 = &gpio1;
  18                 gpio1 = &gpio2;
  19                 gpio2 = &gpio3;
  20                 gpio3 = &gpio4;
  21                 gpio4 = &gpio5;
  22                 gpio5 = &gpio6;
  23                 gpio6 = &gpio7;
  24                 i2c0 = &i2c1;
  25                 i2c1 = &i2c2;
  26                 i2c2 = &i2c3;
  27                 serial0 = &uart1;
  28                 serial1 = &uart2;
  29                 serial2 = &uart3;
  30                 serial3 = &uart4;
  31                 serial4 = &uart5;
  32                 spi0 = &ecspi1;
  33                 spi1 = &ecspi2;
  34                 spi2 = &ecspi3;
  35                 spi3 = &ecspi4;
  36         };
  37
  38         intc: interrupt-controller@00a01000 {
  39                 compatible = "arm,cortex-a9-gic";
  40                 #interrupt-cells = <3>;
  41                 #address-cells = <1>;
  42                 #size-cells = <1>;
  43                 interrupt-controller;
  44                 reg = <0x00a01000 0x1000>,
  45                       <0x00a00100 0x100>;
  46         };
  47
  48         clocks {
  49                 #address-cells = <1>;
  50                 #size-cells = <0>;
  51
  52                 ckil {
  53                         compatible = "fsl,imx-ckil", "fixed-clock";
  54                         clock-frequency = <32768>;
  55                 };
  56
  57                 ckih1 {
  58                         compatible = "fsl,imx-ckih1", "fixed-clock";
  59                         clock-frequency = <0>;
  60                 };
  61
  62                 osc {
  63                         compatible = "fsl,imx-osc", "fixed-clock";
  64                         clock-frequency = <24000000>;
  65                 };
  66         };
  67
  68         soc {
  69                 #address-cells = <1>;
  70                 #size-cells = <1>;
  71                 compatible = "simple-bus";
  72                 interrupt-parent = <&intc>;
  73                 ranges;
  74
  75                 dma_apbh: dma-apbh@00110000 {
  76                         compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
  77                         reg = <0x00110000 0x2000>;
  78                         interrupts = <0 13 0x04>, <0 13 0x04>, <0 13 0x04>, <0 13 0x04>;
  79                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
  80                         #dma-cells = <1>;
  81                         dma-channels = <4>;
  82                         clocks = <&clks 106>;
  83                 };
  84
  85                 gpmi: gpmi-nand@00112000 {
  86                         compatible = "fsl,imx6q-gpmi-nand";
  87                         #address-cells = <1>;
  88                         #size-cells = <1>;
  89                         reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
  90                         reg-names = "gpmi-nand", "bch";
  91                         interrupts = <0 13 0x04>, <0 15 0x04>;
  92                         interrupt-names = "gpmi-dma", "bch";
  93                         clocks = <&clks 152>, <&clks 153>, <&clks 151>,
  94                                  <&clks 150>, <&clks 149>;
  95                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
  96                                       "gpmi_bch_apb", "per1_bch";
  97                         dmas = <&dma_apbh 0>;
  98                         dma-names = "rx-tx";
  99                         fsl,gpmi-dma-channel = <0>;
 100                         status = "disabled";
 101                 };
 102
 103                 ocram: sram@00900000 {
 104                         compatible = "mmio-sram";
 105                         reg = <0x00900000 0x3f000>;
 106                         clocks = <&clks 142>;
 107                 };
 108
 109                 timer@00a00600 {
 110                         compatible = "arm,cortex-a9-twd-timer";
 111                         reg = <0x00a00600 0x20>;
 112                         interrupts = <1 13 0xf01>;
 113                         clocks = <&clks 15>;
 114                 };
 115
 116                 L2: l2-cache@00a02000 {
 117                         compatible = "arm,pl310-cache";
 118                         reg = <0x00a02000 0x1000>;
 119                         interrupts = <0 92 0x04>;
 120                         cache-unified;
 121                         cache-level = <2>;
 122                         arm,tag-latency = <4 2 3>;
 123                         arm,data-latency = <4 2 3>;
 124                 };
 125
 126                 pmu {
 127                         compatible = "arm,cortex-a9-pmu";
 128                         interrupts = <0 94 0x04>;
 129                 };
 130
 131                 aips-bus@02000000 { /* AIPS1 */
 132                         compatible = "fsl,aips-bus", "simple-bus";
 133                         #address-cells = <1>;
 134                         #size-cells = <1>;
 135                         reg = <0x02000000 0x100000>;
 136                         ranges;
 137
 138                         spba-bus@02000000 {
 139                                 compatible = "fsl,spba-bus", "simple-bus";
 140                                 #address-cells = <1>;
 141                                 #size-cells = <1>;
 142                                 reg = <0x02000000 0x40000>;
 143                                 ranges;
 144
 145                                 spdif: spdif@02004000 {
 146                                         reg = <0x02004000 0x4000>;
 147                                         interrupts = <0 52 0x04>;
 148                                 };
 149
 150                                 ecspi1: ecspi@02008000 {
 151                                         #address-cells = <1>;
 152                                         #size-cells = <0>;
 153                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 154                                         reg = <0x02008000 0x4000>;
 155                                         interrupts = <0 31 0x04>;
 156                                         clocks = <&clks 112>, <&clks 112>;
 157                                         clock-names = "ipg", "per";
 158                                         status = "disabled";
 159                                 };
 160
 161                                 ecspi2: ecspi@0200c000 {
 162                                         #address-cells = <1>;
 163                                         #size-cells = <0>;
 164                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 165                                         reg = <0x0200c000 0x4000>;
 166                                         interrupts = <0 32 0x04>;
 167                                         clocks = <&clks 113>, <&clks 113>;
 168                                         clock-names = "ipg", "per";
 169                                         status = "disabled";
 170                                 };
 171
 172                                 ecspi3: ecspi@02010000 {
 173                                         #address-cells = <1>;
 174                                         #size-cells = <0>;
 175                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 176                                         reg = <0x02010000 0x4000>;
 177                                         interrupts = <0 33 0x04>;
 178                                         clocks = <&clks 114>, <&clks 114>;
 179                                         clock-names = "ipg", "per";
 180                                         status = "disabled";
 181                                 };
 182
 183                                 ecspi4: ecspi@02014000 {
 184                                         #address-cells = <1>;
 185                                         #size-cells = <0>;
 186                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 187                                         reg = <0x02014000 0x4000>;
 188                                         interrupts = <0 34 0x04>;
 189                                         clocks = <&clks 115>, <&clks 115>;
 190                                         clock-names = "ipg", "per";
 191                                         status = "disabled";
 192                                 };
 193
 194                                 uart1: serial@02020000 {
 195                                         compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 196                                         reg = <0x02020000 0x4000>;
 197                                         interrupts = <0 26 0x04>;
 198                                         clocks = <&clks 160>, <&clks 161>;
 199                                         clock-names = "ipg", "per";
 200                                         dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
 201                                         dma-names = "rx", "tx";
 202                                         status = "disabled";
 203                                 };
 204
 205                                 esai: esai@02024000 {
 206                                         reg = <0x02024000 0x4000>;
 207                                         interrupts = <0 51 0x04>;
 208                                 };
 209
 210                                 ssi1: ssi@02028000 {
 211                                         compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
 212                                         reg = <0x02028000 0x4000>;
 213                                         interrupts = <0 46 0x04>;
 214                                         clocks = <&clks 178>;
 215                                         fsl,fifo-depth = <15>;
 216                                         fsl,ssi-dma-events = <38 37>;
 217                                         status = "disabled";
 218                                 };
 219
 220                                 ssi2: ssi@0202c000 {
 221                                         compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
 222                                         reg = <0x0202c000 0x4000>;
 223                                         interrupts = <0 47 0x04>;
 224                                         clocks = <&clks 179>;
 225                                         fsl,fifo-depth = <15>;
 226                                         fsl,ssi-dma-events = <42 41>;
 227                                         status = "disabled";
 228                                 };
 229
 230                                 ssi3: ssi@02030000 {
 231                                         compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
 232                                         reg = <0x02030000 0x4000>;
 233                                         interrupts = <0 48 0x04>;
 234                                         clocks = <&clks 180>;
 235                                         fsl,fifo-depth = <15>;
 236                                         fsl,ssi-dma-events = <46 45>;
 237                                         status = "disabled";
 238                                 };
 239
 240                                 asrc: asrc@02034000 {
 241                                         reg = <0x02034000 0x4000>;
 242                                         interrupts = <0 50 0x04>;
 243                                 };
 244
 245                                 spba@0203c000 {
 246                                         reg = <0x0203c000 0x4000>;
 247                                 };
 248                         };
 249
 250                         vpu: vpu@02040000 {
 251                                 reg = <0x02040000 0x3c000>;
 252                                 interrupts = <0 3 0x04 0 12 0x04>;
 253                         };
 254
 255                         aipstz@0207c000 { /* AIPSTZ1 */
 256                                 reg = <0x0207c000 0x4000>;
 257                         };
 258
 259                         pwm1: pwm@02080000 {
 260                                 #pwm-cells = <2>;
 261                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 262                                 reg = <0x02080000 0x4000>;
 263                                 interrupts = <0 83 0x04>;
 264                                 clocks = <&clks 62>, <&clks 145>;
 265                                 clock-names = "ipg", "per";
 266                         };
 267
 268                         pwm2: pwm@02084000 {
 269                                 #pwm-cells = <2>;
 270                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 271                                 reg = <0x02084000 0x4000>;
 272                                 interrupts = <0 84 0x04>;
 273                                 clocks = <&clks 62>, <&clks 146>;
 274                                 clock-names = "ipg", "per";
 275                         };
 276
 277                         pwm3: pwm@02088000 {
 278                                 #pwm-cells = <2>;
 279                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 280                                 reg = <0x02088000 0x4000>;
 281                                 interrupts = <0 85 0x04>;
 282                                 clocks = <&clks 62>, <&clks 147>;
 283                                 clock-names = "ipg", "per";
 284                         };
 285
 286                         pwm4: pwm@0208c000 {
 287                                 #pwm-cells = <2>;
 288                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 289                                 reg = <0x0208c000 0x4000>;
 290                                 interrupts = <0 86 0x04>;
 291                                 clocks = <&clks 62>, <&clks 148>;
 292                                 clock-names = "ipg", "per";
 293                         };
 294
 295                         can1: flexcan@02090000 {
 296                                 compatible = "fsl,imx6q-flexcan";
 297                                 reg = <0x02090000 0x4000>;
 298                                 interrupts = <0 110 0x04>;
 299                                 clocks = <&clks 108>, <&clks 109>;
 300                                 clock-names = "ipg", "per";
 301                         };
 302
 303                         can2: flexcan@02094000 {
 304                                 compatible = "fsl,imx6q-flexcan";
 305                                 reg = <0x02094000 0x4000>;
 306                                 interrupts = <0 111 0x04>;
 307                                 clocks = <&clks 110>, <&clks 111>;
 308                                 clock-names = "ipg", "per";
 309                         };
 310
 311                         gpt: gpt@02098000 {
 312                                 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
 313                                 reg = <0x02098000 0x4000>;
 314                                 interrupts = <0 55 0x04>;
 315                                 clocks = <&clks 119>, <&clks 120>;
 316                                 clock-names = "ipg", "per";
 317                         };
 318
 319                         gpio1: gpio@0209c000 {
 320                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 321                                 reg = <0x0209c000 0x4000>;
 322                                 interrupts = <0 66 0x04 0 67 0x04>;
 323                                 gpio-controller;
 324                                 #gpio-cells = <2>;
 325                                 interrupt-controller;
 326                                 #interrupt-cells = <2>;
 327                         };
 328
 329                         gpio2: gpio@020a0000 {
 330                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 331                                 reg = <0x020a0000 0x4000>;
 332                                 interrupts = <0 68 0x04 0 69 0x04>;
 333                                 gpio-controller;
 334                                 #gpio-cells = <2>;
 335                                 interrupt-controller;
 336                                 #interrupt-cells = <2>;
 337                         };
 338
 339                         gpio3: gpio@020a4000 {
 340                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 341                                 reg = <0x020a4000 0x4000>;
 342                                 interrupts = <0 70 0x04 0 71 0x04>;
 343                                 gpio-controller;
 344                                 #gpio-cells = <2>;
 345                                 interrupt-controller;
 346                                 #interrupt-cells = <2>;
 347                         };
 348
 349                         gpio4: gpio@020a8000 {
 350                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 351                                 reg = <0x020a8000 0x4000>;
 352                                 interrupts = <0 72 0x04 0 73 0x04>;
 353                                 gpio-controller;
 354                                 #gpio-cells = <2>;
 355                                 interrupt-controller;
 356                                 #interrupt-cells = <2>;
 357                         };
 358
 359                         gpio5: gpio@020ac000 {
 360                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 361                                 reg = <0x020ac000 0x4000>;
 362                                 interrupts = <0 74 0x04 0 75 0x04>;
 363                                 gpio-controller;
 364                                 #gpio-cells = <2>;
 365                                 interrupt-controller;
 366                                 #interrupt-cells = <2>;
 367                         };
 368
 369                         gpio6: gpio@020b0000 {
 370                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 371                                 reg = <0x020b0000 0x4000>;
 372                                 interrupts = <0 76 0x04 0 77 0x04>;
 373                                 gpio-controller;
 374                                 #gpio-cells = <2>;
 375                                 interrupt-controller;
 376                                 #interrupt-cells = <2>;
 377                         };
 378
 379                         gpio7: gpio@020b4000 {
 380                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 381                                 reg = <0x020b4000 0x4000>;
 382                                 interrupts = <0 78 0x04 0 79 0x04>;
 383                                 gpio-controller;
 384                                 #gpio-cells = <2>;
 385                                 interrupt-controller;
 386                                 #interrupt-cells = <2>;
 387                         };
 388
 389                         kpp: kpp@020b8000 {
 390                                 reg = <0x020b8000 0x4000>;
 391                                 interrupts = <0 82 0x04>;
 392                         };
 393
 394                         wdog1: wdog@020bc000 {
 395                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 396                                 reg = <0x020bc000 0x4000>;
 397                                 interrupts = <0 80 0x04>;
 398                                 clocks = <&clks 0>;
 399                         };
 400
 401                         wdog2: wdog@020c0000 {
 402                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 403                                 reg = <0x020c0000 0x4000>;
 404                                 interrupts = <0 81 0x04>;
 405                                 clocks = <&clks 0>;
 406                                 status = "disabled";
 407                         };
 408
 409                         clks: ccm@020c4000 {
 410                                 compatible = "fsl,imx6q-ccm";
 411                                 reg = <0x020c4000 0x4000>;
 412                                 interrupts = <0 87 0x04 0 88 0x04>;
 413                                 #clock-cells = <1>;
 414                         };
 415
 416                         anatop: anatop@020c8000 {
 417                                 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
 418                                 reg = <0x020c8000 0x1000>;
 419                                 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
 420
 421                                 regulator-1p1@110 {
 422                                         compatible = "fsl,anatop-regulator";
 423                                         regulator-name = "vdd1p1";
 424                                         regulator-min-microvolt = <800000>;
 425                                         regulator-max-microvolt = <1375000>;
 426                                         regulator-always-on;
 427                                         anatop-reg-offset = <0x110>;
 428                                         anatop-vol-bit-shift = <8>;
 429                                         anatop-vol-bit-width = <5>;
 430                                         anatop-min-bit-val = <4>;
 431                                         anatop-min-voltage = <800000>;
 432                                         anatop-max-voltage = <1375000>;
 433                                 };
 434
 435                                 regulator-3p0@120 {
 436                                         compatible = "fsl,anatop-regulator";
 437                                         regulator-name = "vdd3p0";
 438                                         regulator-min-microvolt = <2800000>;
 439                                         regulator-max-microvolt = <3150000>;
 440                                         regulator-always-on;
 441                                         anatop-reg-offset = <0x120>;
 442                                         anatop-vol-bit-shift = <8>;
 443                                         anatop-vol-bit-width = <5>;
 444                                         anatop-min-bit-val = <0>;
 445                                         anatop-min-voltage = <2625000>;
 446                                         anatop-max-voltage = <3400000>;
 447                                 };
 448
 449                                 regulator-2p5@130 {
 450                                         compatible = "fsl,anatop-regulator";
 451                                         regulator-name = "vdd2p5";
 452                                         regulator-min-microvolt = <2000000>;
 453                                         regulator-max-microvolt = <2750000>;
 454                                         regulator-always-on;
 455                                         anatop-reg-offset = <0x130>;
 456                                         anatop-vol-bit-shift = <8>;
 457                                         anatop-vol-bit-width = <5>;
 458                                         anatop-min-bit-val = <0>;
 459                                         anatop-min-voltage = <2000000>;
 460                                         anatop-max-voltage = <2750000>;
 461                                 };
 462
 463                                 reg_arm: regulator-vddcore@140 {
 464                                         compatible = "fsl,anatop-regulator";
 465                                         regulator-name = "cpu";
 466                                         regulator-min-microvolt = <725000>;
 467                                         regulator-max-microvolt = <1450000>;
 468                                         regulator-always-on;
 469                                         anatop-reg-offset = <0x140>;
 470                                         anatop-vol-bit-shift = <0>;
 471                                         anatop-vol-bit-width = <5>;
 472                                         anatop-delay-reg-offset = <0x170>;
 473                                         anatop-delay-bit-shift = <24>;
 474                                         anatop-delay-bit-width = <2>;
 475                                         anatop-min-bit-val = <1>;
 476                                         anatop-min-voltage = <725000>;
 477                                         anatop-max-voltage = <1450000>;
 478                                 };
 479
 480                                 reg_pu: regulator-vddpu@140 {
 481                                         compatible = "fsl,anatop-regulator";
 482                                         regulator-name = "vddpu";
 483                                         regulator-min-microvolt = <725000>;
 484                                         regulator-max-microvolt = <1450000>;
 485                                         regulator-always-on;
 486                                         anatop-reg-offset = <0x140>;
 487                                         anatop-vol-bit-shift = <9>;
 488                                         anatop-vol-bit-width = <5>;
 489                                         anatop-delay-reg-offset = <0x170>;
 490                                         anatop-delay-bit-shift = <26>;
 491                                         anatop-delay-bit-width = <2>;
 492                                         anatop-min-bit-val = <1>;
 493                                         anatop-min-voltage = <725000>;
 494                                         anatop-max-voltage = <1450000>;
 495                                 };
 496
 497                                 reg_soc: regulator-vddsoc@140 {
 498                                         compatible = "fsl,anatop-regulator";
 499                                         regulator-name = "vddsoc";
 500                                         regulator-min-microvolt = <725000>;
 501                                         regulator-max-microvolt = <1450000>;
 502                                         regulator-always-on;
 503                                         anatop-reg-offset = <0x140>;
 504                                         anatop-vol-bit-shift = <18>;
 505                                         anatop-vol-bit-width = <5>;
 506                                         anatop-delay-reg-offset = <0x170>;
 507                                         anatop-delay-bit-shift = <28>;
 508                                         anatop-delay-bit-width = <2>;
 509                                         anatop-min-bit-val = <1>;
 510                                         anatop-min-voltage = <725000>;
 511                                         anatop-max-voltage = <1450000>;
 512                                 };
 513                         };
 514
 515                         usbphy1: usbphy@020c9000 {
 516                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 517                                 reg = <0x020c9000 0x1000>;
 518                                 interrupts = <0 44 0x04>;
 519                                 clocks = <&clks 182>;
 520                         };
 521
 522                         usbphy2: usbphy@020ca000 {
 523                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 524                                 reg = <0x020ca000 0x1000>;
 525                                 interrupts = <0 45 0x04>;
 526                                 clocks = <&clks 183>;
 527                         };
 528
 529                         snvs@020cc000 {
 530                                 compatible = "fsl,sec-v4.0-mon", "simple-bus";
 531                                 #address-cells = <1>;
 532                                 #size-cells = <1>;
 533                                 ranges = <0 0x020cc000 0x4000>;
 534
 535                                 snvs-rtc-lp@34 {
 536                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 537                                         reg = <0x34 0x58>;
 538                                         interrupts = <0 19 0x04 0 20 0x04>;
 539                                 };
 540                         };
 541
 542                         epit1: epit@020d0000 { /* EPIT1 */
 543                                 reg = <0x020d0000 0x4000>;
 544                                 interrupts = <0 56 0x04>;
 545                         };
 546
 547                         epit2: epit@020d4000 { /* EPIT2 */
 548                                 reg = <0x020d4000 0x4000>;
 549                                 interrupts = <0 57 0x04>;
 550                         };
 551
 552                         src: src@020d8000 {
 553                                 compatible = "fsl,imx6q-src", "fsl,imx51-src";
 554                                 reg = <0x020d8000 0x4000>;
 555                                 interrupts = <0 91 0x04 0 96 0x04>;
 556                                 #reset-cells = <1>;
 557                         };
 558
 559                         gpc: gpc@020dc000 {
 560                                 compatible = "fsl,imx6q-gpc";
 561                                 reg = <0x020dc000 0x4000>;
 562                                 interrupts = <0 89 0x04 0 90 0x04>;
 563                         };
 564
 565                         gpr: iomuxc-gpr@020e0000 {
 566                                 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
 567                                 reg = <0x020e0000 0x38>;
 568                         };
 569
 570                         iomuxc: iomuxc@020e0000 {
 571                                 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
 572                                 reg = <0x020e0000 0x4000>;
 573
 574                                 audmux {
 575                                         pinctrl_audmux_1: audmux-1 {
 576                                                 fsl,pins = <
 577                                                         MX6QDL_PAD_SD2_DAT0__AUD4_RXD  0x80000000
 578                                                         MX6QDL_PAD_SD2_DAT3__AUD4_TXC  0x80000000
 579                                                         MX6QDL_PAD_SD2_DAT2__AUD4_TXD  0x80000000
 580                                                         MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x80000000
 581                                                 >;
 582                                         };
 583
 584                                         pinctrl_audmux_2: audmux-2 {
 585                                                 fsl,pins = <
 586                                                         MX6QDL_PAD_CSI0_DAT7__AUD3_RXD  0x80000000
 587                                                         MX6QDL_PAD_CSI0_DAT4__AUD3_TXC  0x80000000
 588                                                         MX6QDL_PAD_CSI0_DAT5__AUD3_TXD  0x80000000
 589                                                         MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
 590                                                 >;
 591                                         };
 592
 593                                         pinctrl_audmux_3: audmux-3 {
 594                                                 fsl,pins = <
 595                                                         MX6QDL_PAD_DISP0_DAT16__AUD5_TXC  0x80000000
 596                                                         MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x80000000
 597                                                         MX6QDL_PAD_DISP0_DAT19__AUD5_RXD  0x80000000
 598                                                 >;
 599                                         };
 600                                 };
 601
 602                                 ecspi1 {
 603                                         pinctrl_ecspi1_1: ecspi1grp-1 {
 604                                                 fsl,pins = <
 605                                                         MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
 606                                                         MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
 607                                                         MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
 608                                                 >;
 609                                         };
 610
 611                                         pinctrl_ecspi1_2: ecspi1grp-2 {
 612                                                 fsl,pins = <
 613                                                         MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
 614                                                         MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
 615                                                         MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
 616                                                 >;
 617                                         };
 618                                 };
 619
 620                                 ecspi3 {
 621                                         pinctrl_ecspi3_1: ecspi3grp-1 {
 622                                                 fsl,pins = <
 623                                                         MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
 624                                                         MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
 625                                                         MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
 626                                                 >;
 627                                         };
 628                                 };
 629
 630                                 enet {
 631                                         pinctrl_enet_1: enetgrp-1 {
 632                                                 fsl,pins = <
 633                                                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
 634                                                         MX6QDL_PAD_ENET_MDC__ENET_MDC         0x1b0b0
 635                                                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
 636                                                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
 637                                                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
 638                                                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
 639                                                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
 640                                                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
 641                                                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
 642                                                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
 643                                                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
 644                                                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
 645                                                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
 646                                                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
 647                                                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
 648                                                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK      0x4001b0a8
 649                                                 >;
 650                                         };
 651
 652                                         pinctrl_enet_2: enetgrp-2 {
 653                                                 fsl,pins = <
 654                                                         MX6QDL_PAD_KEY_COL1__ENET_MDIO        0x1b0b0
 655                                                         MX6QDL_PAD_KEY_COL2__ENET_MDC         0x1b0b0
 656                                                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
 657                                                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
 658                                                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
 659                                                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
 660                                                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
 661                                                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
 662                                                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
 663                                                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
 664                                                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
 665                                                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
 666                                                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
 667                                                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
 668                                                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
 669                                                 >;
 670                                         };
 671
 672                                         pinctrl_enet_3: enetgrp-3 {
 673                                                 fsl,pins = <
 674                                                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
 675                                                         MX6QDL_PAD_ENET_MDC__ENET_MDC         0x1b0b0
 676                                                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
 677                                                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
 678                                                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
 679                                                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
 680                                                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
 681                                                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
 682                                                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
 683                                                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
 684                                                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
 685                                                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
 686                                                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
 687                                                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
 688                                                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
 689                                                         MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN     0x1b0b0
 690                                                 >;
 691                                         };
 692                                 };
 693
 694                                 esai {
 695                                         pinctrl_esai_1: esaigrp-1 {
 696                                                 fsl,pins = <
 697                                                         MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1b030
 698                                                         MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK  0x1b030
 699                                                         MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS     0x1b030
 700                                                         MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2  0x1b030
 701                                                         MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3   0x1b030
 702                                                         MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1   0x1b030
 703                                                         MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0    0x1b030
 704                                                         MX6QDL_PAD_NANDF_CS2__ESAI_TX0       0x1b030
 705                                                         MX6QDL_PAD_NANDF_CS3__ESAI_TX1       0x1b030
 706                                                 >;
 707                                         };
 708
 709                                         pinctrl_esai_2: esaigrp-2 {
 710                                                 fsl,pins = <
 711                                                         MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
 712                                                         MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS    0x1b030
 713                                                         MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
 714                                                         MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3     0x1b030
 715                                                         MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1  0x1b030
 716                                                         MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0   0x1b030
 717                                                         MX6QDL_PAD_GPIO_17__ESAI_TX0        0x1b030
 718                                                         MX6QDL_PAD_NANDF_CS3__ESAI_TX1      0x1b030
 719                                                         MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK   0x1b030
 720                                                         MX6QDL_PAD_GPIO_9__ESAI_RX_FS       0x1b030
 721                                                 >;
 722                                         };
 723                                 };
 724
 725                                 flexcan1 {
 726                                         pinctrl_flexcan1_1: flexcan1grp-1 {
 727                                                 fsl,pins = <
 728                                                         MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
 729                                                         MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000
 730                                                 >;
 731                                         };
 732
 733                                         pinctrl_flexcan1_2: flexcan1grp-2 {
 734                                                 fsl,pins = <
 735                                                         MX6QDL_PAD_GPIO_7__FLEXCAN1_TX   0x80000000
 736                                                         MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
 737                                                 >;
 738                                         };
 739                                 };
 740
 741                                 flexcan2 {
 742                                         pinctrl_flexcan2_1: flexcan2grp-1 {
 743                                                 fsl,pins = <
 744                                                         MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000
 745                                                         MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000
 746                                                 >;
 747                                         };
 748                                 };
 749
 750                                 gpmi-nand {
 751                                         pinctrl_gpmi_nand_1: gpmi-nand-1 {
 752                                                 fsl,pins = <
 753                                                         MX6QDL_PAD_NANDF_CLE__NAND_CLE     0xb0b1
 754                                                         MX6QDL_PAD_NANDF_ALE__NAND_ALE     0xb0b1
 755                                                         MX6QDL_PAD_NANDF_WP_B__NAND_WP_B   0xb0b1
 756                                                         MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
 757                                                         MX6QDL_PAD_NANDF_CS0__NAND_CE0_B   0xb0b1
 758                                                         MX6QDL_PAD_NANDF_CS1__NAND_CE1_B   0xb0b1
 759                                                         MX6QDL_PAD_SD4_CMD__NAND_RE_B      0xb0b1
 760                                                         MX6QDL_PAD_SD4_CLK__NAND_WE_B      0xb0b1
 761                                                         MX6QDL_PAD_NANDF_D0__NAND_DATA00   0xb0b1
 762                                                         MX6QDL_PAD_NANDF_D1__NAND_DATA01   0xb0b1
 763                                                         MX6QDL_PAD_NANDF_D2__NAND_DATA02   0xb0b1
 764                                                         MX6QDL_PAD_NANDF_D3__NAND_DATA03   0xb0b1
 765                                                         MX6QDL_PAD_NANDF_D4__NAND_DATA04   0xb0b1
 766                                                         MX6QDL_PAD_NANDF_D5__NAND_DATA05   0xb0b1
 767                                                         MX6QDL_PAD_NANDF_D6__NAND_DATA06   0xb0b1
 768                                                         MX6QDL_PAD_NANDF_D7__NAND_DATA07   0xb0b1
 769                                                         MX6QDL_PAD_SD4_DAT0__NAND_DQS      0x00b1
 770                                                 >;
 771                                         };
 772                                 };
 773
 774                                 hdmi_hdcp {
 775                                         pinctrl_hdmi_hdcp_1: hdmihdcpgrp-1 {
 776                                                 fsl,pins = <
 777                                                         MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1
 778                                                         MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
 779                                                 >;
 780                                         };
 781
 782                                         pinctrl_hdmi_hdcp_2: hdmihdcpgrp-2 {
 783                                                 fsl,pins = <
 784                                                         MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
 785                                                         MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1
 786                                                 >;
 787                                         };
 788
 789                                         pinctrl_hdmi_hdcp_3: hdmihdcpgrp-3 {
 790                                                 fsl,pins = <
 791                                                         MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL  0x4001b8b1
 792                                                         MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
 793                                                 >;
 794                                         };
 795                                 };
 796
 797                                 hdmi_cec {
 798                                         pinctrl_hdmi_cec_1: hdmicecgrp-1 {
 799                                                 fsl,pins = <
 800                                                         MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
 801                                                 >;
 802                                         };
 803
 804                                         pinctrl_hdmi_cec_2: hdmicecgrp-2 {
 805                                                 fsl,pins = <
 806                                                         MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
 807                                                 >;
 808                                         };
 809                                 };
 810
 811                                 i2c1 {
 812                                         pinctrl_i2c1_1: i2c1grp-1 {
 813                                                 fsl,pins = <
 814                                                         MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
 815                                                         MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
 816                                                 >;
 817                                         };
 818
 819                                         pinctrl_i2c1_2: i2c1grp-2 {
 820                                                 fsl,pins = <
 821                                                         MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
 822                                                         MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
 823                                                 >;
 824                                         };
 825                                 };
 826
 827                                 i2c2 {
 828                                         pinctrl_i2c2_1: i2c2grp-1 {
 829                                                 fsl,pins = <
 830                                                         MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
 831                                                         MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
 832                                                 >;
 833                                         };
 834
 835                                         pinctrl_i2c2_2: i2c2grp-2 {
 836                                                 fsl,pins = <
 837                                                         MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
 838                                                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
 839                                                 >;
 840                                         };
 841
 842                                         pinctrl_i2c2_3: i2c2grp-3 {
 843                                                 fsl,pins = <
 844                                                         MX6QDL_PAD_EIM_EB2__I2C2_SCL  0x4001b8b1
 845                                                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
 846                                                 >;
 847                                         };
 848                                 };
 849
 850                                 i2c3 {
 851                                         pinctrl_i2c3_1: i2c3grp-1 {
 852                                                 fsl,pins = <
 853                                                         MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
 854                                                         MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
 855                                                 >;
 856                                         };
 857
 858                                         pinctrl_i2c3_2: i2c3grp-2 {
 859                                                 fsl,pins = <
 860                                                         MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
 861                                                         MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
 862                                                 >;
 863                                         };
 864
 865                                         pinctrl_i2c3_3: i2c3grp-3 {
 866                                                 fsl,pins = <
 867                                                         MX6QDL_PAD_GPIO_5__I2C3_SCL  0x4001b8b1
 868                                                         MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
 869                                                 >;
 870                                         };
 871
 872                                         pinctrl_i2c3_4: i2c3grp-4 {
 873                                                 fsl,pins = <
 874                                                         MX6QDL_PAD_GPIO_3__I2C3_SCL  0x4001b8b1
 875                                                         MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
 876                                                 >;
 877                                         };
 878                                 };
 879
 880                                 ipu1 {
 881                                         pinctrl_ipu1_1: ipu1grp-1 {
 882                                                 fsl,pins = <
 883                                                         MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
 884                                                         MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
 885                                                         MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
 886                                                         MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
 887                                                         MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04        0x80000000
 888                                                         MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x10
 889                                                         MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
 890                                                         MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
 891                                                         MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
 892                                                         MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
 893                                                         MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
 894                                                         MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
 895                                                         MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
 896                                                         MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
 897                                                         MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
 898                                                         MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
 899                                                         MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
 900                                                         MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
 901                                                         MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
 902                                                         MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
 903                                                         MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
 904                                                         MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
 905                                                         MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
 906                                                         MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x10
 907                                                         MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x10
 908                                                         MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x10
 909                                                         MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x10
 910                                                         MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x10
 911                                                         MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x10
 912                                                 >;
 913                                         };
 914
 915                                         pinctrl_ipu1_2: ipu1grp-2 { /* parallel camera */
 916                                                 fsl,pins = <
 917                                                         MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12    0x80000000
 918                                                         MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13    0x80000000
 919                                                         MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14    0x80000000
 920                                                         MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15    0x80000000
 921                                                         MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16    0x80000000
 922                                                         MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17    0x80000000
 923                                                         MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18    0x80000000
 924                                                         MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19    0x80000000
 925                                                         MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000
 926                                                         MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK   0x80000000
 927                                                         MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC      0x80000000
 928                                                         MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC     0x80000000
 929                                                 >;
 930                                         };
 931
 932                                         pinctrl_ipu1_3: ipu1grp-3 { /* parallel port 16-bit */
 933                                                 fsl,pins = <
 934                                                         MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04   0x80000000
 935                                                         MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05   0x80000000
 936                                                         MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06   0x80000000
 937                                                         MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07   0x80000000
 938                                                         MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08   0x80000000
 939                                                         MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09   0x80000000
 940                                                         MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10  0x80000000
 941                                                         MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11  0x80000000
 942                                                         MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12  0x80000000
 943                                                         MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13  0x80000000
 944                                                         MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14  0x80000000
 945                                                         MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15  0x80000000
 946                                                         MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16  0x80000000
 947                                                         MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17  0x80000000
 948                                                         MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18  0x80000000
 949                                                         MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19  0x80000000
 950                                                         MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
 951                                                         MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC    0x80000000
 952                                                         MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC   0x80000000
 953                                                 >;
 954                                         };
 955                                 };
 956
 957                                 mlb {
 958                                         pinctrl_mlb_1: mlbgrp-1 {
 959                                                 fsl,pins = <
 960                                                         MX6QDL_PAD_GPIO_3__MLB_CLK  0x71
 961                                                         MX6QDL_PAD_GPIO_6__MLB_SIG  0x71
 962                                                         MX6QDL_PAD_GPIO_2__MLB_DATA 0x71
 963                                                 >;
 964                                         };
 965
 966                                         pinctrl_mlb_2: mlbgrp-2 {
 967                                                 fsl,pins = <
 968                                                         MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x71
 969                                                         MX6QDL_PAD_GPIO_6__MLB_SIG    0x71
 970                                                         MX6QDL_PAD_GPIO_2__MLB_DATA   0x71
 971                                                 >;
 972                                         };
 973                                 };
 974
 975                                 pwm0 {
 976                                         pinctrl_pwm0_1: pwm0grp-1 {
 977                                                 fsl,pins = <
 978                                                         MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
 979                                                 >;
 980                                         };
 981                                 };
 982
 983                                 pwm3 {
 984                                         pinctrl_pwm3_1: pwm3grp-1 {
 985                                                 fsl,pins = <
 986                                                         MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
 987                                                 >;
 988                                         };
 989                                 };
 990
 991                                 spdif {
 992                                         pinctrl_spdif_1: spdifgrp-1 {
 993                                                 fsl,pins = <
 994                                                         MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
 995                                                 >;
 996                                         };
 997
 998                                         pinctrl_spdif_2: spdifgrp-2 {
 999                                                 fsl,pins = <
1000                                                         MX6QDL_PAD_GPIO_16__SPDIF_IN  0x1b0b0
1001                                                         MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
1002                                                 >;
1003                                         };
1004                                 };
1005
1006                                 uart1 {
1007                                         pinctrl_uart1_1: uart1grp-1 {
1008                                                 fsl,pins = <
1009                                                         MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
1010                                                         MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
1011                                                 >;
1012                                         };
1013                                 };
1014
1015                                 uart2 {
1016                                         pinctrl_uart2_1: uart2grp-1 {
1017                                                 fsl,pins = <
1018                                                         MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
1019                                                         MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
1020                                                 >;
1021                                         };
1022
1023                                         pinctrl_uart2_2: uart2grp-2 { /* DTE mode */
1024                                                 fsl,pins = <
1025                                                         MX6QDL_PAD_EIM_D26__UART2_RX_DATA   0x1b0b1
1026                                                         MX6QDL_PAD_EIM_D27__UART2_TX_DATA   0x1b0b1
1027                                                         MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1
1028                                                         MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1
1029                                                 >;
1030                                         };
1031                                 };
1032
1033                                 uart3 {
1034                                         pinctrl_uart3_1: uart3grp-1 {
1035                                                 fsl,pins = <
1036                                                         MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1
1037                                                         MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1
1038                                                         MX6QDL_PAD_EIM_D30__UART3_CTS_B   0x1b0b1
1039                                                         MX6QDL_PAD_EIM_EB3__UART3_RTS_B   0x1b0b1
1040                                                 >;
1041                                         };
1042
1043                                         pinctrl_uart3_2: uart3grp-2 {
1044                                                 fsl,pins = <
1045                                                         MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
1046                                                         MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
1047                                                         MX6QDL_PAD_EIM_D23__UART3_CTS_B   0x1b0b1
1048                                                         MX6QDL_PAD_EIM_EB3__UART3_RTS_B   0x1b0b1
1049                                                 >;
1050                                         };
1051                                 };
1052
1053                                 uart4 {
1054                                         pinctrl_uart4_1: uart4grp-1 {
1055                                                 fsl,pins = <
1056                                                         MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
1057                                                         MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
1058                                                 >;
1059                                         };
1060                                 };
1061
1062                                 usbotg {
1063                                         pinctrl_usbotg_1: usbotggrp-1 {
1064                                                 fsl,pins = <
1065                                                         MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
1066                                                 >;
1067                                         };
1068
1069                                         pinctrl_usbotg_2: usbotggrp-2 {
1070                                                 fsl,pins = <
1071                                                         MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
1072                                                 >;
1073                                         };
1074                                 };
1075
1076                                 usbh2 {
1077                                         pinctrl_usbh2_1: usbh2grp-1 {
1078                                                 fsl,pins = <
1079                                                         MX6QDL_PAD_RGMII_TXC__USB_H2_DATA      0x40013030
1080                                                         MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40013030
1081                                                 >;
1082                                         };
1083
1084                                         pinctrl_usbh2_2: usbh2grp-2 {
1085                                                 fsl,pins = <
1086                                                         MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40017030
1087                                                 >;
1088                                         };
1089                                 };
1090
1091                                 usbh3 {
1092                                         pinctrl_usbh3_1: usbh3grp-1 {
1093                                                 fsl,pins = <
1094                                                         MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x40013030
1095                                                         MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE  0x40013030
1096                                                 >;
1097                                         };
1098
1099                                         pinctrl_usbh3_2: usbh3grp-2 {
1100                                                 fsl,pins = <
1101                                                         MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40017030
1102                                                 >;
1103                                         };
1104                                 };
1105
1106                                 usdhc1 {
1107                                         pinctrl_usdhc1_1: usdhc1grp-1 {
1108                                                 fsl,pins = <
1109                                                         MX6QDL_PAD_SD1_CMD__SD1_CMD    0x17059
1110                                                         MX6QDL_PAD_SD1_CLK__SD1_CLK    0x10059
1111                                                         MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
1112                                                         MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
1113                                                         MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
1114                                                         MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
1115                                                         MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17059
1116                                                         MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17059
1117                                                         MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17059
1118                                                         MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17059
1119                                                 >;
1120                                         };
1121
1122                                         pinctrl_usdhc1_2: usdhc1grp-2 {
1123                                                 fsl,pins = <
1124                                                         MX6QDL_PAD_SD1_CMD__SD1_CMD    0x17059
1125                                                         MX6QDL_PAD_SD1_CLK__SD1_CLK    0x10059
1126                                                         MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
1127                                                         MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
1128                                                         MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
1129                                                         MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
1130                                                 >;
1131                                         };
1132                                 };
1133
1134                                 usdhc2 {
1135                                         pinctrl_usdhc2_1: usdhc2grp-1 {
1136                                                 fsl,pins = <
1137                                                         MX6QDL_PAD_SD2_CMD__SD2_CMD    0x17059
1138                                                         MX6QDL_PAD_SD2_CLK__SD2_CLK    0x10059
1139                                                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
1140                                                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
1141                                                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
1142                                                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
1143                                                         MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
1144                                                         MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
1145                                                         MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
1146                                                         MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
1147                                                 >;
1148                                         };
1149
1150                                         pinctrl_usdhc2_2: usdhc2grp-2 {
1151                                                 fsl,pins = <
1152                                                         MX6QDL_PAD_SD2_CMD__SD2_CMD    0x17059
1153                                                         MX6QDL_PAD_SD2_CLK__SD2_CLK    0x10059
1154                                                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
1155                                                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
1156                                                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
1157                                                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
1158                                                 >;
1159                                         };
1160                                 };
1161
1162                                 usdhc3 {
1163                                         pinctrl_usdhc3_1: usdhc3grp-1 {
1164                                                 fsl,pins = <
1165                                                         MX6QDL_PAD_SD3_CMD__SD3_CMD    0x17059
1166                                                         MX6QDL_PAD_SD3_CLK__SD3_CLK    0x10059
1167                                                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
1168                                                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
1169                                                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
1170                                                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
1171                                                         MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
1172                                                         MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
1173                                                         MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
1174                                                         MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
1175                                                 >;
1176                                         };
1177
1178                                         pinctrl_usdhc3_2: usdhc3grp-2 {
1179                                                 fsl,pins = <
1180                                                         MX6QDL_PAD_SD3_CMD__SD3_CMD    0x17059
1181                                                         MX6QDL_PAD_SD3_CLK__SD3_CLK    0x10059
1182                                                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
1183                                                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
1184                                                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
1185                                                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
1186                                                 >;
1187                                         };
1188                                 };
1189
1190                                 usdhc4 {
1191                                         pinctrl_usdhc4_1: usdhc4grp-1 {
1192                                                 fsl,pins = <
1193                                                         MX6QDL_PAD_SD4_CMD__SD4_CMD    0x17059
1194                                                         MX6QDL_PAD_SD4_CLK__SD4_CLK    0x10059
1195                                                         MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
1196                                                         MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
1197                                                         MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
1198                                                         MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
1199                                                         MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
1200                                                         MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
1201                                                         MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
1202                                                         MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
1203                                                 >;
1204                                         };
1205
1206                                         pinctrl_usdhc4_2: usdhc4grp-2 {
1207                                                 fsl,pins = <
1208                                                         MX6QDL_PAD_SD4_CMD__SD4_CMD    0x17059
1209                                                         MX6QDL_PAD_SD4_CLK__SD4_CLK    0x10059
1210                                                         MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
1211                                                         MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
1212                                                         MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
1213                                                         MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
1214                                                 >;
1215                                         };
1216                                 };
1217
1218                                 weim {
1219                                         pinctrl_weim_cs0_1: weim_cs0grp-1 {
1220                                                 fsl,pins = <
1221                                                         MX6QDL_PAD_EIM_CS0__EIM_CS0_B   0xb0b1
1222                                                 >;
1223                                         };
1224
1225                                         pinctrl_weim_nor_1: weim_norgrp-1 {
1226                                                 fsl,pins = <
1227                                                         MX6QDL_PAD_EIM_OE__EIM_OE_B     0xb0b1
1228                                                         MX6QDL_PAD_EIM_RW__EIM_RW       0xb0b1
1229                                                         MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
1230                                                         /* data */
1231                                                         MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
1232                                                         MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
1233                                                         MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
1234                                                         MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
1235                                                         MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
1236                                                         MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
1237                                                         MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
1238                                                         MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
1239                                                         MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
1240                                                         MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
1241                                                         MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
1242                                                         MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
1243                                                         MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
1244                                                         MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
1245                                                         MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
1246                                                         MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
1247                                                         /* address */
1248                                                         MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
1249                                                         MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
1250                                                         MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
1251                                                         MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
1252                                                         MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
1253                                                         MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
1254                                                         MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
1255                                                         MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
1256                                                         MX6QDL_PAD_EIM_DA15__EIM_AD15  0xb0b1
1257                                                         MX6QDL_PAD_EIM_DA14__EIM_AD14  0xb0b1
1258                                                         MX6QDL_PAD_EIM_DA13__EIM_AD13  0xb0b1
1259                                                         MX6QDL_PAD_EIM_DA12__EIM_AD12  0xb0b1
1260                                                         MX6QDL_PAD_EIM_DA11__EIM_AD11  0xb0b1
1261                                                         MX6QDL_PAD_EIM_DA10__EIM_AD10  0xb0b1
1262                                                         MX6QDL_PAD_EIM_DA9__EIM_AD09   0xb0b1
1263                                                         MX6QDL_PAD_EIM_DA8__EIM_AD08   0xb0b1
1264                                                         MX6QDL_PAD_EIM_DA7__EIM_AD07   0xb0b1
1265                                                         MX6QDL_PAD_EIM_DA6__EIM_AD06   0xb0b1
1266                                                         MX6QDL_PAD_EIM_DA5__EIM_AD05   0xb0b1
1267                                                         MX6QDL_PAD_EIM_DA4__EIM_AD04   0xb0b1
1268                                                         MX6QDL_PAD_EIM_DA3__EIM_AD03   0xb0b1
1269                                                         MX6QDL_PAD_EIM_DA2__EIM_AD02   0xb0b1
1270                                                         MX6QDL_PAD_EIM_DA1__EIM_AD01   0xb0b1
1271                                                         MX6QDL_PAD_EIM_DA0__EIM_AD00   0xb0b1
1272                                                 >;
1273                                         };
1274                                 };
1275                         };
1276
1277                         ldb: ldb@020e0008 {
1278                                 #address-cells = <1>;
1279                                 #size-cells = <0>;
1280                                 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
1281                                 gpr = <&gpr>;
1282                                 status = "disabled";
1283
1284                                 lvds-channel@0 {
1285                                         reg = <0>;
1286                                         status = "disabled";
1287                                 };
1288
1289                                 lvds-channel@1 {
1290                                         reg = <1>;
1291                                         status = "disabled";
1292                                 };
1293                         };
1294
1295                         dcic1: dcic@020e4000 {
1296                                 reg = <0x020e4000 0x4000>;
1297                                 interrupts = <0 124 0x04>;
1298                         };
1299
1300                         dcic2: dcic@020e8000 {
1301                                 reg = <0x020e8000 0x4000>;
1302                                 interrupts = <0 125 0x04>;
1303                         };
1304
1305                         sdma: sdma@020ec000 {
1306                                 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
1307                                 reg = <0x020ec000 0x4000>;
1308                                 interrupts = <0 2 0x04>;
1309                                 clocks = <&clks 155>, <&clks 155>;
1310                                 clock-names = "ipg", "ahb";
1311                                 #dma-cells = <3>;
1312                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
1313                         };
1314                 };
1315
1316                 aips-bus@02100000 { /* AIPS2 */
1317                         compatible = "fsl,aips-bus", "simple-bus";
1318                         #address-cells = <1>;
1319                         #size-cells = <1>;
1320                         reg = <0x02100000 0x100000>;
1321                         ranges;
1322
1323                         caam@02100000 {
1324                                 reg = <0x02100000 0x40000>;
1325                                 interrupts = <0 105 0x04 0 106 0x04>;
1326                         };
1327
1328                         aipstz@0217c000 { /* AIPSTZ2 */
1329                                 reg = <0x0217c000 0x4000>;
1330                         };
1331
1332                         usbotg: usb@02184000 {
1333                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1334                                 reg = <0x02184000 0x200>;
1335                                 interrupts = <0 43 0x04>;
1336                                 clocks = <&clks 162>;
1337                                 fsl,usbphy = <&usbphy1>;
1338                                 fsl,usbmisc = <&usbmisc 0>;
1339                                 status = "disabled";
1340                         };
1341
1342                         usbh1: usb@02184200 {
1343                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1344                                 reg = <0x02184200 0x200>;
1345                                 interrupts = <0 40 0x04>;
1346                                 clocks = <&clks 162>;
1347                                 fsl,usbphy = <&usbphy2>;
1348                                 fsl,usbmisc = <&usbmisc 1>;
1349                                 status = "disabled";
1350                         };
1351
1352                         usbh2: usb@02184400 {
1353                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1354                                 reg = <0x02184400 0x200>;
1355                                 interrupts = <0 41 0x04>;
1356                                 clocks = <&clks 162>;
1357                                 fsl,usbmisc = <&usbmisc 2>;
1358                                 status = "disabled";
1359                         };
1360
1361                         usbh3: usb@02184600 {
1362                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1363                                 reg = <0x02184600 0x200>;
1364                                 interrupts = <0 42 0x04>;
1365                                 clocks = <&clks 162>;
1366                                 fsl,usbmisc = <&usbmisc 3>;
1367                                 status = "disabled";
1368                         };
1369
1370                         usbmisc: usbmisc@02184800 {
1371                                 #index-cells = <1>;
1372                                 compatible = "fsl,imx6q-usbmisc";
1373                                 reg = <0x02184800 0x200>;
1374                                 clocks = <&clks 162>;
1375                         };
1376
1377                         fec: ethernet@02188000 {
1378                                 compatible = "fsl,imx6q-fec";
1379                                 reg = <0x02188000 0x4000>;
1380                                 interrupts = <0 118 0x04 0 119 0x04>;
1381                                 clocks = <&clks 117>, <&clks 117>, <&clks 190>;
1382                                 clock-names = "ipg", "ahb", "ptp";
1383                                 status = "disabled";
1384                         };
1385
1386                         mlb@0218c000 {
1387                                 reg = <0x0218c000 0x4000>;
1388                                 interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
1389                         };
1390
1391                         usdhc1: usdhc@02190000 {
1392                                 compatible = "fsl,imx6q-usdhc";
1393                                 reg = <0x02190000 0x4000>;
1394                                 interrupts = <0 22 0x04>;
1395                                 clocks = <&clks 163>, <&clks 163>, <&clks 163>;
1396                                 clock-names = "ipg", "ahb", "per";
1397                                 bus-width = <4>;
1398                                 status = "disabled";
1399                         };
1400
1401                         usdhc2: usdhc@02194000 {
1402                                 compatible = "fsl,imx6q-usdhc";
1403                                 reg = <0x02194000 0x4000>;
1404                                 interrupts = <0 23 0x04>;
1405                                 clocks = <&clks 164>, <&clks 164>, <&clks 164>;
1406                                 clock-names = "ipg", "ahb", "per";
1407                                 bus-width = <4>;
1408                                 status = "disabled";
1409                         };
1410
1411                         usdhc3: usdhc@02198000 {
1412                                 compatible = "fsl,imx6q-usdhc";
1413                                 reg = <0x02198000 0x4000>;
1414                                 interrupts = <0 24 0x04>;
1415                                 clocks = <&clks 165>, <&clks 165>, <&clks 165>;
1416                                 clock-names = "ipg", "ahb", "per";
1417                                 bus-width = <4>;
1418                                 status = "disabled";
1419                         };
1420
1421                         usdhc4: usdhc@0219c000 {
1422                                 compatible = "fsl,imx6q-usdhc";
1423                                 reg = <0x0219c000 0x4000>;
1424                                 interrupts = <0 25 0x04>;
1425                                 clocks = <&clks 166>, <&clks 166>, <&clks 166>;
1426                                 clock-names = "ipg", "ahb", "per";
1427                                 bus-width = <4>;
1428                                 status = "disabled";
1429                         };
1430
1431                         i2c1: i2c@021a0000 {
1432                                 #address-cells = <1>;
1433                                 #size-cells = <0>;
1434                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1435                                 reg = <0x021a0000 0x4000>;
1436                                 interrupts = <0 36 0x04>;
1437                                 clocks = <&clks 125>;
1438                                 status = "disabled";
1439                         };
1440
1441                         i2c2: i2c@021a4000 {
1442                                 #address-cells = <1>;
1443                                 #size-cells = <0>;
1444                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1445                                 reg = <0x021a4000 0x4000>;
1446                                 interrupts = <0 37 0x04>;
1447                                 clocks = <&clks 126>;
1448                                 status = "disabled";
1449                         };
1450
1451                         i2c3: i2c@021a8000 {
1452                                 #address-cells = <1>;
1453                                 #size-cells = <0>;
1454                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1455                                 reg = <0x021a8000 0x4000>;
1456                                 interrupts = <0 38 0x04>;
1457                                 clocks = <&clks 127>;
1458                                 status = "disabled";
1459                         };
1460
1461                         romcp@021ac000 {
1462                                 reg = <0x021ac000 0x4000>;
1463                         };
1464
1465                         mmdc0: mmdc@021b0000 { /* MMDC0 */
1466                                 compatible = "fsl,imx6q-mmdc";
1467                                 reg = <0x021b0000 0x4000>;
1468                         };
1469
1470                         mmdc1: mmdc@021b4000 { /* MMDC1 */
1471                                 reg = <0x021b4000 0x4000>;
1472                         };
1473
1474                         weim: weim@021b8000 {
1475                                 compatible = "fsl,imx6q-weim";
1476                                 reg = <0x021b8000 0x4000>;
1477                                 interrupts = <0 14 0x04>;
1478                                 clocks = <&clks 196>;
1479                         };
1480
1481                         ocotp@021bc000 {
1482                                 compatible = "fsl,imx6q-ocotp";
1483                                 reg = <0x021bc000 0x4000>;
1484                         };
1485
1486                         tzasc@021d0000 { /* TZASC1 */
1487                                 reg = <0x021d0000 0x4000>;
1488                                 interrupts = <0 108 0x04>;
1489                         };
1490
1491                         tzasc@021d4000 { /* TZASC2 */
1492                                 reg = <0x021d4000 0x4000>;
1493                                 interrupts = <0 109 0x04>;
1494                         };
1495
1496                         audmux: audmux@021d8000 {
1497                                 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
1498                                 reg = <0x021d8000 0x4000>;
1499                                 status = "disabled";
1500                         };
1501
1502                         mipi@021dc000 { /* MIPI-CSI */
1503                                 reg = <0x021dc000 0x4000>;
1504                         };
1505
1506                         mipi@021e0000 { /* MIPI-DSI */
1507                                 reg = <0x021e0000 0x4000>;
1508                         };
1509
1510                         vdoa@021e4000 {
1511                                 reg = <0x021e4000 0x4000>;
1512                                 interrupts = <0 18 0x04>;
1513                         };
1514
1515                         uart2: serial@021e8000 {
1516                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1517                                 reg = <0x021e8000 0x4000>;
1518                                 interrupts = <0 27 0x04>;
1519                                 clocks = <&clks 160>, <&clks 161>;
1520                                 clock-names = "ipg", "per";
1521                                 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1522                                 dma-names = "rx", "tx";
1523                                 status = "disabled";
1524                         };
1525
1526                         uart3: serial@021ec000 {
1527                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1528                                 reg = <0x021ec000 0x4000>;
1529                                 interrupts = <0 28 0x04>;
1530                                 clocks = <&clks 160>, <&clks 161>;
1531                                 clock-names = "ipg", "per";
1532                                 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1533                                 dma-names = "rx", "tx";
1534                                 status = "disabled";
1535                         };
1536
1537                         uart4: serial@021f0000 {
1538                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1539                                 reg = <0x021f0000 0x4000>;
1540                                 interrupts = <0 29 0x04>;
1541                                 clocks = <&clks 160>, <&clks 161>;
1542                                 clock-names = "ipg", "per";
1543                                 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1544                                 dma-names = "rx", "tx";
1545                                 status = "disabled";
1546                         };
1547
1548                         uart5: serial@021f4000 {
1549                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1550                                 reg = <0x021f4000 0x4000>;
1551                                 interrupts = <0 30 0x04>;
1552                                 clocks = <&clks 160>, <&clks 161>;
1553                                 clock-names = "ipg", "per";
1554                                 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1555                                 dma-names = "rx", "tx";
1556                                 status = "disabled";
1557                         };
1558                 };
1559
1560                 ipu1: ipu@02400000 {
1561                         #crtc-cells = <1>;
1562                         compatible = "fsl,imx6q-ipu";
1563                         reg = <0x02400000 0x400000>;
1564                         interrupts = <0 6 0x4 0 5 0x4>;
1565                         clocks = <&clks 130>, <&clks 131>, <&clks 132>;
1566                         clock-names = "bus", "di0", "di1";
1567                         resets = <&src 2>;
1568                 };
1569         };
1570 };