2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include <dt-bindings/clock/imx6qdl-clock.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include "skeleton.dtsi"
50 intc: interrupt-controller@00a01000 {
51 compatible = "arm,cortex-a9-gic";
52 #interrupt-cells = <3>;
54 reg = <0x00a01000 0x1000>,
63 compatible = "fsl,imx-ckil", "fixed-clock";
65 clock-frequency = <32768>;
69 compatible = "fsl,imx-ckih1", "fixed-clock";
71 clock-frequency = <0>;
75 compatible = "fsl,imx-osc", "fixed-clock";
77 clock-frequency = <24000000>;
84 compatible = "simple-bus";
85 interrupt-parent = <&intc>;
88 dma_apbh: dma-apbh@00110000 {
89 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
90 reg = <0x00110000 0x2000>;
91 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
92 <0 13 IRQ_TYPE_LEVEL_HIGH>,
93 <0 13 IRQ_TYPE_LEVEL_HIGH>,
94 <0 13 IRQ_TYPE_LEVEL_HIGH>;
95 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
98 clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
101 gpmi: gpmi-nand@00112000 {
102 compatible = "fsl,imx6q-gpmi-nand";
103 #address-cells = <1>;
105 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
106 reg-names = "gpmi-nand", "bch";
107 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
108 interrupt-names = "bch";
109 clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
110 <&clks IMX6QDL_CLK_GPMI_APB>,
111 <&clks IMX6QDL_CLK_GPMI_BCH>,
112 <&clks IMX6QDL_CLK_GPMI_BCH_APB>,
113 <&clks IMX6QDL_CLK_PER1_BCH>;
114 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
115 "gpmi_bch_apb", "per1_bch";
116 dmas = <&dma_apbh 0>;
122 compatible = "arm,cortex-a9-twd-timer";
123 reg = <0x00a00600 0x20>;
124 interrupts = <1 13 0xf01>;
125 clocks = <&clks IMX6QDL_CLK_TWD>;
128 L2: l2-cache@00a02000 {
129 compatible = "arm,pl310-cache";
130 reg = <0x00a02000 0x1000>;
131 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
134 arm,tag-latency = <4 2 3>;
135 arm,data-latency = <4 2 3>;
138 pcie: pcie@0x01000000 {
139 compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
140 reg = <0x01ffc000 0x4000>; /* DBI */
141 #address-cells = <3>;
144 ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */
145 0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */
146 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
148 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
149 interrupt-names = "msi";
150 #interrupt-cells = <1>;
151 interrupt-map-mask = <0 0 0 0x7>;
152 interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
153 <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
154 <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
155 <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
156 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
157 <&clks IMX6QDL_CLK_LVDS1_GATE>,
158 <&clks IMX6QDL_CLK_PCIE_REF_125M>;
159 clock-names = "pcie", "pcie_bus", "pcie_phy";
164 compatible = "arm,cortex-a9-pmu";
165 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
168 aips-bus@02000000 { /* AIPS1 */
169 compatible = "fsl,aips-bus", "simple-bus";
170 #address-cells = <1>;
172 reg = <0x02000000 0x100000>;
176 compatible = "fsl,spba-bus", "simple-bus";
177 #address-cells = <1>;
179 reg = <0x02000000 0x40000>;
182 spdif: spdif@02004000 {
183 compatible = "fsl,imx35-spdif";
184 reg = <0x02004000 0x4000>;
185 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
186 dmas = <&sdma 14 18 0>,
188 dma-names = "rx", "tx";
189 clocks = <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_OSC>,
190 <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_DUMMY>,
191 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_DUMMY>,
192 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_DUMMY>,
193 <&clks IMX6QDL_CLK_DUMMY>;
194 clock-names = "core", "rxtx0",
202 ecspi1: ecspi@02008000 {
203 #address-cells = <1>;
205 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
206 reg = <0x02008000 0x4000>;
207 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
208 clocks = <&clks IMX6QDL_CLK_ECSPI1>,
209 <&clks IMX6QDL_CLK_ECSPI1>;
210 clock-names = "ipg", "per";
211 dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
212 dma-names = "rx", "tx";
216 ecspi2: ecspi@0200c000 {
217 #address-cells = <1>;
219 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
220 reg = <0x0200c000 0x4000>;
221 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
222 clocks = <&clks IMX6QDL_CLK_ECSPI2>,
223 <&clks IMX6QDL_CLK_ECSPI2>;
224 clock-names = "ipg", "per";
225 dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
226 dma-names = "rx", "tx";
230 ecspi3: ecspi@02010000 {
231 #address-cells = <1>;
233 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
234 reg = <0x02010000 0x4000>;
235 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
236 clocks = <&clks IMX6QDL_CLK_ECSPI3>,
237 <&clks IMX6QDL_CLK_ECSPI3>;
238 clock-names = "ipg", "per";
239 dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
240 dma-names = "rx", "tx";
244 ecspi4: ecspi@02014000 {
245 #address-cells = <1>;
247 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
248 reg = <0x02014000 0x4000>;
249 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
250 clocks = <&clks IMX6QDL_CLK_ECSPI4>,
251 <&clks IMX6QDL_CLK_ECSPI4>;
252 clock-names = "ipg", "per";
253 dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
254 dma-names = "rx", "tx";
258 uart1: serial@02020000 {
259 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
260 reg = <0x02020000 0x4000>;
261 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
262 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
263 <&clks IMX6QDL_CLK_UART_SERIAL>;
264 clock-names = "ipg", "per";
265 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
266 dma-names = "rx", "tx";
270 esai: esai@02024000 {
271 reg = <0x02024000 0x4000>;
272 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
276 compatible = "fsl,imx6q-ssi",
278 reg = <0x02028000 0x4000>;
279 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
280 clocks = <&clks IMX6QDL_CLK_SSI1_IPG>;
281 dmas = <&sdma 37 1 0>,
283 dma-names = "rx", "tx";
284 fsl,fifo-depth = <15>;
289 compatible = "fsl,imx6q-ssi",
291 reg = <0x0202c000 0x4000>;
292 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
293 clocks = <&clks IMX6QDL_CLK_SSI2_IPG>;
294 dmas = <&sdma 41 1 0>,
296 dma-names = "rx", "tx";
297 fsl,fifo-depth = <15>;
302 compatible = "fsl,imx6q-ssi",
304 reg = <0x02030000 0x4000>;
305 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
306 clocks = <&clks IMX6QDL_CLK_SSI3_IPG>;
307 dmas = <&sdma 45 1 0>,
309 dma-names = "rx", "tx";
310 fsl,fifo-depth = <15>;
314 asrc: asrc@02034000 {
315 reg = <0x02034000 0x4000>;
316 interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
320 reg = <0x0203c000 0x4000>;
325 reg = <0x02040000 0x3c000>;
326 interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>,
327 <0 12 IRQ_TYPE_LEVEL_HIGH>;
330 aipstz@0207c000 { /* AIPSTZ1 */
331 reg = <0x0207c000 0x4000>;
336 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
337 reg = <0x02080000 0x4000>;
338 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
339 clocks = <&clks IMX6QDL_CLK_IPG>,
340 <&clks IMX6QDL_CLK_PWM1>;
341 clock-names = "ipg", "per";
346 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
347 reg = <0x02084000 0x4000>;
348 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
349 clocks = <&clks IMX6QDL_CLK_IPG>,
350 <&clks IMX6QDL_CLK_PWM2>;
351 clock-names = "ipg", "per";
356 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
357 reg = <0x02088000 0x4000>;
358 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
359 clocks = <&clks IMX6QDL_CLK_IPG>,
360 <&clks IMX6QDL_CLK_PWM3>;
361 clock-names = "ipg", "per";
366 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
367 reg = <0x0208c000 0x4000>;
368 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
369 clocks = <&clks IMX6QDL_CLK_IPG>,
370 <&clks IMX6QDL_CLK_PWM4>;
371 clock-names = "ipg", "per";
374 can1: flexcan@02090000 {
375 compatible = "fsl,imx6q-flexcan";
376 reg = <0x02090000 0x4000>;
377 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
378 clocks = <&clks IMX6QDL_CLK_CAN1_IPG>,
379 <&clks IMX6QDL_CLK_CAN1_SERIAL>;
380 clock-names = "ipg", "per";
384 can2: flexcan@02094000 {
385 compatible = "fsl,imx6q-flexcan";
386 reg = <0x02094000 0x4000>;
387 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
388 clocks = <&clks IMX6QDL_CLK_CAN2_IPG>,
389 <&clks IMX6QDL_CLK_CAN2_SERIAL>;
390 clock-names = "ipg", "per";
395 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
396 reg = <0x02098000 0x4000>;
397 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
398 clocks = <&clks IMX6QDL_CLK_GPT_IPG>,
399 <&clks IMX6QDL_CLK_GPT_IPG_PER>;
400 clock-names = "ipg", "per";
403 gpio1: gpio@0209c000 {
404 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
405 reg = <0x0209c000 0x4000>;
406 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
407 <0 67 IRQ_TYPE_LEVEL_HIGH>;
410 interrupt-controller;
411 #interrupt-cells = <2>;
414 gpio2: gpio@020a0000 {
415 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
416 reg = <0x020a0000 0x4000>;
417 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
418 <0 69 IRQ_TYPE_LEVEL_HIGH>;
421 interrupt-controller;
422 #interrupt-cells = <2>;
425 gpio3: gpio@020a4000 {
426 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
427 reg = <0x020a4000 0x4000>;
428 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
429 <0 71 IRQ_TYPE_LEVEL_HIGH>;
432 interrupt-controller;
433 #interrupt-cells = <2>;
436 gpio4: gpio@020a8000 {
437 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
438 reg = <0x020a8000 0x4000>;
439 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
440 <0 73 IRQ_TYPE_LEVEL_HIGH>;
443 interrupt-controller;
444 #interrupt-cells = <2>;
447 gpio5: gpio@020ac000 {
448 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
449 reg = <0x020ac000 0x4000>;
450 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
451 <0 75 IRQ_TYPE_LEVEL_HIGH>;
454 interrupt-controller;
455 #interrupt-cells = <2>;
458 gpio6: gpio@020b0000 {
459 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
460 reg = <0x020b0000 0x4000>;
461 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
462 <0 77 IRQ_TYPE_LEVEL_HIGH>;
465 interrupt-controller;
466 #interrupt-cells = <2>;
469 gpio7: gpio@020b4000 {
470 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
471 reg = <0x020b4000 0x4000>;
472 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
473 <0 79 IRQ_TYPE_LEVEL_HIGH>;
476 interrupt-controller;
477 #interrupt-cells = <2>;
481 compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
482 reg = <0x020b8000 0x4000>;
483 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
484 clocks = <&clks IMX6QDL_CLK_IPG>;
488 wdog1: wdog@020bc000 {
489 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
490 reg = <0x020bc000 0x4000>;
491 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
492 clocks = <&clks IMX6QDL_CLK_DUMMY>;
495 wdog2: wdog@020c0000 {
496 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
497 reg = <0x020c0000 0x4000>;
498 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
499 clocks = <&clks IMX6QDL_CLK_DUMMY>;
504 compatible = "fsl,imx6q-ccm";
505 reg = <0x020c4000 0x4000>;
506 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
507 <0 88 IRQ_TYPE_LEVEL_HIGH>;
511 anatop: anatop@020c8000 {
512 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
513 reg = <0x020c8000 0x1000>;
514 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
515 <0 54 IRQ_TYPE_LEVEL_HIGH>,
516 <0 127 IRQ_TYPE_LEVEL_HIGH>;
519 compatible = "fsl,anatop-regulator";
520 regulator-name = "vdd1p1";
521 regulator-min-microvolt = <800000>;
522 regulator-max-microvolt = <1375000>;
524 anatop-reg-offset = <0x110>;
525 anatop-vol-bit-shift = <8>;
526 anatop-vol-bit-width = <5>;
527 anatop-min-bit-val = <4>;
528 anatop-min-voltage = <800000>;
529 anatop-max-voltage = <1375000>;
533 compatible = "fsl,anatop-regulator";
534 regulator-name = "vdd3p0";
535 regulator-min-microvolt = <2800000>;
536 regulator-max-microvolt = <3150000>;
538 anatop-reg-offset = <0x120>;
539 anatop-vol-bit-shift = <8>;
540 anatop-vol-bit-width = <5>;
541 anatop-min-bit-val = <0>;
542 anatop-min-voltage = <2625000>;
543 anatop-max-voltage = <3400000>;
547 compatible = "fsl,anatop-regulator";
548 regulator-name = "vdd2p5";
549 regulator-min-microvolt = <2000000>;
550 regulator-max-microvolt = <2750000>;
552 anatop-reg-offset = <0x130>;
553 anatop-vol-bit-shift = <8>;
554 anatop-vol-bit-width = <5>;
555 anatop-min-bit-val = <0>;
556 anatop-min-voltage = <2000000>;
557 anatop-max-voltage = <2750000>;
560 reg_arm: regulator-vddcore@140 {
561 compatible = "fsl,anatop-regulator";
562 regulator-name = "vddarm";
563 regulator-min-microvolt = <725000>;
564 regulator-max-microvolt = <1450000>;
566 anatop-reg-offset = <0x140>;
567 anatop-vol-bit-shift = <0>;
568 anatop-vol-bit-width = <5>;
569 anatop-delay-reg-offset = <0x170>;
570 anatop-delay-bit-shift = <24>;
571 anatop-delay-bit-width = <2>;
572 anatop-min-bit-val = <1>;
573 anatop-min-voltage = <725000>;
574 anatop-max-voltage = <1450000>;
577 reg_pu: regulator-vddpu@140 {
578 compatible = "fsl,anatop-regulator";
579 regulator-name = "vddpu";
580 regulator-min-microvolt = <725000>;
581 regulator-max-microvolt = <1450000>;
583 anatop-reg-offset = <0x140>;
584 anatop-vol-bit-shift = <9>;
585 anatop-vol-bit-width = <5>;
586 anatop-delay-reg-offset = <0x170>;
587 anatop-delay-bit-shift = <26>;
588 anatop-delay-bit-width = <2>;
589 anatop-min-bit-val = <1>;
590 anatop-min-voltage = <725000>;
591 anatop-max-voltage = <1450000>;
594 reg_soc: regulator-vddsoc@140 {
595 compatible = "fsl,anatop-regulator";
596 regulator-name = "vddsoc";
597 regulator-min-microvolt = <725000>;
598 regulator-max-microvolt = <1450000>;
600 anatop-reg-offset = <0x140>;
601 anatop-vol-bit-shift = <18>;
602 anatop-vol-bit-width = <5>;
603 anatop-delay-reg-offset = <0x170>;
604 anatop-delay-bit-shift = <28>;
605 anatop-delay-bit-width = <2>;
606 anatop-min-bit-val = <1>;
607 anatop-min-voltage = <725000>;
608 anatop-max-voltage = <1450000>;
613 compatible = "fsl,imx6q-tempmon";
614 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
615 fsl,tempmon = <&anatop>;
616 fsl,tempmon-data = <&ocotp>;
617 clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
620 usbphy1: usbphy@020c9000 {
621 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
622 reg = <0x020c9000 0x1000>;
623 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
624 clocks = <&clks IMX6QDL_CLK_USBPHY1>;
625 fsl,anatop = <&anatop>;
628 usbphy2: usbphy@020ca000 {
629 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
630 reg = <0x020ca000 0x1000>;
631 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
632 clocks = <&clks IMX6QDL_CLK_USBPHY2>;
633 fsl,anatop = <&anatop>;
637 compatible = "fsl,sec-v4.0-mon", "simple-bus";
638 #address-cells = <1>;
640 ranges = <0 0x020cc000 0x4000>;
643 compatible = "fsl,sec-v4.0-mon-rtc-lp";
645 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
646 <0 20 IRQ_TYPE_LEVEL_HIGH>;
650 epit1: epit@020d0000 { /* EPIT1 */
651 reg = <0x020d0000 0x4000>;
652 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
655 epit2: epit@020d4000 { /* EPIT2 */
656 reg = <0x020d4000 0x4000>;
657 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
661 compatible = "fsl,imx6q-src", "fsl,imx51-src";
662 reg = <0x020d8000 0x4000>;
663 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
664 <0 96 IRQ_TYPE_LEVEL_HIGH>;
669 compatible = "fsl,imx6q-gpc";
670 reg = <0x020dc000 0x4000>;
671 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
672 <0 90 IRQ_TYPE_LEVEL_HIGH>;
675 gpr: iomuxc-gpr@020e0000 {
676 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
677 reg = <0x020e0000 0x38>;
680 iomuxc: iomuxc@020e0000 {
681 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
682 reg = <0x020e0000 0x4000>;
686 #address-cells = <1>;
688 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
693 #address-cells = <1>;
701 lvds0_mux_0: endpoint {
702 remote-endpoint = <&ipu1_di0_lvds0>;
709 lvds0_mux_1: endpoint {
710 remote-endpoint = <&ipu1_di1_lvds0>;
716 #address-cells = <1>;
724 lvds1_mux_0: endpoint {
725 remote-endpoint = <&ipu1_di0_lvds1>;
732 lvds1_mux_1: endpoint {
733 remote-endpoint = <&ipu1_di1_lvds1>;
740 #address-cells = <1>;
742 reg = <0x00120000 0x9000>;
743 interrupts = <0 115 0x04>;
745 clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
746 <&clks IMX6QDL_CLK_HDMI_ISFR>;
747 clock-names = "iahb", "isfr";
753 hdmi_mux_0: endpoint {
754 remote-endpoint = <&ipu1_di0_hdmi>;
761 hdmi_mux_1: endpoint {
762 remote-endpoint = <&ipu1_di1_hdmi>;
767 dcic1: dcic@020e4000 {
768 reg = <0x020e4000 0x4000>;
769 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
772 dcic2: dcic@020e8000 {
773 reg = <0x020e8000 0x4000>;
774 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
777 sdma: sdma@020ec000 {
778 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
779 reg = <0x020ec000 0x4000>;
780 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
781 clocks = <&clks IMX6QDL_CLK_SDMA>,
782 <&clks IMX6QDL_CLK_SDMA>;
783 clock-names = "ipg", "ahb";
785 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
789 aips-bus@02100000 { /* AIPS2 */
790 compatible = "fsl,aips-bus", "simple-bus";
791 #address-cells = <1>;
793 reg = <0x02100000 0x100000>;
797 reg = <0x02100000 0x40000>;
798 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>,
799 <0 106 IRQ_TYPE_LEVEL_HIGH>;
802 aipstz@0217c000 { /* AIPSTZ2 */
803 reg = <0x0217c000 0x4000>;
806 usbotg: usb@02184000 {
807 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
808 reg = <0x02184000 0x200>;
809 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
810 clocks = <&clks IMX6QDL_CLK_USBOH3>;
811 fsl,usbphy = <&usbphy1>;
812 fsl,usbmisc = <&usbmisc 0>;
816 usbh1: usb@02184200 {
817 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
818 reg = <0x02184200 0x200>;
819 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
820 clocks = <&clks IMX6QDL_CLK_USBOH3>;
821 fsl,usbphy = <&usbphy2>;
822 fsl,usbmisc = <&usbmisc 1>;
826 usbh2: usb@02184400 {
827 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
828 reg = <0x02184400 0x200>;
829 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
830 clocks = <&clks IMX6QDL_CLK_USBOH3>;
831 fsl,usbmisc = <&usbmisc 2>;
835 usbh3: usb@02184600 {
836 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
837 reg = <0x02184600 0x200>;
838 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
839 clocks = <&clks IMX6QDL_CLK_USBOH3>;
840 fsl,usbmisc = <&usbmisc 3>;
844 usbmisc: usbmisc@02184800 {
846 compatible = "fsl,imx6q-usbmisc";
847 reg = <0x02184800 0x200>;
848 clocks = <&clks IMX6QDL_CLK_USBOH3>;
851 fec: ethernet@02188000 {
852 compatible = "fsl,imx6q-fec";
853 reg = <0x02188000 0x4000>;
854 interrupts-extended =
855 <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
856 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
857 clocks = <&clks IMX6QDL_CLK_ENET>,
858 <&clks IMX6QDL_CLK_ENET>,
859 <&clks IMX6QDL_CLK_ENET_REF>;
860 clock-names = "ipg", "ahb", "ptp";
865 reg = <0x0218c000 0x4000>;
866 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
867 <0 117 IRQ_TYPE_LEVEL_HIGH>,
868 <0 126 IRQ_TYPE_LEVEL_HIGH>;
871 usdhc1: usdhc@02190000 {
872 compatible = "fsl,imx6q-usdhc";
873 reg = <0x02190000 0x4000>;
874 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
875 clocks = <&clks IMX6QDL_CLK_USDHC1>,
876 <&clks IMX6QDL_CLK_USDHC1>,
877 <&clks IMX6QDL_CLK_USDHC1>;
878 clock-names = "ipg", "ahb", "per";
883 usdhc2: usdhc@02194000 {
884 compatible = "fsl,imx6q-usdhc";
885 reg = <0x02194000 0x4000>;
886 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
887 clocks = <&clks IMX6QDL_CLK_USDHC2>,
888 <&clks IMX6QDL_CLK_USDHC2>,
889 <&clks IMX6QDL_CLK_USDHC2>;
890 clock-names = "ipg", "ahb", "per";
895 usdhc3: usdhc@02198000 {
896 compatible = "fsl,imx6q-usdhc";
897 reg = <0x02198000 0x4000>;
898 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
899 clocks = <&clks IMX6QDL_CLK_USDHC3>,
900 <&clks IMX6QDL_CLK_USDHC3>,
901 <&clks IMX6QDL_CLK_USDHC3>;
902 clock-names = "ipg", "ahb", "per";
907 usdhc4: usdhc@0219c000 {
908 compatible = "fsl,imx6q-usdhc";
909 reg = <0x0219c000 0x4000>;
910 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
911 clocks = <&clks IMX6QDL_CLK_USDHC4>,
912 <&clks IMX6QDL_CLK_USDHC4>,
913 <&clks IMX6QDL_CLK_USDHC4>;
914 clock-names = "ipg", "ahb", "per";
920 #address-cells = <1>;
922 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
923 reg = <0x021a0000 0x4000>;
924 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
925 clocks = <&clks IMX6QDL_CLK_I2C1>;
930 #address-cells = <1>;
932 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
933 reg = <0x021a4000 0x4000>;
934 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
935 clocks = <&clks IMX6QDL_CLK_I2C2>;
940 #address-cells = <1>;
942 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
943 reg = <0x021a8000 0x4000>;
944 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
945 clocks = <&clks IMX6QDL_CLK_I2C3>;
950 reg = <0x021ac000 0x4000>;
953 mmdc0: mmdc@021b0000 { /* MMDC0 */
954 compatible = "fsl,imx6q-mmdc";
955 reg = <0x021b0000 0x4000>;
958 mmdc1: mmdc@021b4000 { /* MMDC1 */
959 reg = <0x021b4000 0x4000>;
962 weim: weim@021b8000 {
963 compatible = "fsl,imx6q-weim";
964 reg = <0x021b8000 0x4000>;
965 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
966 clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
969 ocotp: ocotp@021bc000 {
970 compatible = "fsl,imx6q-ocotp", "syscon";
971 reg = <0x021bc000 0x4000>;
974 tzasc@021d0000 { /* TZASC1 */
975 reg = <0x021d0000 0x4000>;
976 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
979 tzasc@021d4000 { /* TZASC2 */
980 reg = <0x021d4000 0x4000>;
981 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
984 audmux: audmux@021d8000 {
985 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
986 reg = <0x021d8000 0x4000>;
990 mipi_csi: mipi@021dc000 {
991 reg = <0x021dc000 0x4000>;
994 mipi_dsi: mipi@021e0000 {
995 #address-cells = <1>;
997 reg = <0x021e0000 0x4000>;
1003 mipi_mux_0: endpoint {
1004 remote-endpoint = <&ipu1_di0_mipi>;
1011 mipi_mux_1: endpoint {
1012 remote-endpoint = <&ipu1_di1_mipi>;
1018 reg = <0x021e4000 0x4000>;
1019 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
1022 uart2: serial@021e8000 {
1023 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1024 reg = <0x021e8000 0x4000>;
1025 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
1026 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1027 <&clks IMX6QDL_CLK_UART_SERIAL>;
1028 clock-names = "ipg", "per";
1029 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1030 dma-names = "rx", "tx";
1031 status = "disabled";
1034 uart3: serial@021ec000 {
1035 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1036 reg = <0x021ec000 0x4000>;
1037 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
1038 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1039 <&clks IMX6QDL_CLK_UART_SERIAL>;
1040 clock-names = "ipg", "per";
1041 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1042 dma-names = "rx", "tx";
1043 status = "disabled";
1046 uart4: serial@021f0000 {
1047 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1048 reg = <0x021f0000 0x4000>;
1049 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
1050 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1051 <&clks IMX6QDL_CLK_UART_SERIAL>;
1052 clock-names = "ipg", "per";
1053 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1054 dma-names = "rx", "tx";
1055 status = "disabled";
1058 uart5: serial@021f4000 {
1059 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1060 reg = <0x021f4000 0x4000>;
1061 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
1062 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1063 <&clks IMX6QDL_CLK_UART_SERIAL>;
1064 clock-names = "ipg", "per";
1065 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1066 dma-names = "rx", "tx";
1067 status = "disabled";
1071 ipu1: ipu@02400000 {
1072 #address-cells = <1>;
1074 compatible = "fsl,imx6q-ipu";
1075 reg = <0x02400000 0x400000>;
1076 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
1077 <0 5 IRQ_TYPE_LEVEL_HIGH>;
1078 clocks = <&clks IMX6QDL_CLK_IPU1>,
1079 <&clks IMX6QDL_CLK_IPU1_DI0>,
1080 <&clks IMX6QDL_CLK_IPU1_DI1>;
1081 clock-names = "bus", "di0", "di1";
1093 #address-cells = <1>;
1097 ipu1_di0_disp0: endpoint@0 {
1100 ipu1_di0_hdmi: endpoint@1 {
1101 remote-endpoint = <&hdmi_mux_0>;
1104 ipu1_di0_mipi: endpoint@2 {
1105 remote-endpoint = <&mipi_mux_0>;
1108 ipu1_di0_lvds0: endpoint@3 {
1109 remote-endpoint = <&lvds0_mux_0>;
1112 ipu1_di0_lvds1: endpoint@4 {
1113 remote-endpoint = <&lvds1_mux_0>;
1118 #address-cells = <1>;
1122 ipu1_di0_disp1: endpoint@0 {
1125 ipu1_di1_hdmi: endpoint@1 {
1126 remote-endpoint = <&hdmi_mux_1>;
1129 ipu1_di1_mipi: endpoint@2 {
1130 remote-endpoint = <&mipi_mux_1>;
1133 ipu1_di1_lvds0: endpoint@3 {
1134 remote-endpoint = <&lvds0_mux_1>;
1137 ipu1_di1_lvds1: endpoint@4 {
1138 remote-endpoint = <&lvds1_mux_1>;