arch/arm/boot/dts/imx6qdl.dtsi

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include "skeleton.dtsi"
  14
  15 / {
  16         aliases {
  17                 can0 = &can1;
  18                 can1 = &can2;
  19                 gpio0 = &gpio1;
  20                 gpio1 = &gpio2;
  21                 gpio2 = &gpio3;
  22                 gpio3 = &gpio4;
  23                 gpio4 = &gpio5;
  24                 gpio5 = &gpio6;
  25                 gpio6 = &gpio7;
  26                 i2c0 = &i2c1;
  27                 i2c1 = &i2c2;
  28                 i2c2 = &i2c3;
  29                 serial0 = &uart1;
  30                 serial1 = &uart2;
  31                 serial2 = &uart3;
  32                 serial3 = &uart4;
  33                 serial4 = &uart5;
  34                 spi0 = &ecspi1;
  35                 spi1 = &ecspi2;
  36                 spi2 = &ecspi3;
  37                 spi3 = &ecspi4;
  38         };
  39
  40         intc: interrupt-controller@00a01000 {
  41                 compatible = "arm,cortex-a9-gic";
  42                 #interrupt-cells = <3>;
  43                 #address-cells = <1>;
  44                 #size-cells = <1>;
  45                 interrupt-controller;
  46                 reg = <0x00a01000 0x1000>,
  47                       <0x00a00100 0x100>;
  48         };
  49
  50         clocks {
  51                 #address-cells = <1>;
  52                 #size-cells = <0>;
  53
  54                 ckil {
  55                         compatible = "fsl,imx-ckil", "fixed-clock";
  56                         clock-frequency = <32768>;
  57                 };
  58
  59                 ckih1 {
  60                         compatible = "fsl,imx-ckih1", "fixed-clock";
  61                         clock-frequency = <0>;
  62                 };
  63
  64                 osc {
  65                         compatible = "fsl,imx-osc", "fixed-clock";
  66                         clock-frequency = <24000000>;
  67                 };
  68         };
  69
  70         soc {
  71                 #address-cells = <1>;
  72                 #size-cells = <1>;
  73                 compatible = "simple-bus";
  74                 interrupt-parent = <&intc>;
  75                 ranges;
  76
  77                 dma_apbh: dma-apbh@00110000 {
  78                         compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
  79                         reg = <0x00110000 0x2000>;
  80                         interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
  81                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
  82                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
  83                                      <0 13 IRQ_TYPE_LEVEL_HIGH>;
  84                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
  85                         #dma-cells = <1>;
  86                         dma-channels = <4>;
  87                         clocks = <&clks 106>;
  88                 };
  89
  90                 gpmi: gpmi-nand@00112000 {
  91                         compatible = "fsl,imx6q-gpmi-nand";
  92                         #address-cells = <1>;
  93                         #size-cells = <1>;
  94                         reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
  95                         reg-names = "gpmi-nand", "bch";
  96                         interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
  97                         interrupt-names = "bch";
  98                         clocks = <&clks 152>, <&clks 153>, <&clks 151>,
  99                                  <&clks 150>, <&clks 149>;
 100                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
 101                                       "gpmi_bch_apb", "per1_bch";
 102                         dmas = <&dma_apbh 0>;
 103                         dma-names = "rx-tx";
 104                         status = "disabled";
 105                 };
 106
 107                 timer@00a00600 {
 108                         compatible = "arm,cortex-a9-twd-timer";
 109                         reg = <0x00a00600 0x20>;
 110                         interrupts = <1 13 0xf01>;
 111                         clocks = <&clks 15>;
 112                 };
 113
 114                 L2: l2-cache@00a02000 {
 115                         compatible = "arm,pl310-cache";
 116                         reg = <0x00a02000 0x1000>;
 117                         interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
 118                         cache-unified;
 119                         cache-level = <2>;
 120                         arm,tag-latency = <4 2 3>;
 121                         arm,data-latency = <4 2 3>;
 122                 };
 123
 124                 pcie: pcie@0x01000000 {
 125                         compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
 126                         reg = <0x01ffc000 0x4000>; /* DBI */
 127                         #address-cells = <3>;
 128                         #size-cells = <2>;
 129                         device_type = "pci";
 130                         ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */
 131                                   0x81000000 0 0          0x01f80000 0 0x00010000 /* downstream I/O */
 132                                   0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
 133                         num-lanes = <1>;
 134                         interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>;
 135                         clocks = <&clks 189>, <&clks 187>, <&clks 206>, <&clks 144>;
 136                         clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi";
 137                         status = "disabled";
 138                 };
 139
 140                 pmu {
 141                         compatible = "arm,cortex-a9-pmu";
 142                         interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
 143                 };
 144
 145                 aips-bus@02000000 { /* AIPS1 */
 146                         compatible = "fsl,aips-bus", "simple-bus";
 147                         #address-cells = <1>;
 148                         #size-cells = <1>;
 149                         reg = <0x02000000 0x100000>;
 150                         ranges;
 151
 152                         spba-bus@02000000 {
 153                                 compatible = "fsl,spba-bus", "simple-bus";
 154                                 #address-cells = <1>;
 155                                 #size-cells = <1>;
 156                                 reg = <0x02000000 0x40000>;
 157                                 ranges;
 158
 159                                 spdif: spdif@02004000 {
 160                                         compatible = "fsl,imx35-spdif";
 161                                         reg = <0x02004000 0x4000>;
 162                                         interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
 163                                         dmas = <&sdma 14 18 0>,
 164                                                <&sdma 15 18 0>;
 165                                         dma-names = "rx", "tx";
 166                                         clocks = <&clks 197>, <&clks 3>,
 167                                                  <&clks 197>, <&clks 107>,
 168                                                  <&clks 0>,   <&clks 118>,
 169                                                  <&clks 0>,  <&clks 139>,
 170                                                  <&clks 0>;
 171                                         clock-names = "core",  "rxtx0",
 172                                                       "rxtx1", "rxtx2",
 173                                                       "rxtx3", "rxtx4",
 174                                                       "rxtx5", "rxtx6",
 175                                                       "rxtx7";
 176                                         status = "disabled";
 177                                 };
 178
 179                                 ecspi1: ecspi@02008000 {
 180                                         #address-cells = <1>;
 181                                         #size-cells = <0>;
 182                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 183                                         reg = <0x02008000 0x4000>;
 184                                         interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 185                                         clocks = <&clks 112>, <&clks 112>;
 186                                         clock-names = "ipg", "per";
 187                                         status = "disabled";
 188                                 };
 189
 190                                 ecspi2: ecspi@0200c000 {
 191                                         #address-cells = <1>;
 192                                         #size-cells = <0>;
 193                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 194                                         reg = <0x0200c000 0x4000>;
 195                                         interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
 196                                         clocks = <&clks 113>, <&clks 113>;
 197                                         clock-names = "ipg", "per";
 198                                         status = "disabled";
 199                                 };
 200
 201                                 ecspi3: ecspi@02010000 {
 202                                         #address-cells = <1>;
 203                                         #size-cells = <0>;
 204                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 205                                         reg = <0x02010000 0x4000>;
 206                                         interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
 207                                         clocks = <&clks 114>, <&clks 114>;
 208                                         clock-names = "ipg", "per";
 209                                         status = "disabled";
 210                                 };
 211
 212                                 ecspi4: ecspi@02014000 {
 213                                         #address-cells = <1>;
 214                                         #size-cells = <0>;
 215                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 216                                         reg = <0x02014000 0x4000>;
 217                                         interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
 218                                         clocks = <&clks 115>, <&clks 115>;
 219                                         clock-names = "ipg", "per";
 220                                         status = "disabled";
 221                                 };
 222
 223                                 uart1: serial@02020000 {
 224                                         compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 225                                         reg = <0x02020000 0x4000>;
 226                                         interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
 227                                         clocks = <&clks 160>, <&clks 161>;
 228                                         clock-names = "ipg", "per";
 229                                         dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
 230                                         dma-names = "rx", "tx";
 231                                         status = "disabled";
 232                                 };
 233
 234                                 esai: esai@02024000 {
 235                                         reg = <0x02024000 0x4000>;
 236                                         interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
 237                                 };
 238
 239                                 ssi1: ssi@02028000 {
 240                                         compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
 241                                         reg = <0x02028000 0x4000>;
 242                                         interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
 243                                         clocks = <&clks 178>;
 244                                         dmas = <&sdma 37 1 0>,
 245                                                <&sdma 38 1 0>;
 246                                         dma-names = "rx", "tx";
 247                                         fsl,fifo-depth = <15>;
 248                                         fsl,ssi-dma-events = <38 37>;
 249                                         status = "disabled";
 250                                 };
 251
 252                                 ssi2: ssi@0202c000 {
 253                                         compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
 254                                         reg = <0x0202c000 0x4000>;
 255                                         interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
 256                                         clocks = <&clks 179>;
 257                                         dmas = <&sdma 41 1 0>,
 258                                                <&sdma 42 1 0>;
 259                                         dma-names = "rx", "tx";
 260                                         fsl,fifo-depth = <15>;
 261                                         fsl,ssi-dma-events = <42 41>;
 262                                         status = "disabled";
 263                                 };
 264
 265                                 ssi3: ssi@02030000 {
 266                                         compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
 267                                         reg = <0x02030000 0x4000>;
 268                                         interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
 269                                         clocks = <&clks 180>;
 270                                         dmas = <&sdma 45 1 0>,
 271                                                <&sdma 46 1 0>;
 272                                         dma-names = "rx", "tx";
 273                                         fsl,fifo-depth = <15>;
 274                                         fsl,ssi-dma-events = <46 45>;
 275                                         status = "disabled";
 276                                 };
 277
 278                                 asrc: asrc@02034000 {
 279                                         reg = <0x02034000 0x4000>;
 280                                         interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
 281                                 };
 282
 283                                 spba@0203c000 {
 284                                         reg = <0x0203c000 0x4000>;
 285                                 };
 286                         };
 287
 288                         vpu: vpu@02040000 {
 289                                 reg = <0x02040000 0x3c000>;
 290                                 interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>,
 291                                              <0 12 IRQ_TYPE_LEVEL_HIGH>;
 292                         };
 293
 294                         aipstz@0207c000 { /* AIPSTZ1 */
 295                                 reg = <0x0207c000 0x4000>;
 296                         };
 297
 298                         pwm1: pwm@02080000 {
 299                                 #pwm-cells = <2>;
 300                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 301                                 reg = <0x02080000 0x4000>;
 302                                 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
 303                                 clocks = <&clks 62>, <&clks 145>;
 304                                 clock-names = "ipg", "per";
 305                         };
 306
 307                         pwm2: pwm@02084000 {
 308                                 #pwm-cells = <2>;
 309                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 310                                 reg = <0x02084000 0x4000>;
 311                                 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
 312                                 clocks = <&clks 62>, <&clks 146>;
 313                                 clock-names = "ipg", "per";
 314                         };
 315
 316                         pwm3: pwm@02088000 {
 317                                 #pwm-cells = <2>;
 318                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 319                                 reg = <0x02088000 0x4000>;
 320                                 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
 321                                 clocks = <&clks 62>, <&clks 147>;
 322                                 clock-names = "ipg", "per";
 323                         };
 324
 325                         pwm4: pwm@0208c000 {
 326                                 #pwm-cells = <2>;
 327                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 328                                 reg = <0x0208c000 0x4000>;
 329                                 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
 330                                 clocks = <&clks 62>, <&clks 148>;
 331                                 clock-names = "ipg", "per";
 332                         };
 333
 334                         can1: flexcan@02090000 {
 335                                 compatible = "fsl,imx6q-flexcan";
 336                                 reg = <0x02090000 0x4000>;
 337                                 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
 338                                 clocks = <&clks 108>, <&clks 109>;
 339                                 clock-names = "ipg", "per";
 340                                 status = "disabled";
 341                         };
 342
 343                         can2: flexcan@02094000 {
 344                                 compatible = "fsl,imx6q-flexcan";
 345                                 reg = <0x02094000 0x4000>;
 346                                 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
 347                                 clocks = <&clks 110>, <&clks 111>;
 348                                 clock-names = "ipg", "per";
 349                                 status = "disabled";
 350                         };
 351
 352                         gpt: gpt@02098000 {
 353                                 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
 354                                 reg = <0x02098000 0x4000>;
 355                                 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
 356                                 clocks = <&clks 119>, <&clks 120>;
 357                                 clock-names = "ipg", "per";
 358                         };
 359
 360                         gpio1: gpio@0209c000 {
 361                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 362                                 reg = <0x0209c000 0x4000>;
 363                                 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
 364                                              <0 67 IRQ_TYPE_LEVEL_HIGH>;
 365                                 gpio-controller;
 366                                 #gpio-cells = <2>;
 367                                 interrupt-controller;
 368                                 #interrupt-cells = <2>;
 369                         };
 370
 371                         gpio2: gpio@020a0000 {
 372                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 373                                 reg = <0x020a0000 0x4000>;
 374                                 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
 375                                              <0 69 IRQ_TYPE_LEVEL_HIGH>;
 376                                 gpio-controller;
 377                                 #gpio-cells = <2>;
 378                                 interrupt-controller;
 379                                 #interrupt-cells = <2>;
 380                         };
 381
 382                         gpio3: gpio@020a4000 {
 383                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 384                                 reg = <0x020a4000 0x4000>;
 385                                 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
 386                                              <0 71 IRQ_TYPE_LEVEL_HIGH>;
 387                                 gpio-controller;
 388                                 #gpio-cells = <2>;
 389                                 interrupt-controller;
 390                                 #interrupt-cells = <2>;
 391                         };
 392
 393                         gpio4: gpio@020a8000 {
 394                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 395                                 reg = <0x020a8000 0x4000>;
 396                                 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
 397                                              <0 73 IRQ_TYPE_LEVEL_HIGH>;
 398                                 gpio-controller;
 399                                 #gpio-cells = <2>;
 400                                 interrupt-controller;
 401                                 #interrupt-cells = <2>;
 402                         };
 403
 404                         gpio5: gpio@020ac000 {
 405                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 406                                 reg = <0x020ac000 0x4000>;
 407                                 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
 408                                              <0 75 IRQ_TYPE_LEVEL_HIGH>;
 409                                 gpio-controller;
 410                                 #gpio-cells = <2>;
 411                                 interrupt-controller;
 412                                 #interrupt-cells = <2>;
 413                         };
 414
 415                         gpio6: gpio@020b0000 {
 416                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 417                                 reg = <0x020b0000 0x4000>;
 418                                 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
 419                                              <0 77 IRQ_TYPE_LEVEL_HIGH>;
 420                                 gpio-controller;
 421                                 #gpio-cells = <2>;
 422                                 interrupt-controller;
 423                                 #interrupt-cells = <2>;
 424                         };
 425
 426                         gpio7: gpio@020b4000 {
 427                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 428                                 reg = <0x020b4000 0x4000>;
 429                                 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
 430                                              <0 79 IRQ_TYPE_LEVEL_HIGH>;
 431                                 gpio-controller;
 432                                 #gpio-cells = <2>;
 433                                 interrupt-controller;
 434                                 #interrupt-cells = <2>;
 435                         };
 436
 437                         kpp: kpp@020b8000 {
 438                                 reg = <0x020b8000 0x4000>;
 439                                 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
 440                         };
 441
 442                         wdog1: wdog@020bc000 {
 443                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 444                                 reg = <0x020bc000 0x4000>;
 445                                 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
 446                                 clocks = <&clks 0>;
 447                         };
 448
 449                         wdog2: wdog@020c0000 {
 450                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 451                                 reg = <0x020c0000 0x4000>;
 452                                 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
 453                                 clocks = <&clks 0>;
 454                                 status = "disabled";
 455                         };
 456
 457                         clks: ccm@020c4000 {
 458                                 compatible = "fsl,imx6q-ccm";
 459                                 reg = <0x020c4000 0x4000>;
 460                                 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
 461                                              <0 88 IRQ_TYPE_LEVEL_HIGH>;
 462                                 #clock-cells = <1>;
 463                         };
 464
 465                         anatop: anatop@020c8000 {
 466                                 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
 467                                 reg = <0x020c8000 0x1000>;
 468                                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
 469                                              <0 54 IRQ_TYPE_LEVEL_HIGH>,
 470                                              <0 127 IRQ_TYPE_LEVEL_HIGH>;
 471
 472                                 regulator-1p1@110 {
 473                                         compatible = "fsl,anatop-regulator";
 474                                         regulator-name = "vdd1p1";
 475                                         regulator-min-microvolt = <800000>;
 476                                         regulator-max-microvolt = <1375000>;
 477                                         regulator-always-on;
 478                                         anatop-reg-offset = <0x110>;
 479                                         anatop-vol-bit-shift = <8>;
 480                                         anatop-vol-bit-width = <5>;
 481                                         anatop-min-bit-val = <4>;
 482                                         anatop-min-voltage = <800000>;
 483                                         anatop-max-voltage = <1375000>;
 484                                 };
 485
 486                                 regulator-3p0@120 {
 487                                         compatible = "fsl,anatop-regulator";
 488                                         regulator-name = "vdd3p0";
 489                                         regulator-min-microvolt = <2800000>;
 490                                         regulator-max-microvolt = <3150000>;
 491                                         regulator-always-on;
 492                                         anatop-reg-offset = <0x120>;
 493                                         anatop-vol-bit-shift = <8>;
 494                                         anatop-vol-bit-width = <5>;
 495                                         anatop-min-bit-val = <0>;
 496                                         anatop-min-voltage = <2625000>;
 497                                         anatop-max-voltage = <3400000>;
 498                                 };
 499
 500                                 regulator-2p5@130 {
 501                                         compatible = "fsl,anatop-regulator";
 502                                         regulator-name = "vdd2p5";
 503                                         regulator-min-microvolt = <2000000>;
 504                                         regulator-max-microvolt = <2750000>;
 505                                         regulator-always-on;
 506                                         anatop-reg-offset = <0x130>;
 507                                         anatop-vol-bit-shift = <8>;
 508                                         anatop-vol-bit-width = <5>;
 509                                         anatop-min-bit-val = <0>;
 510                                         anatop-min-voltage = <2000000>;
 511                                         anatop-max-voltage = <2750000>;
 512                                 };
 513
 514                                 reg_arm: regulator-vddcore@140 {
 515                                         compatible = "fsl,anatop-regulator";
 516                                         regulator-name = "vddarm";
 517                                         regulator-min-microvolt = <725000>;
 518                                         regulator-max-microvolt = <1450000>;
 519                                         regulator-always-on;
 520                                         anatop-reg-offset = <0x140>;
 521                                         anatop-vol-bit-shift = <0>;
 522                                         anatop-vol-bit-width = <5>;
 523                                         anatop-delay-reg-offset = <0x170>;
 524                                         anatop-delay-bit-shift = <24>;
 525                                         anatop-delay-bit-width = <2>;
 526                                         anatop-min-bit-val = <1>;
 527                                         anatop-min-voltage = <725000>;
 528                                         anatop-max-voltage = <1450000>;
 529                                 };
 530
 531                                 reg_pu: regulator-vddpu@140 {
 532                                         compatible = "fsl,anatop-regulator";
 533                                         regulator-name = "vddpu";
 534                                         regulator-min-microvolt = <725000>;
 535                                         regulator-max-microvolt = <1450000>;
 536                                         regulator-always-on;
 537                                         anatop-reg-offset = <0x140>;
 538                                         anatop-vol-bit-shift = <9>;
 539                                         anatop-vol-bit-width = <5>;
 540                                         anatop-delay-reg-offset = <0x170>;
 541                                         anatop-delay-bit-shift = <26>;
 542                                         anatop-delay-bit-width = <2>;
 543                                         anatop-min-bit-val = <1>;
 544                                         anatop-min-voltage = <725000>;
 545                                         anatop-max-voltage = <1450000>;
 546                                 };
 547
 548                                 reg_soc: regulator-vddsoc@140 {
 549                                         compatible = "fsl,anatop-regulator";
 550                                         regulator-name = "vddsoc";
 551                                         regulator-min-microvolt = <725000>;
 552                                         regulator-max-microvolt = <1450000>;
 553                                         regulator-always-on;
 554                                         anatop-reg-offset = <0x140>;
 555                                         anatop-vol-bit-shift = <18>;
 556                                         anatop-vol-bit-width = <5>;
 557                                         anatop-delay-reg-offset = <0x170>;
 558                                         anatop-delay-bit-shift = <28>;
 559                                         anatop-delay-bit-width = <2>;
 560                                         anatop-min-bit-val = <1>;
 561                                         anatop-min-voltage = <725000>;
 562                                         anatop-max-voltage = <1450000>;
 563                                 };
 564                         };
 565
 566                         tempmon: tempmon {
 567                                 compatible = "fsl,imx6q-tempmon";
 568                                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
 569                                 fsl,tempmon = <&anatop>;
 570                                 fsl,tempmon-data = <&ocotp>;
 571                                 clocks = <&clks 172>;
 572                         };
 573
 574                         usbphy1: usbphy@020c9000 {
 575                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 576                                 reg = <0x020c9000 0x1000>;
 577                                 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
 578                                 clocks = <&clks 182>;
 579                                 fsl,anatop = <&anatop>;
 580                         };
 581
 582                         usbphy2: usbphy@020ca000 {
 583                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 584                                 reg = <0x020ca000 0x1000>;
 585                                 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
 586                                 clocks = <&clks 183>;
 587                                 fsl,anatop = <&anatop>;
 588                         };
 589
 590                         snvs@020cc000 {
 591                                 compatible = "fsl,sec-v4.0-mon", "simple-bus";
 592                                 #address-cells = <1>;
 593                                 #size-cells = <1>;
 594                                 ranges = <0 0x020cc000 0x4000>;
 595
 596                                 snvs-rtc-lp@34 {
 597                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 598                                         reg = <0x34 0x58>;
 599                                         interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
 600                                                      <0 20 IRQ_TYPE_LEVEL_HIGH>;
 601                                 };
 602                         };
 603
 604                         epit1: epit@020d0000 { /* EPIT1 */
 605                                 reg = <0x020d0000 0x4000>;
 606                                 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
 607                         };
 608
 609                         epit2: epit@020d4000 { /* EPIT2 */
 610                                 reg = <0x020d4000 0x4000>;
 611                                 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
 612                         };
 613
 614                         src: src@020d8000 {
 615                                 compatible = "fsl,imx6q-src", "fsl,imx51-src";
 616                                 reg = <0x020d8000 0x4000>;
 617                                 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
 618                                              <0 96 IRQ_TYPE_LEVEL_HIGH>;
 619                                 #reset-cells = <1>;
 620                         };
 621
 622                         gpc: gpc@020dc000 {
 623                                 compatible = "fsl,imx6q-gpc";
 624                                 reg = <0x020dc000 0x4000>;
 625                                 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
 626                                              <0 90 IRQ_TYPE_LEVEL_HIGH>;
 627                         };
 628
 629                         gpr: iomuxc-gpr@020e0000 {
 630                                 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
 631                                 reg = <0x020e0000 0x38>;
 632                         };
 633
 634                         iomuxc: iomuxc@020e0000 {
 635                                 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
 636                                 reg = <0x020e0000 0x4000>;
 637                         };
 638
 639                         ldb: ldb@020e0008 {
 640                                 #address-cells = <1>;
 641                                 #size-cells = <0>;
 642                                 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
 643                                 gpr = <&gpr>;
 644                                 status = "disabled";
 645
 646                                 lvds-channel@0 {
 647                                         reg = <0>;
 648                                         status = "disabled";
 649                                 };
 650
 651                                 lvds-channel@1 {
 652                                         reg = <1>;
 653                                         status = "disabled";
 654                                 };
 655                         };
 656
 657                         dcic1: dcic@020e4000 {
 658                                 reg = <0x020e4000 0x4000>;
 659                                 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
 660                         };
 661
 662                         dcic2: dcic@020e8000 {
 663                                 reg = <0x020e8000 0x4000>;
 664                                 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
 665                         };
 666
 667                         sdma: sdma@020ec000 {
 668                                 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
 669                                 reg = <0x020ec000 0x4000>;
 670                                 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
 671                                 clocks = <&clks 155>, <&clks 155>;
 672                                 clock-names = "ipg", "ahb";
 673                                 #dma-cells = <3>;
 674                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 675                         };
 676                 };
 677
 678                 aips-bus@02100000 { /* AIPS2 */
 679                         compatible = "fsl,aips-bus", "simple-bus";
 680                         #address-cells = <1>;
 681                         #size-cells = <1>;
 682                         reg = <0x02100000 0x100000>;
 683                         ranges;
 684
 685                         caam@02100000 {
 686                                 reg = <0x02100000 0x40000>;
 687                                 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>,
 688                                              <0 106 IRQ_TYPE_LEVEL_HIGH>;
 689                         };
 690
 691                         aipstz@0217c000 { /* AIPSTZ2 */
 692                                 reg = <0x0217c000 0x4000>;
 693                         };
 694
 695                         usbotg: usb@02184000 {
 696                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 697                                 reg = <0x02184000 0x200>;
 698                                 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
 699                                 clocks = <&clks 162>;
 700                                 fsl,usbphy = <&usbphy1>;
 701                                 fsl,usbmisc = <&usbmisc 0>;
 702                                 status = "disabled";
 703                         };
 704
 705                         usbh1: usb@02184200 {
 706                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 707                                 reg = <0x02184200 0x200>;
 708                                 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
 709                                 clocks = <&clks 162>;
 710                                 fsl,usbphy = <&usbphy2>;
 711                                 fsl,usbmisc = <&usbmisc 1>;
 712                                 status = "disabled";
 713                         };
 714
 715                         usbh2: usb@02184400 {
 716                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 717                                 reg = <0x02184400 0x200>;
 718                                 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
 719                                 clocks = <&clks 162>;
 720                                 fsl,usbmisc = <&usbmisc 2>;
 721                                 status = "disabled";
 722                         };
 723
 724                         usbh3: usb@02184600 {
 725                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 726                                 reg = <0x02184600 0x200>;
 727                                 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
 728                                 clocks = <&clks 162>;
 729                                 fsl,usbmisc = <&usbmisc 3>;
 730                                 status = "disabled";
 731                         };
 732
 733                         usbmisc: usbmisc@02184800 {
 734                                 #index-cells = <1>;
 735                                 compatible = "fsl,imx6q-usbmisc";
 736                                 reg = <0x02184800 0x200>;
 737                                 clocks = <&clks 162>;
 738                         };
 739
 740                         fec: ethernet@02188000 {
 741                                 compatible = "fsl,imx6q-fec";
 742                                 reg = <0x02188000 0x4000>;
 743                                 interrupts-extended =
 744                                         <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
 745                                         <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
 746                                 clocks = <&clks 117>, <&clks 117>, <&clks 190>;
 747                                 clock-names = "ipg", "ahb", "ptp";
 748                                 status = "disabled";
 749                         };
 750
 751                         mlb@0218c000 {
 752                                 reg = <0x0218c000 0x4000>;
 753                                 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
 754                                              <0 117 IRQ_TYPE_LEVEL_HIGH>,
 755                                              <0 126 IRQ_TYPE_LEVEL_HIGH>;
 756                         };
 757
 758                         usdhc1: usdhc@02190000 {
 759                                 compatible = "fsl,imx6q-usdhc";
 760                                 reg = <0x02190000 0x4000>;
 761                                 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 762                                 clocks = <&clks 163>, <&clks 163>, <&clks 163>;
 763                                 clock-names = "ipg", "ahb", "per";
 764                                 bus-width = <4>;
 765                                 status = "disabled";
 766                         };
 767
 768                         usdhc2: usdhc@02194000 {
 769                                 compatible = "fsl,imx6q-usdhc";
 770                                 reg = <0x02194000 0x4000>;
 771                                 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 772                                 clocks = <&clks 164>, <&clks 164>, <&clks 164>;
 773                                 clock-names = "ipg", "ahb", "per";
 774                                 bus-width = <4>;
 775                                 status = "disabled";
 776                         };
 777
 778                         usdhc3: usdhc@02198000 {
 779                                 compatible = "fsl,imx6q-usdhc";
 780                                 reg = <0x02198000 0x4000>;
 781                                 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
 782                                 clocks = <&clks 165>, <&clks 165>, <&clks 165>;
 783                                 clock-names = "ipg", "ahb", "per";
 784                                 bus-width = <4>;
 785                                 status = "disabled";
 786                         };
 787
 788                         usdhc4: usdhc@0219c000 {
 789                                 compatible = "fsl,imx6q-usdhc";
 790                                 reg = <0x0219c000 0x4000>;
 791                                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 792                                 clocks = <&clks 166>, <&clks 166>, <&clks 166>;
 793                                 clock-names = "ipg", "ahb", "per";
 794                                 bus-width = <4>;
 795                                 status = "disabled";
 796                         };
 797
 798                         i2c1: i2c@021a0000 {
 799                                 #address-cells = <1>;
 800                                 #size-cells = <0>;
 801                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 802                                 reg = <0x021a0000 0x4000>;
 803                                 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
 804                                 clocks = <&clks 125>;
 805                                 status = "disabled";
 806                         };
 807
 808                         i2c2: i2c@021a4000 {
 809                                 #address-cells = <1>;
 810                                 #size-cells = <0>;
 811                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 812                                 reg = <0x021a4000 0x4000>;
 813                                 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
 814                                 clocks = <&clks 126>;
 815                                 status = "disabled";
 816                         };
 817
 818                         i2c3: i2c@021a8000 {
 819                                 #address-cells = <1>;
 820                                 #size-cells = <0>;
 821                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 822                                 reg = <0x021a8000 0x4000>;
 823                                 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
 824                                 clocks = <&clks 127>;
 825                                 status = "disabled";
 826                         };
 827
 828                         romcp@021ac000 {
 829                                 reg = <0x021ac000 0x4000>;
 830                         };
 831
 832                         mmdc0: mmdc@021b0000 { /* MMDC0 */
 833                                 compatible = "fsl,imx6q-mmdc";
 834                                 reg = <0x021b0000 0x4000>;
 835                         };
 836
 837                         mmdc1: mmdc@021b4000 { /* MMDC1 */
 838                                 reg = <0x021b4000 0x4000>;
 839                         };
 840
 841                         weim: weim@021b8000 {
 842                                 compatible = "fsl,imx6q-weim";
 843                                 reg = <0x021b8000 0x4000>;
 844                                 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
 845                                 clocks = <&clks 196>;
 846                         };
 847
 848                         ocotp: ocotp@021bc000 {
 849                                 compatible = "fsl,imx6q-ocotp", "syscon";
 850                                 reg = <0x021bc000 0x4000>;
 851                         };
 852
 853                         tzasc@021d0000 { /* TZASC1 */
 854                                 reg = <0x021d0000 0x4000>;
 855                                 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
 856                         };
 857
 858                         tzasc@021d4000 { /* TZASC2 */
 859                                 reg = <0x021d4000 0x4000>;
 860                                 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
 861                         };
 862
 863                         audmux: audmux@021d8000 {
 864                                 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
 865                                 reg = <0x021d8000 0x4000>;
 866                                 status = "disabled";
 867                         };
 868
 869                         mipi_csi: mipi@021dc000 {
 870                                 reg = <0x021dc000 0x4000>;
 871                         };
 872
 873                         mipi@021e0000 { /* MIPI-DSI */
 874                                 reg = <0x021e0000 0x4000>;
 875                         };
 876
 877                         vdoa@021e4000 {
 878                                 reg = <0x021e4000 0x4000>;
 879                                 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
 880                         };
 881
 882                         uart2: serial@021e8000 {
 883                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 884                                 reg = <0x021e8000 0x4000>;
 885                                 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
 886                                 clocks = <&clks 160>, <&clks 161>;
 887                                 clock-names = "ipg", "per";
 888                                 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
 889                                 dma-names = "rx", "tx";
 890                                 status = "disabled";
 891                         };
 892
 893                         uart3: serial@021ec000 {
 894                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 895                                 reg = <0x021ec000 0x4000>;
 896                                 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
 897                                 clocks = <&clks 160>, <&clks 161>;
 898                                 clock-names = "ipg", "per";
 899                                 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
 900                                 dma-names = "rx", "tx";
 901                                 status = "disabled";
 902                         };
 903
 904                         uart4: serial@021f0000 {
 905                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 906                                 reg = <0x021f0000 0x4000>;
 907                                 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
 908                                 clocks = <&clks 160>, <&clks 161>;
 909                                 clock-names = "ipg", "per";
 910                                 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
 911                                 dma-names = "rx", "tx";
 912                                 status = "disabled";
 913                         };
 914
 915                         uart5: serial@021f4000 {
 916                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 917                                 reg = <0x021f4000 0x4000>;
 918                                 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
 919                                 clocks = <&clks 160>, <&clks 161>;
 920                                 clock-names = "ipg", "per";
 921                                 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
 922                                 dma-names = "rx", "tx";
 923                                 status = "disabled";
 924                         };
 925                 };
 926
 927                 ipu1: ipu@02400000 {
 928                         #crtc-cells = <1>;
 929                         compatible = "fsl,imx6q-ipu";
 930                         reg = <0x02400000 0x400000>;
 931                         interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
 932                                      <0 5 IRQ_TYPE_LEVEL_HIGH>;
 933                         clocks = <&clks 130>, <&clks 131>, <&clks 132>;
 934                         clock-names = "bus", "di0", "di1";
 935                         resets = <&src 2>;
 936                 };
 937         };
 938 };