2 * Copyright 2013 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include "skeleton.dtsi"
12 #include "imx6sl-pinfunc.h"
13 #include <dt-bindings/clock/imx6sl-clock.h>
41 compatible = "arm,cortex-a9";
44 next-level-cache = <&L2>;
51 fsl,soc-operating-points = <
52 /* ARM kHz SOC-PU uV */
57 clock-latency = <61036>; /* two CLK32 periods */
58 clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
59 <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
60 <&clks IMX6SL_CLK_PLL1_SYS>;
61 clock-names = "arm", "pll2_pfd2_396m", "step",
62 "pll1_sw", "pll1_sys";
63 arm-supply = <®_arm>;
64 pu-supply = <®_pu>;
65 soc-supply = <®_soc>;
69 intc: interrupt-controller@00a01000 {
70 compatible = "arm,cortex-a9-gic";
71 #interrupt-cells = <3>;
73 reg = <0x00a01000 0x1000>,
82 compatible = "fixed-clock";
84 clock-frequency = <32768>;
88 compatible = "fixed-clock";
90 clock-frequency = <24000000>;
97 compatible = "simple-bus";
98 interrupt-parent = <&intc>;
101 ocram: sram@00900000 {
102 compatible = "mmio-sram";
103 reg = <0x00900000 0x20000>;
104 clocks = <&clks IMX6SL_CLK_OCRAM>;
107 L2: l2-cache@00a02000 {
108 compatible = "arm,pl310-cache";
109 reg = <0x00a02000 0x1000>;
110 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
113 arm,tag-latency = <4 2 3>;
114 arm,data-latency = <4 2 3>;
118 compatible = "arm,cortex-a9-pmu";
119 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
122 aips1: aips-bus@02000000 {
123 compatible = "fsl,aips-bus", "simple-bus";
124 #address-cells = <1>;
126 reg = <0x02000000 0x100000>;
129 spba: spba-bus@02000000 {
130 compatible = "fsl,spba-bus", "simple-bus";
131 #address-cells = <1>;
133 reg = <0x02000000 0x40000>;
136 spdif: spdif@02004000 {
137 reg = <0x02004000 0x4000>;
138 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
141 ecspi1: ecspi@02008000 {
142 #address-cells = <1>;
144 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
145 reg = <0x02008000 0x4000>;
146 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
147 clocks = <&clks IMX6SL_CLK_ECSPI1>,
148 <&clks IMX6SL_CLK_ECSPI1>;
149 clock-names = "ipg", "per";
153 ecspi2: ecspi@0200c000 {
154 #address-cells = <1>;
156 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
157 reg = <0x0200c000 0x4000>;
158 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
159 clocks = <&clks IMX6SL_CLK_ECSPI2>,
160 <&clks IMX6SL_CLK_ECSPI2>;
161 clock-names = "ipg", "per";
165 ecspi3: ecspi@02010000 {
166 #address-cells = <1>;
168 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
169 reg = <0x02010000 0x4000>;
170 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
171 clocks = <&clks IMX6SL_CLK_ECSPI3>,
172 <&clks IMX6SL_CLK_ECSPI3>;
173 clock-names = "ipg", "per";
177 ecspi4: ecspi@02014000 {
178 #address-cells = <1>;
180 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
181 reg = <0x02014000 0x4000>;
182 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
183 clocks = <&clks IMX6SL_CLK_ECSPI4>,
184 <&clks IMX6SL_CLK_ECSPI4>;
185 clock-names = "ipg", "per";
189 uart5: serial@02018000 {
190 compatible = "fsl,imx6sl-uart",
191 "fsl,imx6q-uart", "fsl,imx21-uart";
192 reg = <0x02018000 0x4000>;
193 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
194 clocks = <&clks IMX6SL_CLK_UART>,
195 <&clks IMX6SL_CLK_UART_SERIAL>;
196 clock-names = "ipg", "per";
197 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
198 dma-names = "rx", "tx";
202 uart1: serial@02020000 {
203 compatible = "fsl,imx6sl-uart",
204 "fsl,imx6q-uart", "fsl,imx21-uart";
205 reg = <0x02020000 0x4000>;
206 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
207 clocks = <&clks IMX6SL_CLK_UART>,
208 <&clks IMX6SL_CLK_UART_SERIAL>;
209 clock-names = "ipg", "per";
210 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
211 dma-names = "rx", "tx";
215 uart2: serial@02024000 {
216 compatible = "fsl,imx6sl-uart",
217 "fsl,imx6q-uart", "fsl,imx21-uart";
218 reg = <0x02024000 0x4000>;
219 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
220 clocks = <&clks IMX6SL_CLK_UART>,
221 <&clks IMX6SL_CLK_UART_SERIAL>;
222 clock-names = "ipg", "per";
223 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
224 dma-names = "rx", "tx";
229 compatible = "fsl,imx6sl-ssi",
232 reg = <0x02028000 0x4000>;
233 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
234 clocks = <&clks IMX6SL_CLK_SSI1>;
235 dmas = <&sdma 37 1 0>,
237 dma-names = "rx", "tx";
238 fsl,fifo-depth = <15>;
243 compatible = "fsl,imx6sl-ssi",
246 reg = <0x0202c000 0x4000>;
247 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
248 clocks = <&clks IMX6SL_CLK_SSI2>;
249 dmas = <&sdma 41 1 0>,
251 dma-names = "rx", "tx";
252 fsl,fifo-depth = <15>;
257 compatible = "fsl,imx6sl-ssi",
260 reg = <0x02030000 0x4000>;
261 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
262 clocks = <&clks IMX6SL_CLK_SSI3>;
263 dmas = <&sdma 45 1 0>,
265 dma-names = "rx", "tx";
266 fsl,fifo-depth = <15>;
270 uart3: serial@02034000 {
271 compatible = "fsl,imx6sl-uart",
272 "fsl,imx6q-uart", "fsl,imx21-uart";
273 reg = <0x02034000 0x4000>;
274 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
275 clocks = <&clks IMX6SL_CLK_UART>,
276 <&clks IMX6SL_CLK_UART_SERIAL>;
277 clock-names = "ipg", "per";
278 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
279 dma-names = "rx", "tx";
283 uart4: serial@02038000 {
284 compatible = "fsl,imx6sl-uart",
285 "fsl,imx6q-uart", "fsl,imx21-uart";
286 reg = <0x02038000 0x4000>;
287 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
288 clocks = <&clks IMX6SL_CLK_UART>,
289 <&clks IMX6SL_CLK_UART_SERIAL>;
290 clock-names = "ipg", "per";
291 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
292 dma-names = "rx", "tx";
299 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
300 reg = <0x02080000 0x4000>;
301 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
302 clocks = <&clks IMX6SL_CLK_PWM1>,
303 <&clks IMX6SL_CLK_PWM1>;
304 clock-names = "ipg", "per";
309 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
310 reg = <0x02084000 0x4000>;
311 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
312 clocks = <&clks IMX6SL_CLK_PWM2>,
313 <&clks IMX6SL_CLK_PWM2>;
314 clock-names = "ipg", "per";
319 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
320 reg = <0x02088000 0x4000>;
321 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
322 clocks = <&clks IMX6SL_CLK_PWM3>,
323 <&clks IMX6SL_CLK_PWM3>;
324 clock-names = "ipg", "per";
329 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
330 reg = <0x0208c000 0x4000>;
331 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
332 clocks = <&clks IMX6SL_CLK_PWM4>,
333 <&clks IMX6SL_CLK_PWM4>;
334 clock-names = "ipg", "per";
338 compatible = "fsl,imx6sl-gpt";
339 reg = <0x02098000 0x4000>;
340 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
341 clocks = <&clks IMX6SL_CLK_GPT>,
342 <&clks IMX6SL_CLK_GPT_SERIAL>;
343 clock-names = "ipg", "per";
346 gpio1: gpio@0209c000 {
347 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
348 reg = <0x0209c000 0x4000>;
349 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
350 <0 67 IRQ_TYPE_LEVEL_HIGH>;
353 interrupt-controller;
354 #interrupt-cells = <2>;
357 gpio2: gpio@020a0000 {
358 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
359 reg = <0x020a0000 0x4000>;
360 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
361 <0 69 IRQ_TYPE_LEVEL_HIGH>;
364 interrupt-controller;
365 #interrupt-cells = <2>;
368 gpio3: gpio@020a4000 {
369 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
370 reg = <0x020a4000 0x4000>;
371 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
372 <0 71 IRQ_TYPE_LEVEL_HIGH>;
375 interrupt-controller;
376 #interrupt-cells = <2>;
379 gpio4: gpio@020a8000 {
380 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
381 reg = <0x020a8000 0x4000>;
382 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
383 <0 73 IRQ_TYPE_LEVEL_HIGH>;
386 interrupt-controller;
387 #interrupt-cells = <2>;
390 gpio5: gpio@020ac000 {
391 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
392 reg = <0x020ac000 0x4000>;
393 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
394 <0 75 IRQ_TYPE_LEVEL_HIGH>;
397 interrupt-controller;
398 #interrupt-cells = <2>;
402 compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp";
403 reg = <0x020b8000 0x4000>;
404 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
405 clocks = <&clks IMX6SL_CLK_DUMMY>;
408 wdog1: wdog@020bc000 {
409 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
410 reg = <0x020bc000 0x4000>;
411 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
412 clocks = <&clks IMX6SL_CLK_DUMMY>;
415 wdog2: wdog@020c0000 {
416 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
417 reg = <0x020c0000 0x4000>;
418 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
419 clocks = <&clks IMX6SL_CLK_DUMMY>;
424 compatible = "fsl,imx6sl-ccm";
425 reg = <0x020c4000 0x4000>;
426 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
427 <0 88 IRQ_TYPE_LEVEL_HIGH>;
431 anatop: anatop@020c8000 {
432 compatible = "fsl,imx6sl-anatop",
434 "syscon", "simple-bus";
435 reg = <0x020c8000 0x1000>;
436 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
437 <0 54 IRQ_TYPE_LEVEL_HIGH>,
438 <0 127 IRQ_TYPE_LEVEL_HIGH>;
441 compatible = "fsl,anatop-regulator";
442 regulator-name = "vdd1p1";
443 regulator-min-microvolt = <800000>;
444 regulator-max-microvolt = <1375000>;
446 anatop-reg-offset = <0x110>;
447 anatop-vol-bit-shift = <8>;
448 anatop-vol-bit-width = <5>;
449 anatop-min-bit-val = <4>;
450 anatop-min-voltage = <800000>;
451 anatop-max-voltage = <1375000>;
455 compatible = "fsl,anatop-regulator";
456 regulator-name = "vdd3p0";
457 regulator-min-microvolt = <2800000>;
458 regulator-max-microvolt = <3150000>;
460 anatop-reg-offset = <0x120>;
461 anatop-vol-bit-shift = <8>;
462 anatop-vol-bit-width = <5>;
463 anatop-min-bit-val = <0>;
464 anatop-min-voltage = <2625000>;
465 anatop-max-voltage = <3400000>;
469 compatible = "fsl,anatop-regulator";
470 regulator-name = "vdd2p5";
471 regulator-min-microvolt = <2100000>;
472 regulator-max-microvolt = <2850000>;
474 anatop-reg-offset = <0x130>;
475 anatop-vol-bit-shift = <8>;
476 anatop-vol-bit-width = <5>;
477 anatop-min-bit-val = <0>;
478 anatop-min-voltage = <2100000>;
479 anatop-max-voltage = <2850000>;
482 reg_arm: regulator-vddcore@140 {
483 compatible = "fsl,anatop-regulator";
484 regulator-name = "vddarm";
485 regulator-min-microvolt = <725000>;
486 regulator-max-microvolt = <1450000>;
488 anatop-reg-offset = <0x140>;
489 anatop-vol-bit-shift = <0>;
490 anatop-vol-bit-width = <5>;
491 anatop-delay-reg-offset = <0x170>;
492 anatop-delay-bit-shift = <24>;
493 anatop-delay-bit-width = <2>;
494 anatop-min-bit-val = <1>;
495 anatop-min-voltage = <725000>;
496 anatop-max-voltage = <1450000>;
499 reg_pu: regulator-vddpu@140 {
500 compatible = "fsl,anatop-regulator";
501 regulator-name = "vddpu";
502 regulator-min-microvolt = <725000>;
503 regulator-max-microvolt = <1450000>;
505 anatop-reg-offset = <0x140>;
506 anatop-vol-bit-shift = <9>;
507 anatop-vol-bit-width = <5>;
508 anatop-delay-reg-offset = <0x170>;
509 anatop-delay-bit-shift = <26>;
510 anatop-delay-bit-width = <2>;
511 anatop-min-bit-val = <1>;
512 anatop-min-voltage = <725000>;
513 anatop-max-voltage = <1450000>;
516 reg_soc: regulator-vddsoc@140 {
517 compatible = "fsl,anatop-regulator";
518 regulator-name = "vddsoc";
519 regulator-min-microvolt = <725000>;
520 regulator-max-microvolt = <1450000>;
522 anatop-reg-offset = <0x140>;
523 anatop-vol-bit-shift = <18>;
524 anatop-vol-bit-width = <5>;
525 anatop-delay-reg-offset = <0x170>;
526 anatop-delay-bit-shift = <28>;
527 anatop-delay-bit-width = <2>;
528 anatop-min-bit-val = <1>;
529 anatop-min-voltage = <725000>;
530 anatop-max-voltage = <1450000>;
534 usbphy1: usbphy@020c9000 {
535 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
536 reg = <0x020c9000 0x1000>;
537 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
538 clocks = <&clks IMX6SL_CLK_USBPHY1>;
539 fsl,anatop = <&anatop>;
542 usbphy2: usbphy@020ca000 {
543 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
544 reg = <0x020ca000 0x1000>;
545 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
546 clocks = <&clks IMX6SL_CLK_USBPHY2>;
547 fsl,anatop = <&anatop>;
551 compatible = "fsl,sec-v4.0-mon", "simple-bus";
552 #address-cells = <1>;
554 ranges = <0 0x020cc000 0x4000>;
557 compatible = "fsl,sec-v4.0-mon-rtc-lp";
559 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
560 <0 20 IRQ_TYPE_LEVEL_HIGH>;
564 epit1: epit@020d0000 {
565 reg = <0x020d0000 0x4000>;
566 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
569 epit2: epit@020d4000 {
570 reg = <0x020d4000 0x4000>;
571 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
575 compatible = "fsl,imx6sl-src", "fsl,imx51-src";
576 reg = <0x020d8000 0x4000>;
577 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
578 <0 96 IRQ_TYPE_LEVEL_HIGH>;
583 compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
584 reg = <0x020dc000 0x4000>;
585 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
588 gpr: iomuxc-gpr@020e0000 {
589 compatible = "fsl,imx6sl-iomuxc-gpr",
590 "fsl,imx6q-iomuxc-gpr", "syscon";
591 reg = <0x020e0000 0x38>;
594 iomuxc: iomuxc@020e0000 {
595 compatible = "fsl,imx6sl-iomuxc";
596 reg = <0x020e0000 0x4000>;
600 reg = <0x020e4000 0x4000>;
601 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
604 spdc: spdc@020e8000 {
605 reg = <0x020e8000 0x4000>;
606 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
609 sdma: sdma@020ec000 {
610 compatible = "fsl,imx6sl-sdma", "fsl,imx35-sdma";
611 reg = <0x020ec000 0x4000>;
612 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
613 clocks = <&clks IMX6SL_CLK_SDMA>,
614 <&clks IMX6SL_CLK_SDMA>;
615 clock-names = "ipg", "ahb";
617 /* imx6sl reuses imx6q sdma firmware */
618 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
622 reg = <0x020f0000 0x4000>;
623 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
626 epdc: epdc@020f4000 {
627 reg = <0x020f4000 0x4000>;
628 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
631 lcdif: lcdif@020f8000 {
632 reg = <0x020f8000 0x4000>;
633 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
637 reg = <0x020fc000 0x4000>;
638 interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>;
642 aips2: aips-bus@02100000 {
643 compatible = "fsl,aips-bus", "simple-bus";
644 #address-cells = <1>;
646 reg = <0x02100000 0x100000>;
649 usbotg1: usb@02184000 {
650 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
651 reg = <0x02184000 0x200>;
652 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
653 clocks = <&clks IMX6SL_CLK_USBOH3>;
654 fsl,usbphy = <&usbphy1>;
655 fsl,usbmisc = <&usbmisc 0>;
659 usbotg2: usb@02184200 {
660 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
661 reg = <0x02184200 0x200>;
662 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
663 clocks = <&clks IMX6SL_CLK_USBOH3>;
664 fsl,usbphy = <&usbphy2>;
665 fsl,usbmisc = <&usbmisc 1>;
670 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
671 reg = <0x02184400 0x200>;
672 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
673 clocks = <&clks IMX6SL_CLK_USBOH3>;
674 fsl,usbmisc = <&usbmisc 2>;
678 usbmisc: usbmisc@02184800 {
680 compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
681 reg = <0x02184800 0x200>;
682 clocks = <&clks IMX6SL_CLK_USBOH3>;
685 fec: ethernet@02188000 {
686 compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
687 reg = <0x02188000 0x4000>;
688 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
689 clocks = <&clks IMX6SL_CLK_ENET>,
690 <&clks IMX6SL_CLK_ENET_REF>;
691 clock-names = "ipg", "ahb";
695 usdhc1: usdhc@02190000 {
696 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
697 reg = <0x02190000 0x4000>;
698 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
699 clocks = <&clks IMX6SL_CLK_USDHC1>,
700 <&clks IMX6SL_CLK_USDHC1>,
701 <&clks IMX6SL_CLK_USDHC1>;
702 clock-names = "ipg", "ahb", "per";
707 usdhc2: usdhc@02194000 {
708 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
709 reg = <0x02194000 0x4000>;
710 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
711 clocks = <&clks IMX6SL_CLK_USDHC2>,
712 <&clks IMX6SL_CLK_USDHC2>,
713 <&clks IMX6SL_CLK_USDHC2>;
714 clock-names = "ipg", "ahb", "per";
719 usdhc3: usdhc@02198000 {
720 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
721 reg = <0x02198000 0x4000>;
722 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
723 clocks = <&clks IMX6SL_CLK_USDHC3>,
724 <&clks IMX6SL_CLK_USDHC3>,
725 <&clks IMX6SL_CLK_USDHC3>;
726 clock-names = "ipg", "ahb", "per";
731 usdhc4: usdhc@0219c000 {
732 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
733 reg = <0x0219c000 0x4000>;
734 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
735 clocks = <&clks IMX6SL_CLK_USDHC4>,
736 <&clks IMX6SL_CLK_USDHC4>,
737 <&clks IMX6SL_CLK_USDHC4>;
738 clock-names = "ipg", "ahb", "per";
744 #address-cells = <1>;
746 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
747 reg = <0x021a0000 0x4000>;
748 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
749 clocks = <&clks IMX6SL_CLK_I2C1>;
754 #address-cells = <1>;
756 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
757 reg = <0x021a4000 0x4000>;
758 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
759 clocks = <&clks IMX6SL_CLK_I2C2>;
764 #address-cells = <1>;
766 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
767 reg = <0x021a8000 0x4000>;
768 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
769 clocks = <&clks IMX6SL_CLK_I2C3>;
773 mmdc: mmdc@021b0000 {
774 compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
775 reg = <0x021b0000 0x4000>;
778 rngb: rngb@021b4000 {
779 reg = <0x021b4000 0x4000>;
780 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
783 weim: weim@021b8000 {
784 reg = <0x021b8000 0x4000>;
785 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
788 ocotp: ocotp@021bc000 {
789 compatible = "fsl,imx6sl-ocotp";
790 reg = <0x021bc000 0x4000>;
793 audmux: audmux@021d8000 {
794 compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux";
795 reg = <0x021d8000 0x4000>;