2 * Device Tree for the ARM Integrator/AP platform
6 /include/ "integrator.dtsi"
9 model = "ARM Integrator/AP";
10 compatible = "arm,integrator-ap";
13 arm,timer-primary = &timer2;
14 arm,timer-secondary = &timer1;
18 bootargs = "root=/dev/ram0 console=ttyAM0,38400n8 earlyprintk";
21 /* 24 MHz chrystal on the core module */
22 xtal24mhz: xtal24mhz@24M {
24 compatible = "fixed-clock";
25 clock-frequency = <24000000>;
30 compatible = "fixed-factor-clock";
33 clocks = <&xtal24mhz>;
36 /* The UART clock is 14.74 MHz divided by an ICS525 */
37 uartclk: uartclk@14.74M {
39 compatible = "fixed-clock";
40 clock-frequency = <14745600>;
44 compatible = "arm,integrator-ap-syscon";
45 reg = <0x11000000 0x100>;
46 interrupt-parent = <&pic>;
47 /* These are the logical module IRQs */
48 interrupts = <9>, <10>, <11>, <12>;
51 timer0: timer@13000000 {
52 compatible = "arm,integrator-timer";
53 clocks = <&xtal24mhz>;
56 timer1: timer@13000100 {
57 compatible = "arm,integrator-timer";
58 clocks = <&xtal24mhz>;
61 timer2: timer@13000200 {
62 compatible = "arm,integrator-timer";
63 clocks = <&xtal24mhz>;
67 valid-mask = <0x003fffff>;
71 compatible = "v3,v360epc-pci";
72 #interrupt-cells = <1>;
75 reg = <0x62000000 0x10000>;
76 interrupt-parent = <&pic>;
77 interrupts = <17>; /* Bus error IRQ */
78 ranges = <0x00000000 0 0x61000000 /* config space */
79 0x61000000 0 0x00100000 /* 16 MiB @ 61000000 */
80 0x01000000 0 0x0 /* I/O space */
81 0x60000000 0 0x00100000 /* 16 MiB @ 60000000 */
82 0x02000000 0 0x00000000 /* non-prefectable memory */
83 0x40000000 0 0x10000000 /* 256 MiB @ 40000000 */
84 0x42000000 0 0x10000000 /* prefetchable memory */
85 0x50000000 0 0x10000000>; /* 256 MiB @ 50000000 */
86 interrupt-map-mask = <0xf800 0 0 0x7>;
89 0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */
90 0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */
91 0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */
92 0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */
94 0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */
95 0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */
96 0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */
97 0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */
99 0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */
100 0x5800 0 0 2 &pic 16 /* INT B on slot 11 is irq 16 */
101 0x5800 0 0 3 &pic 13 /* INT C on slot 11 is irq 13 */
102 0x5800 0 0 4 &pic 14 /* INT D on slot 11 is irq 14 */
104 0x6000 0 0 1 &pic 16 /* INT A on slot 12 is irq 16 */
105 0x6000 0 0 2 &pic 13 /* INT B on slot 12 is irq 13 */
106 0x6000 0 0 3 &pic 14 /* INT C on slot 12 is irq 14 */
107 0x6000 0 0 4 &pic 15 /* INT D on slot 12 is irq 15 */
113 * The Integator/AP predates the idea to have magic numbers
114 * identifying the PrimeCell in hardware, thus we have to
115 * supply these from the device tree.
118 compatible = "arm,pl030", "arm,primecell";
119 arm,primecell-periphid = <0x00041030>;
121 clock-names = "apb_pclk";
124 uart0: uart@16000000 {
125 compatible = "arm,pl010", "arm,primecell";
126 arm,primecell-periphid = <0x00041010>;
127 clocks = <&uartclk>, <&pclk>;
128 clock-names = "uartclk", "apb_pclk";
131 uart1: uart@17000000 {
132 compatible = "arm,pl010", "arm,primecell";
133 arm,primecell-periphid = <0x00041010>;
134 clocks = <&uartclk>, <&pclk>;
135 clock-names = "uartclk", "apb_pclk";
139 compatible = "arm,pl050", "arm,primecell";
140 arm,primecell-periphid = <0x00041050>;
141 clocks = <&xtal24mhz>, <&pclk>;
142 clock-names = "KMIREFCLK", "apb_pclk";
146 compatible = "arm,pl050", "arm,primecell";
147 arm,primecell-periphid = <0x00041050>;
148 clocks = <&xtal24mhz>, <&pclk>;
149 clock-names = "KMIREFCLK", "apb_pclk";