arch/arm/boot/dts/keystone-clocks.dtsi

   1 /*
   2  * Device Tree Source for Keystone 2 clock tree
   3  *
   4  * Copyright (C) 2013 Texas Instruments, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 clocks {
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14         ranges;
  15
  16         mainpllclk: mainpllclk@2310110 {
  17                 #clock-cells = <0>;
  18                 compatible = "ti,keystone,main-pll-clock";
  19                 clocks = <&refclksys>;
  20                 reg = <0x02620350 4>, <0x02310110 4>;
  21                 reg-names = "control", "multiplier";
  22                 fixed-postdiv = <2>;
  23         };
  24
  25         papllclk: papllclk@2620358 {
  26                 #clock-cells = <0>;
  27                 compatible = "ti,keystone,pll-clock";
  28                 clocks = <&refclkpass>;
  29                 clock-output-names = "pa-pll-clk";
  30                 reg = <0x02620358 4>;
  31                 reg-names = "control";
  32         };
  33
  34         ddr3apllclk: ddr3apllclk@2620360 {
  35                 #clock-cells = <0>;
  36                 compatible = "ti,keystone,pll-clock";
  37                 clocks = <&refclkddr3a>;
  38                 clock-output-names = "ddr-3a-pll-clk";
  39                 reg = <0x02620360 4>;
  40                 reg-names = "control";
  41         };
  42
  43         ddr3bpllclk: ddr3bpllclk@2620368 {
  44                 #clock-cells = <0>;
  45                 compatible = "ti,keystone,pll-clock";
  46                 clocks = <&refclkddr3b>;
  47                 clock-output-names = "ddr-3b-pll-clk";
  48                 reg = <0x02620368 4>;
  49                 reg-names = "control";
  50         };
  51
  52         armpllclk: armpllclk@2620370 {
  53                 #clock-cells = <0>;
  54                 compatible = "ti,keystone,pll-clock";
  55                 clocks = <&refclkarm>;
  56                 clock-output-names = "arm-pll-clk";
  57                 reg = <0x02620370 4>;
  58                 reg-names = "control";
  59         };
  60
  61         mainmuxclk: mainmuxclk@2310108 {
  62                 #clock-cells = <0>;
  63                 compatible = "ti,keystone,pll-mux-clock";
  64                 clocks = <&mainpllclk>, <&refclksys>;
  65                 reg = <0x02310108 4>;
  66                 bit-shift = <23>;
  67                 bit-mask = <1>;
  68                 clock-output-names = "mainmuxclk";
  69         };
  70
  71         chipclk1: chipclk1 {
  72                 #clock-cells = <0>;
  73                 compatible = "fixed-factor-clock";
  74                 clocks = <&mainmuxclk>;
  75                 clock-div = <1>;
  76                 clock-mult = <1>;
  77                 clock-output-names = "chipclk1";
  78         };
  79
  80         chipclk1rstiso: chipclk1rstiso {
  81                 #clock-cells = <0>;
  82                 compatible = "fixed-factor-clock";
  83                 clocks = <&mainmuxclk>;
  84                 clock-div = <1>;
  85                 clock-mult = <1>;
  86                 clock-output-names = "chipclk1rstiso";
  87         };
  88
  89         gemtraceclk: gemtraceclk@2310120 {
  90                 #clock-cells = <0>;
  91                 compatible = "ti,keystone,pll-divider-clock";
  92                 clocks = <&mainmuxclk>;
  93                 reg = <0x02310120 4>;
  94                 bit-shift = <0>;
  95                 bit-mask = <8>;
  96                 clock-output-names = "gemtraceclk";
  97         };
  98
  99         chipstmxptclk: chipstmxptclk {
 100                 #clock-cells = <0>;
 101                 compatible = "ti,keystone,pll-divider-clock";
 102                 clocks = <&mainmuxclk>;
 103                 reg = <0x02310164 4>;
 104                 bit-shift = <0>;
 105                 bit-mask = <8>;
 106                 clock-output-names = "chipstmxptclk";
 107         };
 108
 109         chipclk12: chipclk12 {
 110                 #clock-cells = <0>;
 111                 compatible = "fixed-factor-clock";
 112                 clocks = <&chipclk1>;
 113                 clock-div = <2>;
 114                 clock-mult = <1>;
 115                 clock-output-names = "chipclk12";
 116         };
 117
 118         chipclk13: chipclk13 {
 119                 #clock-cells = <0>;
 120                 compatible = "fixed-factor-clock";
 121                 clocks = <&chipclk1>;
 122                 clock-div = <3>;
 123                 clock-mult = <1>;
 124                 clock-output-names = "chipclk13";
 125         };
 126
 127         chipclk14: chipclk14 {
 128                 #clock-cells = <0>;
 129                 compatible = "fixed-factor-clock";
 130                 clocks = <&chipclk1>;
 131                 clock-div = <4>;
 132                 clock-mult = <1>;
 133                 clock-output-names = "chipclk14";
 134         };
 135
 136         chipclk16: chipclk16 {
 137                 #clock-cells = <0>;
 138                 compatible = "fixed-factor-clock";
 139                 clocks = <&chipclk1>;
 140                 clock-div = <6>;
 141                 clock-mult = <1>;
 142                 clock-output-names = "chipclk16";
 143         };
 144
 145         chipclk112: chipclk112 {
 146                 #clock-cells = <0>;
 147                 compatible = "fixed-factor-clock";
 148                 clocks = <&chipclk1>;
 149                 clock-div = <12>;
 150                 clock-mult = <1>;
 151                 clock-output-names = "chipclk112";
 152         };
 153
 154         chipclk124: chipclk124 {
 155                 #clock-cells = <0>;
 156                 compatible = "fixed-factor-clock";
 157                 clocks = <&chipclk1>;
 158                 clock-div = <24>;
 159                 clock-mult = <1>;
 160                 clock-output-names = "chipclk114";
 161         };
 162
 163         chipclk1rstiso13: chipclk1rstiso13 {
 164                 #clock-cells = <0>;
 165                 compatible = "fixed-factor-clock";
 166                 clocks = <&chipclk1rstiso>;
 167                 clock-div = <3>;
 168                 clock-mult = <1>;
 169                 clock-output-names = "chipclk1rstiso13";
 170         };
 171
 172         chipclk1rstiso14: chipclk1rstiso14 {
 173                 #clock-cells = <0>;
 174                 compatible = "fixed-factor-clock";
 175                 clocks = <&chipclk1rstiso>;
 176                 clock-div = <4>;
 177                 clock-mult = <1>;
 178                 clock-output-names = "chipclk1rstiso14";
 179         };
 180
 181         chipclk1rstiso16: chipclk1rstiso16 {
 182                 #clock-cells = <0>;
 183                 compatible = "fixed-factor-clock";
 184                 clocks = <&chipclk1rstiso>;
 185                 clock-div = <6>;
 186                 clock-mult = <1>;
 187                 clock-output-names = "chipclk1rstiso16";
 188         };
 189
 190         chipclk1rstiso112: chipclk1rstiso112 {
 191                 #clock-cells = <0>;
 192                 compatible = "fixed-factor-clock";
 193                 clocks = <&chipclk1rstiso>;
 194                 clock-div = <12>;
 195                 clock-mult = <1>;
 196                 clock-output-names = "chipclk1rstiso112";
 197         };
 198
 199         clkmodrst0: clkmodrst0 {
 200                 #clock-cells = <0>;
 201                 compatible = "ti,keystone,psc-clock";
 202                 clocks = <&chipclk16>;
 203                 clock-output-names = "modrst0";
 204                 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
 205                 reg-names = "control", "domain";
 206                 domain-id = <0>;
 207         };
 208
 209
 210         clkusb: clkusb {
 211                 #clock-cells = <0>;
 212                 compatible = "ti,keystone,psc-clock";
 213                 clocks = <&chipclk16>;
 214                 clock-output-names = "usb";
 215                 reg = <0x02350008 0xb00>, <0x02350000 0x400>;
 216                 reg-names = "control", "domain";
 217                 domain-id = <0>;
 218         };
 219
 220         clkaemifspi: clkaemifspi {
 221                 #clock-cells = <0>;
 222                 compatible = "ti,keystone,psc-clock";
 223                 clocks = <&chipclk16>;
 224                 clock-output-names = "aemif-spi";
 225                 reg = <0x0235000c 0xb00>, <0x02350000 0x400>;
 226                 reg-names = "control", "domain";
 227                 domain-id = <0>;
 228         };
 229
 230
 231         clkdebugsstrc: clkdebugsstrc {
 232                 #clock-cells = <0>;
 233                 compatible = "ti,keystone,psc-clock";
 234                 clocks = <&chipclk13>;
 235                 clock-output-names = "debugss-trc";
 236                 reg = <0x02350014 0xb00>, <0x02350000 0x400>;
 237                 reg-names = "control", "domain";
 238                 domain-id = <0>;
 239         };
 240
 241         clktetbtrc: clktetbtrc {
 242                 #clock-cells = <0>;
 243                 compatible = "ti,keystone,psc-clock";
 244                 clocks = <&chipclk13>;
 245                 clock-output-names = "tetb-trc";
 246                 reg = <0x02350018 0xb00>, <0x02350004 0x400>;
 247                 reg-names = "control", "domain";
 248                 domain-id = <1>;
 249         };
 250
 251         clkpa: clkpa {
 252                 #clock-cells = <0>;
 253                 compatible = "ti,keystone,psc-clock";
 254                 clocks = <&chipclk16>;
 255                 clock-output-names = "pa";
 256                 reg = <0x0235001c 0xb00>, <0x02350008 0x400>;
 257                 reg-names = "control", "domain";
 258                 domain-id = <2>;
 259         };
 260
 261         clkcpgmac: clkcpgmac {
 262                 #clock-cells = <0>;
 263                 compatible = "ti,keystone,psc-clock";
 264                 clocks = <&clkpa>;
 265                 clock-output-names = "cpgmac";
 266                 reg = <0x02350020 0xb00>, <0x02350008 0x400>;
 267                 reg-names = "control", "domain";
 268                 domain-id = <2>;
 269         };
 270
 271         clksa: clksa {
 272                 #clock-cells = <0>;
 273                 compatible = "ti,keystone,psc-clock";
 274                 clocks = <&clkpa>;
 275                 clock-output-names = "sa";
 276                 reg = <0x02350024 0xb00>, <0x02350008 0x400>;
 277                 reg-names = "control", "domain";
 278                 domain-id = <2>;
 279         };
 280
 281         clkpcie: clkpcie {
 282                 #clock-cells = <0>;
 283                 compatible = "ti,keystone,psc-clock";
 284                 clocks = <&chipclk12>;
 285                 clock-output-names = "pcie";
 286                 reg = <0x02350028 0xb00>, <0x0235000c 0x400>;
 287                 reg-names = "control", "domain";
 288                 domain-id = <3>;
 289         };
 290
 291         clksrio: clksrio {
 292                 #clock-cells = <0>;
 293                 compatible = "ti,keystone,psc-clock";
 294                 clocks = <&chipclk1rstiso13>;
 295                 clock-output-names = "srio";
 296                 reg = <0x0235002c 0xb00>, <0x02350010 0x400>;
 297                 reg-names = "control", "domain";
 298                 domain-id = <4>;
 299         };
 300
 301         clkhyperlink0: clkhyperlink0 {
 302                 #clock-cells = <0>;
 303                 compatible = "ti,keystone,psc-clock";
 304                 clocks = <&chipclk12>;
 305                 clock-output-names = "hyperlink-0";
 306                 reg = <0x02350030 0xb00>, <0x02350014 0x400>;
 307                 reg-names = "control", "domain";
 308                 domain-id = <5>;
 309         };
 310
 311         clksr: clksr {
 312                 #clock-cells = <0>;
 313                 compatible = "ti,keystone,psc-clock";
 314                 clocks = <&chipclk1rstiso112>;
 315                 clock-output-names = "sr";
 316                 reg = <0x02350034 0xb00>, <0x02350018 0x400>;
 317                 reg-names = "control", "domain";
 318                 domain-id = <6>;
 319         };
 320
 321         clkmsmcsram: clkmsmcsram {
 322                 #clock-cells = <0>;
 323                 compatible = "ti,keystone,psc-clock";
 324                 clocks = <&chipclk1>;
 325                 clock-output-names = "msmcsram";
 326                 reg = <0x02350038 0xb00>, <0x0235001c 0x400>;
 327                 reg-names = "control", "domain";
 328                 domain-id = <7>;
 329         };
 330
 331         clkgem0: clkgem0 {
 332                 #clock-cells = <0>;
 333                 compatible = "ti,keystone,psc-clock";
 334                 clocks = <&chipclk1>;
 335                 clock-output-names = "gem0";
 336                 reg = <0x0235003c 0xb00>, <0x02350020 0x400>;
 337                 reg-names = "control", "domain";
 338                 domain-id = <8>;
 339         };
 340
 341         clkgem1: clkgem1 {
 342                 #clock-cells = <0>;
 343                 compatible = "ti,keystone,psc-clock";
 344                 clocks = <&chipclk1>;
 345                 clock-output-names = "gem1";
 346                 reg = <0x02350040 0xb00>, <0x02350024 0x400>;
 347                 reg-names = "control", "domain";
 348                 domain-id = <9>;
 349         };
 350
 351         clkgem2: clkgem2 {
 352                 #clock-cells = <0>;
 353                 compatible = "ti,keystone,psc-clock";
 354                 clocks = <&chipclk1>;
 355                 clock-output-names = "gem2";
 356                 reg = <0x02350044 0xb00>, <0x02350028 0x400>;
 357                 reg-names = "control", "domain";
 358                 domain-id = <10>;
 359         };
 360
 361         clkgem3: clkgem3 {
 362                 #clock-cells = <0>;
 363                 compatible = "ti,keystone,psc-clock";
 364                 clocks = <&chipclk1>;
 365                 clock-output-names = "gem3";
 366                 reg = <0x02350048 0xb00>, <0x0235002c 0x400>;
 367                 reg-names = "control", "domain";
 368                 domain-id = <11>;
 369         };
 370
 371         clkgem4: clkgem4 {
 372                 #clock-cells = <0>;
 373                 compatible = "ti,keystone,psc-clock";
 374                 clocks = <&chipclk1>;
 375                 clock-output-names = "gem4";
 376                 reg = <0x0235004c 0xb00>, <0x02350030 0x400>;
 377                 reg-names = "control", "domain";
 378                 domain-id = <12>;
 379         };
 380
 381         clkgem5: clkgem5 {
 382                 #clock-cells = <0>;
 383                 compatible = "ti,keystone,psc-clock";
 384                 clocks = <&chipclk1>;
 385                 clock-output-names = "gem5";
 386                 reg = <0x02350050 0xb00>, <0x02350034 0x400>;
 387                 reg-names = "control", "domain";
 388                 domain-id = <13>;
 389         };
 390
 391         clkgem6: clkgem6 {
 392                 #clock-cells = <0>;
 393                 compatible = "ti,keystone,psc-clock";
 394                 clocks = <&chipclk1>;
 395                 clock-output-names = "gem6";
 396                 reg = <0x02350054 0xb00>, <0x02350038 0x400>;
 397                 reg-names = "control", "domain";
 398                 domain-id = <14>;
 399         };
 400
 401         clkgem7: clkgem7 {
 402                 #clock-cells = <0>;
 403                 compatible = "ti,keystone,psc-clock";
 404                 clocks = <&chipclk1>;
 405                 clock-output-names = "gem7";
 406                 reg = <0x02350058 0xb00>, <0x0235003c 0x400>;
 407                 reg-names = "control", "domain";
 408                 domain-id = <15>;
 409         };
 410
 411         clkddr30: clkddr30 {
 412                 #clock-cells = <0>;
 413                 compatible = "ti,keystone,psc-clock";
 414                 clocks = <&chipclk12>;
 415                 clock-output-names = "ddr3-0";
 416                 reg = <0x0235005c 0xb00>, <0x02350040 0x400>;
 417                 reg-names = "control", "domain";
 418                 domain-id = <16>;
 419         };
 420
 421         clkddr31: clkddr31 {
 422                 #clock-cells = <0>;
 423                 compatible = "ti,keystone,psc-clock";
 424                 clocks = <&chipclk13>;
 425                 clock-output-names = "ddr3-1";
 426                 reg = <0x02350060 0xb00>, <0x02350040 0x400>;
 427                 reg-names = "control", "domain";
 428                 domain-id = <16>;
 429         };
 430
 431         clktac: clktac {
 432                 #clock-cells = <0>;
 433                 compatible = "ti,keystone,psc-clock";
 434                 clocks = <&chipclk13>;
 435                 clock-output-names = "tac";
 436                 reg = <0x02350064 0xb00>, <0x02350044 0x400>;
 437                 reg-names = "control", "domain";
 438                 domain-id = <17>;
 439         };
 440
 441         clkrac01: clktac01 {
 442                 #clock-cells = <0>;
 443                 compatible = "ti,keystone,psc-clock";
 444                 clocks = <&chipclk13>;
 445                 clock-output-names = "rac-01";
 446                 reg = <0x02350068 0xb00>, <0x02350044 0x400>;
 447                 reg-names = "control", "domain";
 448                 domain-id = <17>;
 449         };
 450
 451         clkrac23: clktac23 {
 452                 #clock-cells = <0>;
 453                 compatible = "ti,keystone,psc-clock";
 454                 clocks = <&chipclk13>;
 455                 clock-output-names = "rac-23";
 456                 reg = <0x0235006c 0xb00>, <0x02350048 0x400>;
 457                 reg-names = "control", "domain";
 458                 domain-id = <18>;
 459         };
 460
 461         clkfftc0: clkfftc0 {
 462                 #clock-cells = <0>;
 463                 compatible = "ti,keystone,psc-clock";
 464                 clocks = <&chipclk13>;
 465                 clock-output-names = "fftc-0";
 466                 reg = <0x02350070 0xb00>, <0x0235004c 0x400>;
 467                 reg-names = "control", "domain";
 468                 domain-id = <19>;
 469         };
 470
 471         clkfftc1: clkfftc1 {
 472                 #clock-cells = <0>;
 473                 compatible = "ti,keystone,psc-clock";
 474                 clocks = <&chipclk13>;
 475                 clock-output-names = "fftc-1";
 476                 reg = <0x02350074 0xb00>, <0x023504c0 0x400>;
 477                 reg-names = "control", "domain";
 478                 domain-id = <19>;
 479         };
 480
 481         clkfftc2: clkfftc2 {
 482                 #clock-cells = <0>;
 483                 compatible = "ti,keystone,psc-clock";
 484                 clocks = <&chipclk13>;
 485                 clock-output-names = "fftc-2";
 486                 reg = <0x02350078 0xb00>, <0x02350050 0x400>;
 487                 reg-names = "control", "domain";
 488                 domain-id = <20>;
 489         };
 490
 491         clkfftc3: clkfftc3 {
 492                 #clock-cells = <0>;
 493                 compatible = "ti,keystone,psc-clock";
 494                 clocks = <&chipclk13>;
 495                 clock-output-names = "fftc-3";
 496                 reg = <0x0235007c 0xb00>, <0x02350050 0x400>;
 497                 reg-names = "control", "domain";
 498                 domain-id = <20>;
 499         };
 500
 501         clkfftc4: clkfftc4 {
 502                 #clock-cells = <0>;
 503                 compatible = "ti,keystone,psc-clock";
 504                 clocks = <&chipclk13>;
 505                 clock-output-names = "fftc-4";
 506                 reg = <0x02350080 0xb00>, <0x02350050 0x400>;
 507                 reg-names = "control", "domain";
 508                 domain-id = <20>;
 509         };
 510
 511         clkfftc5: clkfftc5 {
 512                 #clock-cells = <0>;
 513                 compatible = "ti,keystone,psc-clock";
 514                 clocks = <&chipclk13>;
 515                 clock-output-names = "fftc-5";
 516                 reg = <0x02350084 0xb00>, <0x02350050 0x400>;
 517                 reg-names = "control", "domain";
 518                 domain-id = <20>;
 519         };
 520
 521         clkaif: clkaif {
 522                 #clock-cells = <0>;
 523                 compatible = "ti,keystone,psc-clock";
 524                 clocks = <&chipclk13>;
 525                 clock-output-names = "aif";
 526                 reg = <0x02350088 0xb00>, <0x02350054 0x400>;
 527                 reg-names = "control", "domain";
 528                 domain-id = <21>;
 529         };
 530
 531         clktcp3d0: clktcp3d0 {
 532                 #clock-cells = <0>;
 533                 compatible = "ti,keystone,psc-clock";
 534                 clocks = <&chipclk13>;
 535                 clock-output-names = "tcp3d-0";
 536                 reg = <0x0235008c 0xb00>, <0x02350058 0x400>;
 537                 reg-names = "control", "domain";
 538                 domain-id = <22>;
 539         };
 540
 541         clktcp3d1: clktcp3d1 {
 542                 #clock-cells = <0>;
 543                 compatible = "ti,keystone,psc-clock";
 544                 clocks = <&chipclk13>;
 545                 clock-output-names = "tcp3d-1";
 546                 reg = <0x02350090 0xb00>, <0x02350058 0x400>;
 547                 reg-names = "control", "domain";
 548                 domain-id = <22>;
 549         };
 550
 551         clktcp3d2: clktcp3d2 {
 552                 #clock-cells = <0>;
 553                 compatible = "ti,keystone,psc-clock";
 554                 clocks = <&chipclk13>;
 555                 clock-output-names = "tcp3d-2";
 556                 reg = <0x02350094 0xb00>, <0x0235005c 0x400>;
 557                 reg-names = "control", "domain";
 558                 domain-id = <23>;
 559         };
 560
 561         clktcp3d3: clktcp3d3 {
 562                 #clock-cells = <0>;
 563                 compatible = "ti,keystone,psc-clock";
 564                 clocks = <&chipclk13>;
 565                 clock-output-names = "tcp3d-3";
 566                 reg = <0x02350098 0xb00>, <0x0235005c 0x400>;
 567                 reg-names = "control", "domain";
 568                 domain-id = <23>;
 569         };
 570
 571         clkvcp0: clkvcp0 {
 572                 #clock-cells = <0>;
 573                 compatible = "ti,keystone,psc-clock";
 574                 clocks = <&chipclk13>;
 575                 clock-output-names = "vcp-0";
 576                 reg = <0x0235009c 0xb00>, <0x02350060 0x400>;
 577                 reg-names = "control", "domain";
 578                 domain-id = <24>;
 579         };
 580
 581         clkvcp1: clkvcp1 {
 582                 #clock-cells = <0>;
 583                 compatible = "ti,keystone,psc-clock";
 584                 clocks = <&chipclk13>;
 585                 clock-output-names = "vcp-1";
 586                 reg = <0x023500a0 0xb00>, <0x02350060 0x400>;
 587                 reg-names = "control", "domain";
 588                 domain-id = <24>;
 589         };
 590
 591         clkvcp2: clkvcp2 {
 592                 #clock-cells = <0>;
 593                 compatible = "ti,keystone,psc-clock";
 594                 clocks = <&chipclk13>;
 595                 clock-output-names = "vcp-2";
 596                 reg = <0x023500a4 0xb00>, <0x02350060 0x400>;
 597                 reg-names = "control", "domain";
 598                 domain-id = <24>;
 599         };
 600
 601         clkvcp3: clkvcp3 {
 602                 #clock-cells = <0>;
 603                 compatible = "ti,keystone,psc-clock";
 604                 clocks = <&chipclk13>;
 605                 clock-output-names = "vcp-3";
 606                 reg = <0x0235000a8 0xb00>, <0x02350060 0x400>;
 607                 reg-names = "control", "domain";
 608                 domain-id = <24>;
 609         };
 610
 611         clkvcp4: clkvcp4 {
 612                 #clock-cells = <0>;
 613                 compatible = "ti,keystone,psc-clock";
 614                 clocks = <&chipclk13>;
 615                 clock-output-names = "vcp-4";
 616                 reg = <0x023500ac 0xb00>, <0x02350064 0x400>;
 617                 reg-names = "control", "domain";
 618                 domain-id = <25>;
 619         };
 620
 621         clkvcp5: clkvcp5 {
 622                 #clock-cells = <0>;
 623                 compatible = "ti,keystone,psc-clock";
 624                 clocks = <&chipclk13>;
 625                 clock-output-names = "vcp-5";
 626                 reg = <0x023500b0 0xb00>, <0x02350064 0x400>;
 627                 reg-names = "control", "domain";
 628                 domain-id = <25>;
 629         };
 630
 631         clkvcp6: clkvcp6 {
 632                 #clock-cells = <0>;
 633                 compatible = "ti,keystone,psc-clock";
 634                 clocks = <&chipclk13>;
 635                 clock-output-names = "vcp-6";
 636                 reg = <0x023500b4 0xb00>, <0x02350064 0x400>;
 637                 reg-names = "control", "domain";
 638                 domain-id = <25>;
 639         };
 640
 641         clkvcp7: clkvcp7 {
 642                 #clock-cells = <0>;
 643                 compatible = "ti,keystone,psc-clock";
 644                 clocks = <&chipclk13>;
 645                 clock-output-names = "vcp-7";
 646                 reg = <0x023500b8 0xb00>, <0x02350064 0x400>;
 647                 reg-names = "control", "domain";
 648                 domain-id = <25>;
 649         };
 650
 651         clkbcp: clkbcp {
 652                 #clock-cells = <0>;
 653                 compatible = "ti,keystone,psc-clock";
 654                 clocks = <&chipclk13>;
 655                 clock-output-names = "bcp";
 656                 reg = <0x023500bc 0xb00>, <0x02350068 0x400>;
 657                 reg-names = "control", "domain";
 658                 domain-id = <26>;
 659         };
 660
 661         clkdxb: clkdxb {
 662                 #clock-cells = <0>;
 663                 compatible = "ti,keystone,psc-clock";
 664                 clocks = <&chipclk13>;
 665                 clock-output-names = "dxb";
 666                 reg = <0x023500c0 0xb00>, <0x0235006c 0x400>;
 667                 reg-names = "control", "domain";
 668                 domain-id = <27>;
 669         };
 670
 671         clkhyperlink1: clkhyperlink1 {
 672                 #clock-cells = <0>;
 673                 compatible = "ti,keystone,psc-clock";
 674                 clocks = <&chipclk12>;
 675                 clock-output-names = "hyperlink-1";
 676                 reg = <0x023500c4 0xb00>, <0x02350070 0x400>;
 677                 reg-names = "control", "domain";
 678                 domain-id = <28>;
 679         };
 680
 681         clkxge: clkxge {
 682                 #clock-cells = <0>;
 683                 compatible = "ti,keystone,psc-clock";
 684                 clocks = <&chipclk13>;
 685                 clock-output-names = "xge";
 686                 reg = <0x023500c8 0xb00>, <0x02350074 0x400>;
 687                 reg-names = "control", "domain";
 688                 domain-id = <29>;
 689         };
 690
 691         clkwdtimer0: clkwdtimer0 {
 692                 #clock-cells = <0>;
 693                 compatible = "ti,keystone,psc-clock";
 694                 clocks = <&clkmodrst0>;
 695                 clock-output-names = "timer0";
 696                 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
 697                 reg-names = "control", "domain";
 698                 domain-id = <0>;
 699         };
 700
 701         clkwdtimer1: clkwdtimer1 {
 702                 #clock-cells = <0>;
 703                 compatible = "ti,keystone,psc-clock";
 704                 clocks = <&clkmodrst0>;
 705                 clock-output-names = "timer1";
 706                 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
 707                 reg-names = "control", "domain";
 708                 domain-id = <0>;
 709         };
 710
 711         clkwdtimer2: clkwdtimer2 {
 712                 #clock-cells = <0>;
 713                 compatible = "ti,keystone,psc-clock";
 714                 clocks = <&clkmodrst0>;
 715                 clock-output-names = "timer2";
 716                 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
 717                 reg-names = "control", "domain";
 718                 domain-id = <0>;
 719         };
 720
 721         clkwdtimer3: clkwdtimer3 {
 722                 #clock-cells = <0>;
 723                 compatible = "ti,keystone,psc-clock";
 724                 clocks = <&clkmodrst0>;
 725                 clock-output-names = "timer3";
 726                 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
 727                 reg-names = "control", "domain";
 728                 domain-id = <0>;
 729         };
 730
 731         clkuart0: clkuart0 {
 732                 #clock-cells = <0>;
 733                 compatible = "ti,keystone,psc-clock";
 734                 clocks = <&clkmodrst0>;
 735                 clock-output-names = "uart0";
 736                 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
 737                 reg-names = "control", "domain";
 738                 domain-id = <0>;
 739         };
 740
 741         clkuart1: clkuart1 {
 742                 #clock-cells = <0>;
 743                 compatible = "ti,keystone,psc-clock";
 744                 clocks = <&clkmodrst0>;
 745                 clock-output-names = "uart1";
 746                 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
 747                 reg-names = "control", "domain";
 748                 domain-id = <0>;
 749         };
 750
 751         clkaemif: clkaemif {
 752                 #clock-cells = <0>;
 753                 compatible = "ti,keystone,psc-clock";
 754                 clocks = <&clkaemifspi>;
 755                 clock-output-names = "aemif";
 756                 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
 757                 reg-names = "control", "domain";
 758                 domain-id = <0>;
 759         };
 760
 761         clkusim: clkusim {
 762                 #clock-cells = <0>;
 763                 compatible = "ti,keystone,psc-clock";
 764                 clocks = <&clkmodrst0>;
 765                 clock-output-names = "usim";
 766                 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
 767                 reg-names = "control", "domain";
 768                 domain-id = <0>;
 769         };
 770
 771         clki2c: clki2c {
 772                 #clock-cells = <0>;
 773                 compatible = "ti,keystone,psc-clock";
 774                 clocks = <&clkmodrst0>;
 775                 clock-output-names = "i2c";
 776                 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
 777                 reg-names = "control", "domain";
 778                 domain-id = <0>;
 779         };
 780
 781         clkspi: clkspi {
 782                 #clock-cells = <0>;
 783                 compatible = "ti,keystone,psc-clock";
 784                 clocks = <&clkaemifspi>;
 785                 clock-output-names = "spi";
 786                 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
 787                 reg-names = "control", "domain";
 788                 domain-id = <0>;
 789         };
 790
 791         clkgpio: clkgpio {
 792                 #clock-cells = <0>;
 793                 compatible = "ti,keystone,psc-clock";
 794                 clocks = <&clkmodrst0>;
 795                 clock-output-names = "gpio";
 796                 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
 797                 reg-names = "control", "domain";
 798                 domain-id = <0>;
 799         };
 800
 801         clkkeymgr: clkkeymgr {
 802                 #clock-cells = <0>;
 803                 compatible = "ti,keystone,psc-clock";
 804                 clocks = <&clkmodrst0>;
 805                 clock-output-names = "keymgr";
 806                 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
 807                 reg-names = "control", "domain";
 808                 domain-id = <0>;
 809         };
 810 };